1 //===-- RegisterContextDarwin_i386.cpp --------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10
11 // C Includes
12 #include <stddef.h> // offsetof
13
14 // C++ Includes
15 // Other libraries and framework includes
16 #include "lldb/Core/DataBufferHeap.h"
17 #include "lldb/Core/DataExtractor.h"
18 #include "lldb/Core/Log.h"
19 #include "lldb/Core/RegisterValue.h"
20 #include "lldb/Core/Scalar.h"
21 #include "lldb/Host/Endian.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/Support/Compiler.h"
24
25 // Support building against older versions of LLVM, this macro was added
26 // recently.
27 #ifndef LLVM_EXTENSION
28 #define LLVM_EXTENSION
29 #endif
30
31 // Project includes
32 #include "RegisterContextDarwin_i386.h"
33
34 using namespace lldb;
35 using namespace lldb_private;
36
37 enum
38 {
39 gpr_eax = 0,
40 gpr_ebx,
41 gpr_ecx,
42 gpr_edx,
43 gpr_edi,
44 gpr_esi,
45 gpr_ebp,
46 gpr_esp,
47 gpr_ss,
48 gpr_eflags,
49 gpr_eip,
50 gpr_cs,
51 gpr_ds,
52 gpr_es,
53 gpr_fs,
54 gpr_gs,
55
56 fpu_fcw,
57 fpu_fsw,
58 fpu_ftw,
59 fpu_fop,
60 fpu_ip,
61 fpu_cs,
62 fpu_dp,
63 fpu_ds,
64 fpu_mxcsr,
65 fpu_mxcsrmask,
66 fpu_stmm0,
67 fpu_stmm1,
68 fpu_stmm2,
69 fpu_stmm3,
70 fpu_stmm4,
71 fpu_stmm5,
72 fpu_stmm6,
73 fpu_stmm7,
74 fpu_xmm0,
75 fpu_xmm1,
76 fpu_xmm2,
77 fpu_xmm3,
78 fpu_xmm4,
79 fpu_xmm5,
80 fpu_xmm6,
81 fpu_xmm7,
82
83 exc_trapno,
84 exc_err,
85 exc_faultvaddr,
86
87 k_num_registers,
88
89 // Aliases
90 fpu_fctrl = fpu_fcw,
91 fpu_fstat = fpu_fsw,
92 fpu_ftag = fpu_ftw,
93 fpu_fiseg = fpu_cs,
94 fpu_fioff = fpu_ip,
95 fpu_foseg = fpu_ds,
96 fpu_fooff = fpu_dp
97 };
98
99 enum
100 {
101 gcc_eax = 0,
102 gcc_ecx,
103 gcc_edx,
104 gcc_ebx,
105 gcc_ebp,
106 gcc_esp,
107 gcc_esi,
108 gcc_edi,
109 gcc_eip,
110 gcc_eflags
111 };
112
113 enum
114 {
115 dwarf_eax = 0,
116 dwarf_ecx,
117 dwarf_edx,
118 dwarf_ebx,
119 dwarf_esp,
120 dwarf_ebp,
121 dwarf_esi,
122 dwarf_edi,
123 dwarf_eip,
124 dwarf_eflags,
125 dwarf_stmm0 = 11,
126 dwarf_stmm1,
127 dwarf_stmm2,
128 dwarf_stmm3,
129 dwarf_stmm4,
130 dwarf_stmm5,
131 dwarf_stmm6,
132 dwarf_stmm7,
133 dwarf_xmm0 = 21,
134 dwarf_xmm1,
135 dwarf_xmm2,
136 dwarf_xmm3,
137 dwarf_xmm4,
138 dwarf_xmm5,
139 dwarf_xmm6,
140 dwarf_xmm7
141 };
142
143 enum
144 {
145 gdb_eax = 0,
146 gdb_ecx = 1,
147 gdb_edx = 2,
148 gdb_ebx = 3,
149 gdb_esp = 4,
150 gdb_ebp = 5,
151 gdb_esi = 6,
152 gdb_edi = 7,
153 gdb_eip = 8,
154 gdb_eflags = 9,
155 gdb_cs = 10,
156 gdb_ss = 11,
157 gdb_ds = 12,
158 gdb_es = 13,
159 gdb_fs = 14,
160 gdb_gs = 15,
161 gdb_stmm0 = 16,
162 gdb_stmm1 = 17,
163 gdb_stmm2 = 18,
164 gdb_stmm3 = 19,
165 gdb_stmm4 = 20,
166 gdb_stmm5 = 21,
167 gdb_stmm6 = 22,
168 gdb_stmm7 = 23,
169 gdb_fctrl = 24, gdb_fcw = gdb_fctrl,
170 gdb_fstat = 25, gdb_fsw = gdb_fstat,
171 gdb_ftag = 26, gdb_ftw = gdb_ftag,
172 gdb_fiseg = 27, gdb_fpu_cs = gdb_fiseg,
173 gdb_fioff = 28, gdb_ip = gdb_fioff,
174 gdb_foseg = 29, gdb_fpu_ds = gdb_foseg,
175 gdb_fooff = 30, gdb_dp = gdb_fooff,
176 gdb_fop = 31,
177 gdb_xmm0 = 32,
178 gdb_xmm1 = 33,
179 gdb_xmm2 = 34,
180 gdb_xmm3 = 35,
181 gdb_xmm4 = 36,
182 gdb_xmm5 = 37,
183 gdb_xmm6 = 38,
184 gdb_xmm7 = 39,
185 gdb_mxcsr = 40,
186 gdb_mm0 = 41,
187 gdb_mm1 = 42,
188 gdb_mm2 = 43,
189 gdb_mm3 = 44,
190 gdb_mm4 = 45,
191 gdb_mm5 = 46,
192 gdb_mm6 = 47,
193 gdb_mm7 = 48
194 };
195
RegisterContextDarwin_i386(Thread & thread,uint32_t concrete_frame_idx)196 RegisterContextDarwin_i386::RegisterContextDarwin_i386 (Thread &thread, uint32_t concrete_frame_idx) :
197 RegisterContext(thread, concrete_frame_idx),
198 gpr(),
199 fpu(),
200 exc()
201 {
202 uint32_t i;
203 for (i=0; i<kNumErrors; i++)
204 {
205 gpr_errs[i] = -1;
206 fpu_errs[i] = -1;
207 exc_errs[i] = -1;
208 }
209 }
210
~RegisterContextDarwin_i386()211 RegisterContextDarwin_i386::~RegisterContextDarwin_i386()
212 {
213 }
214
215
216
217 #define GPR_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_i386::GPR, reg))
218 #define FPU_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_i386::FPU, reg) + sizeof (RegisterContextDarwin_i386::GPR))
219 #define EXC_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_i386::EXC, reg) + sizeof (RegisterContextDarwin_i386::GPR) + sizeof (RegisterContextDarwin_i386::FPU))
220
221 // These macros will auto define the register name, alt name, register size,
222 // register offset, encoding, format and native register. This ensures that
223 // the register state structures are defined correctly and have the correct
224 // sizes and offsets.
225 #define DEFINE_GPR(reg, alt) #reg, alt, sizeof(((RegisterContextDarwin_i386::GPR *)NULL)->reg), GPR_OFFSET(reg), eEncodingUint, eFormatHex
226 #define DEFINE_FPU_UINT(reg) #reg, NULL, sizeof(((RegisterContextDarwin_i386::FPU *)NULL)->reg), FPU_OFFSET(reg), eEncodingUint, eFormatHex
227 #define DEFINE_FPU_VECT(reg, i) #reg#i, NULL, sizeof(((RegisterContextDarwin_i386::FPU *)NULL)->reg[i].bytes), FPU_OFFSET(reg[i]), eEncodingVector, eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_##reg##i, LLDB_INVALID_REGNUM, gdb_##reg##i, fpu_##reg##i }, NULL, NULL
228
229 #define DEFINE_EXC(reg) #reg, NULL, sizeof(((RegisterContextDarwin_i386::EXC *)NULL)->reg), EXC_OFFSET(reg), eEncodingUint, eFormatHex
230 #define REG_CONTEXT_SIZE (sizeof (RegisterContextDarwin_i386::GPR) + sizeof (RegisterContextDarwin_i386::FPU) + sizeof (RegisterContextDarwin_i386::EXC))
231
232 static RegisterInfo g_register_infos[] =
233 {
234 // Macro auto defines most stuff GCC DWARF GENERIC GDB LLDB VALUE REGS INVALIDATE REGS
235 // =============================== ======================= =================== ========================= ================== ================= ========== ===============
236 { DEFINE_GPR(eax , NULL) , { gcc_eax , dwarf_eax , LLDB_INVALID_REGNUM , gdb_eax , gpr_eax }, NULL, NULL},
237 { DEFINE_GPR(ebx , NULL) , { gcc_ebx , dwarf_ebx , LLDB_INVALID_REGNUM , gdb_ebx , gpr_ebx }, NULL, NULL},
238 { DEFINE_GPR(ecx , NULL) , { gcc_ecx , dwarf_ecx , LLDB_INVALID_REGNUM , gdb_ecx , gpr_ecx }, NULL, NULL},
239 { DEFINE_GPR(edx , NULL) , { gcc_edx , dwarf_edx , LLDB_INVALID_REGNUM , gdb_edx , gpr_edx }, NULL, NULL},
240 { DEFINE_GPR(edi , NULL) , { gcc_edi , dwarf_edi , LLDB_INVALID_REGNUM , gdb_edi , gpr_edi }, NULL, NULL},
241 { DEFINE_GPR(esi , NULL) , { gcc_esi , dwarf_esi , LLDB_INVALID_REGNUM , gdb_esi , gpr_esi }, NULL, NULL},
242 { DEFINE_GPR(ebp , "fp") , { gcc_ebp , dwarf_ebp , LLDB_REGNUM_GENERIC_FP , gdb_ebp , gpr_ebp }, NULL, NULL},
243 { DEFINE_GPR(esp , "sp") , { gcc_esp , dwarf_esp , LLDB_REGNUM_GENERIC_SP , gdb_esp , gpr_esp }, NULL, NULL},
244 { DEFINE_GPR(ss , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_ss , gpr_ss }, NULL, NULL},
245 { DEFINE_GPR(eflags , "flags") , { gcc_eflags , dwarf_eflags , LLDB_REGNUM_GENERIC_FLAGS , gdb_eflags , gpr_eflags }, NULL, NULL},
246 { DEFINE_GPR(eip , "pc") , { gcc_eip , dwarf_eip , LLDB_REGNUM_GENERIC_PC , gdb_eip , gpr_eip }, NULL, NULL},
247 { DEFINE_GPR(cs , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_cs , gpr_cs }, NULL, NULL},
248 { DEFINE_GPR(ds , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_ds , gpr_ds }, NULL, NULL},
249 { DEFINE_GPR(es , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_es , gpr_es }, NULL, NULL},
250 { DEFINE_GPR(fs , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fs , gpr_fs }, NULL, NULL},
251 { DEFINE_GPR(gs , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_gs , gpr_gs }, NULL, NULL},
252
253 { DEFINE_FPU_UINT(fcw) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fcw , fpu_fcw }, NULL, NULL},
254 { DEFINE_FPU_UINT(fsw) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fsw , fpu_fsw }, NULL, NULL},
255 { DEFINE_FPU_UINT(ftw) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_ftw , fpu_ftw }, NULL, NULL},
256 { DEFINE_FPU_UINT(fop) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fop , fpu_fop }, NULL, NULL},
257 { DEFINE_FPU_UINT(ip) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_ip , fpu_ip }, NULL, NULL},
258 { DEFINE_FPU_UINT(cs) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_cs , fpu_cs }, NULL, NULL},
259 { DEFINE_FPU_UINT(dp) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_dp , fpu_dp }, NULL, NULL},
260 { DEFINE_FPU_UINT(ds) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_ds , fpu_ds }, NULL, NULL},
261 { DEFINE_FPU_UINT(mxcsr) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_mxcsr , fpu_mxcsr }, NULL, NULL},
262 { DEFINE_FPU_UINT(mxcsrmask) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, fpu_mxcsrmask}, NULL, NULL},
263 { DEFINE_FPU_VECT(stmm,0) },
264 { DEFINE_FPU_VECT(stmm,1) },
265 { DEFINE_FPU_VECT(stmm,2) },
266 { DEFINE_FPU_VECT(stmm,3) },
267 { DEFINE_FPU_VECT(stmm,4) },
268 { DEFINE_FPU_VECT(stmm,5) },
269 { DEFINE_FPU_VECT(stmm,6) },
270 { DEFINE_FPU_VECT(stmm,7) },
271 { DEFINE_FPU_VECT(xmm,0) },
272 { DEFINE_FPU_VECT(xmm,1) },
273 { DEFINE_FPU_VECT(xmm,2) },
274 { DEFINE_FPU_VECT(xmm,3) },
275 { DEFINE_FPU_VECT(xmm,4) },
276 { DEFINE_FPU_VECT(xmm,5) },
277 { DEFINE_FPU_VECT(xmm,6) },
278 { DEFINE_FPU_VECT(xmm,7) },
279
280 { DEFINE_EXC(trapno) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, exc_trapno }, NULL, NULL},
281 { DEFINE_EXC(err) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, exc_err }, NULL, NULL},
282 { DEFINE_EXC(faultvaddr) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, exc_faultvaddr }, NULL, NULL}
283 };
284
285 static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos);
286
287 void
InvalidateAllRegisters()288 RegisterContextDarwin_i386::InvalidateAllRegisters ()
289 {
290 InvalidateAllRegisterStates();
291 }
292
293
294 size_t
GetRegisterCount()295 RegisterContextDarwin_i386::GetRegisterCount ()
296 {
297 assert(k_num_register_infos == k_num_registers);
298 return k_num_registers;
299 }
300
301 const RegisterInfo *
GetRegisterInfoAtIndex(size_t reg)302 RegisterContextDarwin_i386::GetRegisterInfoAtIndex (size_t reg)
303 {
304 assert(k_num_register_infos == k_num_registers);
305 if (reg < k_num_registers)
306 return &g_register_infos[reg];
307 return NULL;
308 }
309
310 size_t
GetRegisterInfosCount()311 RegisterContextDarwin_i386::GetRegisterInfosCount ()
312 {
313 return k_num_register_infos;
314 }
315
316 const RegisterInfo *
GetRegisterInfos()317 RegisterContextDarwin_i386::GetRegisterInfos ()
318 {
319 return g_register_infos;
320 }
321
322
323 // General purpose registers
324 static uint32_t
325 g_gpr_regnums[] =
326 {
327 gpr_eax,
328 gpr_ebx,
329 gpr_ecx,
330 gpr_edx,
331 gpr_edi,
332 gpr_esi,
333 gpr_ebp,
334 gpr_esp,
335 gpr_ss,
336 gpr_eflags,
337 gpr_eip,
338 gpr_cs,
339 gpr_ds,
340 gpr_es,
341 gpr_fs,
342 gpr_gs
343 };
344
345 // Floating point registers
346 static uint32_t
347 g_fpu_regnums[] =
348 {
349 fpu_fcw,
350 fpu_fsw,
351 fpu_ftw,
352 fpu_fop,
353 fpu_ip,
354 fpu_cs,
355 fpu_dp,
356 fpu_ds,
357 fpu_mxcsr,
358 fpu_mxcsrmask,
359 fpu_stmm0,
360 fpu_stmm1,
361 fpu_stmm2,
362 fpu_stmm3,
363 fpu_stmm4,
364 fpu_stmm5,
365 fpu_stmm6,
366 fpu_stmm7,
367 fpu_xmm0,
368 fpu_xmm1,
369 fpu_xmm2,
370 fpu_xmm3,
371 fpu_xmm4,
372 fpu_xmm5,
373 fpu_xmm6,
374 fpu_xmm7
375 };
376
377 // Exception registers
378
379 static uint32_t
380 g_exc_regnums[] =
381 {
382 exc_trapno,
383 exc_err,
384 exc_faultvaddr
385 };
386
387 // Number of registers in each register set
388 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums);
389 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums);
390 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums);
391
392 //----------------------------------------------------------------------
393 // Register set definitions. The first definitions at register set index
394 // of zero is for all registers, followed by other registers sets. The
395 // register information for the all register set need not be filled in.
396 //----------------------------------------------------------------------
397 static const RegisterSet g_reg_sets[] =
398 {
399 { "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, },
400 { "Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums },
401 { "Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums }
402 };
403
404 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets);
405
406
407 size_t
GetRegisterSetCount()408 RegisterContextDarwin_i386::GetRegisterSetCount ()
409 {
410 return k_num_regsets;
411 }
412
413 const RegisterSet *
GetRegisterSet(size_t reg_set)414 RegisterContextDarwin_i386::GetRegisterSet (size_t reg_set)
415 {
416 if (reg_set < k_num_regsets)
417 return &g_reg_sets[reg_set];
418 return NULL;
419 }
420
421
422 //----------------------------------------------------------------------
423 // Register information definitions for 32 bit i386.
424 //----------------------------------------------------------------------
425 int
GetSetForNativeRegNum(int reg_num)426 RegisterContextDarwin_i386::GetSetForNativeRegNum (int reg_num)
427 {
428 if (reg_num < fpu_fcw)
429 return GPRRegSet;
430 else if (reg_num < exc_trapno)
431 return FPURegSet;
432 else if (reg_num < k_num_registers)
433 return EXCRegSet;
434 return -1;
435 }
436
437
438 void
LogGPR(Log * log,const char * title)439 RegisterContextDarwin_i386::LogGPR(Log *log, const char *title)
440 {
441 if (log)
442 {
443 if (title)
444 log->Printf ("%s", title);
445 for (uint32_t i=0; i<k_num_gpr_registers; i++)
446 {
447 uint32_t reg = gpr_eax + i;
448 log->Printf("%12s = 0x%8.8x", g_register_infos[reg].name, (&gpr.eax)[reg]);
449 }
450 }
451 }
452
453
454
455 int
ReadGPR(bool force)456 RegisterContextDarwin_i386::ReadGPR (bool force)
457 {
458 int set = GPRRegSet;
459 if (force || !RegisterSetIsCached(set))
460 {
461 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
462 }
463 return GetError(set, Read);
464 }
465
466 int
ReadFPU(bool force)467 RegisterContextDarwin_i386::ReadFPU (bool force)
468 {
469 int set = FPURegSet;
470 if (force || !RegisterSetIsCached(set))
471 {
472 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
473 }
474 return GetError(set, Read);
475 }
476
477 int
ReadEXC(bool force)478 RegisterContextDarwin_i386::ReadEXC (bool force)
479 {
480 int set = EXCRegSet;
481 if (force || !RegisterSetIsCached(set))
482 {
483 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
484 }
485 return GetError(set, Read);
486 }
487
488 int
WriteGPR()489 RegisterContextDarwin_i386::WriteGPR ()
490 {
491 int set = GPRRegSet;
492 if (!RegisterSetIsCached(set))
493 {
494 SetError (set, Write, -1);
495 return -1;
496 }
497 SetError (set, Write, DoWriteGPR(GetThreadID(), set, gpr));
498 SetError (set, Read, -1);
499 return GetError(set, Write);
500 }
501
502 int
WriteFPU()503 RegisterContextDarwin_i386::WriteFPU ()
504 {
505 int set = FPURegSet;
506 if (!RegisterSetIsCached(set))
507 {
508 SetError (set, Write, -1);
509 return -1;
510 }
511 SetError (set, Write, DoWriteFPU(GetThreadID(), set, fpu));
512 SetError (set, Read, -1);
513 return GetError(set, Write);
514 }
515
516 int
WriteEXC()517 RegisterContextDarwin_i386::WriteEXC ()
518 {
519 int set = EXCRegSet;
520 if (!RegisterSetIsCached(set))
521 {
522 SetError (set, Write, -1);
523 return -1;
524 }
525 SetError (set, Write, DoWriteEXC(GetThreadID(), set, exc));
526 SetError (set, Read, -1);
527 return GetError(set, Write);
528 }
529
530 int
ReadRegisterSet(uint32_t set,bool force)531 RegisterContextDarwin_i386::ReadRegisterSet (uint32_t set, bool force)
532 {
533 switch (set)
534 {
535 case GPRRegSet: return ReadGPR(force);
536 case FPURegSet: return ReadFPU(force);
537 case EXCRegSet: return ReadEXC(force);
538 default: break;
539 }
540 return -1;
541 }
542
543 int
WriteRegisterSet(uint32_t set)544 RegisterContextDarwin_i386::WriteRegisterSet (uint32_t set)
545 {
546 // Make sure we have a valid context to set.
547 if (RegisterSetIsCached(set))
548 {
549 switch (set)
550 {
551 case GPRRegSet: return WriteGPR();
552 case FPURegSet: return WriteFPU();
553 case EXCRegSet: return WriteEXC();
554 default: break;
555 }
556 }
557 return -1;
558 }
559
560 bool
ReadRegister(const RegisterInfo * reg_info,RegisterValue & value)561 RegisterContextDarwin_i386::ReadRegister (const RegisterInfo *reg_info,
562 RegisterValue &value)
563 {
564 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
565 int set = RegisterContextDarwin_i386::GetSetForNativeRegNum (reg);
566
567 if (set == -1)
568 return false;
569
570 if (ReadRegisterSet(set, false) != 0)
571 return false;
572
573 switch (reg)
574 {
575 case gpr_eax:
576 case gpr_ebx:
577 case gpr_ecx:
578 case gpr_edx:
579 case gpr_edi:
580 case gpr_esi:
581 case gpr_ebp:
582 case gpr_esp:
583 case gpr_ss:
584 case gpr_eflags:
585 case gpr_eip:
586 case gpr_cs:
587 case gpr_ds:
588 case gpr_es:
589 case gpr_fs:
590 case gpr_gs:
591 value = (&gpr.eax)[reg - gpr_eax];
592 break;
593
594 case fpu_fcw:
595 value = fpu.fcw;
596 break;
597
598 case fpu_fsw:
599 value = fpu.fsw;
600 break;
601
602 case fpu_ftw:
603 value = fpu.ftw;
604 break;
605
606 case fpu_fop:
607 value = fpu.fop;
608 break;
609
610 case fpu_ip:
611 value = fpu.ip;
612 break;
613
614 case fpu_cs:
615 value = fpu.cs;
616 break;
617
618 case fpu_dp:
619 value = fpu.dp;
620 break;
621
622 case fpu_ds:
623 value = fpu.ds;
624 break;
625
626 case fpu_mxcsr:
627 value = fpu.mxcsr;
628 break;
629
630 case fpu_mxcsrmask:
631 value = fpu.mxcsrmask;
632 break;
633
634 case fpu_stmm0:
635 case fpu_stmm1:
636 case fpu_stmm2:
637 case fpu_stmm3:
638 case fpu_stmm4:
639 case fpu_stmm5:
640 case fpu_stmm6:
641 case fpu_stmm7:
642 // These values don't fit into scalar types,
643 // RegisterContext::ReadRegisterBytes() must be used for these
644 // registers
645 //::memcpy (reg_value.value.vector.uint8, fpu.stmm[reg - fpu_stmm0].bytes, 10);
646 return false;
647
648 case fpu_xmm0:
649 case fpu_xmm1:
650 case fpu_xmm2:
651 case fpu_xmm3:
652 case fpu_xmm4:
653 case fpu_xmm5:
654 case fpu_xmm6:
655 case fpu_xmm7:
656 // These values don't fit into scalar types, RegisterContext::ReadRegisterBytes()
657 // must be used for these registers
658 //::memcpy (reg_value.value.vector.uint8, fpu.xmm[reg - fpu_xmm0].bytes, 16);
659 return false;
660
661 case exc_trapno:
662 value = exc.trapno;
663 break;
664
665 case exc_err:
666 value = exc.err;
667 break;
668
669 case exc_faultvaddr:
670 value = exc.faultvaddr;
671 break;
672
673 default:
674 return false;
675 }
676 return true;
677 }
678
679
680 bool
WriteRegister(const RegisterInfo * reg_info,const RegisterValue & value)681 RegisterContextDarwin_i386::WriteRegister (const RegisterInfo *reg_info,
682 const RegisterValue &value)
683 {
684 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
685 int set = GetSetForNativeRegNum (reg);
686
687 if (set == -1)
688 return false;
689
690 if (ReadRegisterSet(set, false) != 0)
691 return false;
692
693 switch (reg)
694 {
695 case gpr_eax:
696 case gpr_ebx:
697 case gpr_ecx:
698 case gpr_edx:
699 case gpr_edi:
700 case gpr_esi:
701 case gpr_ebp:
702 case gpr_esp:
703 case gpr_ss:
704 case gpr_eflags:
705 case gpr_eip:
706 case gpr_cs:
707 case gpr_ds:
708 case gpr_es:
709 case gpr_fs:
710 case gpr_gs:
711 (&gpr.eax)[reg - gpr_eax] = value.GetAsUInt32();
712 break;
713
714 case fpu_fcw:
715 fpu.fcw = value.GetAsUInt16();
716 break;
717
718 case fpu_fsw:
719 fpu.fsw = value.GetAsUInt16();
720 break;
721
722 case fpu_ftw:
723 fpu.ftw = value.GetAsUInt8();
724 break;
725
726 case fpu_fop:
727 fpu.fop = value.GetAsUInt16();
728 break;
729
730 case fpu_ip:
731 fpu.ip = value.GetAsUInt32();
732 break;
733
734 case fpu_cs:
735 fpu.cs = value.GetAsUInt16();
736 break;
737
738 case fpu_dp:
739 fpu.dp = value.GetAsUInt32();
740 break;
741
742 case fpu_ds:
743 fpu.ds = value.GetAsUInt16();
744 break;
745
746 case fpu_mxcsr:
747 fpu.mxcsr = value.GetAsUInt32();
748 break;
749
750 case fpu_mxcsrmask:
751 fpu.mxcsrmask = value.GetAsUInt32();
752 break;
753
754 case fpu_stmm0:
755 case fpu_stmm1:
756 case fpu_stmm2:
757 case fpu_stmm3:
758 case fpu_stmm4:
759 case fpu_stmm5:
760 case fpu_stmm6:
761 case fpu_stmm7:
762 // These values don't fit into scalar types, RegisterContext::ReadRegisterBytes()
763 // must be used for these registers
764 ::memcpy (fpu.stmm[reg - fpu_stmm0].bytes, value.GetBytes(), value.GetByteSize());
765 return false;
766
767 case fpu_xmm0:
768 case fpu_xmm1:
769 case fpu_xmm2:
770 case fpu_xmm3:
771 case fpu_xmm4:
772 case fpu_xmm5:
773 case fpu_xmm6:
774 case fpu_xmm7:
775 // These values don't fit into scalar types, RegisterContext::ReadRegisterBytes()
776 // must be used for these registers
777 ::memcpy (fpu.xmm[reg - fpu_xmm0].bytes, value.GetBytes(), value.GetByteSize());
778 return false;
779
780 case exc_trapno:
781 exc.trapno = value.GetAsUInt32();
782 break;
783
784 case exc_err:
785 exc.err = value.GetAsUInt32();
786 break;
787
788 case exc_faultvaddr:
789 exc.faultvaddr = value.GetAsUInt32();
790 break;
791
792 default:
793 return false;
794 }
795 return WriteRegisterSet(set) == 0;
796 }
797
798 bool
ReadAllRegisterValues(lldb::DataBufferSP & data_sp)799 RegisterContextDarwin_i386::ReadAllRegisterValues (lldb::DataBufferSP &data_sp)
800 {
801 data_sp.reset (new DataBufferHeap (REG_CONTEXT_SIZE, 0));
802 if (data_sp &&
803 ReadGPR (false) == 0 &&
804 ReadFPU (false) == 0 &&
805 ReadEXC (false) == 0)
806 {
807 uint8_t *dst = data_sp->GetBytes();
808 ::memcpy (dst, &gpr, sizeof(gpr));
809 dst += sizeof(gpr);
810
811 ::memcpy (dst, &fpu, sizeof(fpu));
812 dst += sizeof(gpr);
813
814 ::memcpy (dst, &exc, sizeof(exc));
815 return true;
816 }
817 return false;
818 }
819
820 bool
WriteAllRegisterValues(const lldb::DataBufferSP & data_sp)821 RegisterContextDarwin_i386::WriteAllRegisterValues (const lldb::DataBufferSP &data_sp)
822 {
823 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE)
824 {
825 const uint8_t *src = data_sp->GetBytes();
826 ::memcpy (&gpr, src, sizeof(gpr));
827 src += sizeof(gpr);
828
829 ::memcpy (&fpu, src, sizeof(fpu));
830 src += sizeof(gpr);
831
832 ::memcpy (&exc, src, sizeof(exc));
833 uint32_t success_count = 0;
834 if (WriteGPR() == 0)
835 ++success_count;
836 if (WriteFPU() == 0)
837 ++success_count;
838 if (WriteEXC() == 0)
839 ++success_count;
840 return success_count == 3;
841 }
842 return false;
843 }
844
845
846 uint32_t
ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind,uint32_t reg)847 RegisterContextDarwin_i386::ConvertRegisterKindToRegisterNumber (lldb::RegisterKind kind, uint32_t reg)
848 {
849 if (kind == eRegisterKindGeneric)
850 {
851 switch (reg)
852 {
853 case LLDB_REGNUM_GENERIC_PC: return gpr_eip;
854 case LLDB_REGNUM_GENERIC_SP: return gpr_esp;
855 case LLDB_REGNUM_GENERIC_FP: return gpr_ebp;
856 case LLDB_REGNUM_GENERIC_FLAGS: return gpr_eflags;
857 case LLDB_REGNUM_GENERIC_RA:
858 default:
859 break;
860 }
861 }
862 else if (kind == eRegisterKindGCC || kind == eRegisterKindDWARF)
863 {
864 switch (reg)
865 {
866 case dwarf_eax: return gpr_eax;
867 case dwarf_ecx: return gpr_ecx;
868 case dwarf_edx: return gpr_edx;
869 case dwarf_ebx: return gpr_ebx;
870 case dwarf_esp: return gpr_esp;
871 case dwarf_ebp: return gpr_ebp;
872 case dwarf_esi: return gpr_esi;
873 case dwarf_edi: return gpr_edi;
874 case dwarf_eip: return gpr_eip;
875 case dwarf_eflags: return gpr_eflags;
876 case dwarf_stmm0: return fpu_stmm0;
877 case dwarf_stmm1: return fpu_stmm1;
878 case dwarf_stmm2: return fpu_stmm2;
879 case dwarf_stmm3: return fpu_stmm3;
880 case dwarf_stmm4: return fpu_stmm4;
881 case dwarf_stmm5: return fpu_stmm5;
882 case dwarf_stmm6: return fpu_stmm6;
883 case dwarf_stmm7: return fpu_stmm7;
884 case dwarf_xmm0: return fpu_xmm0;
885 case dwarf_xmm1: return fpu_xmm1;
886 case dwarf_xmm2: return fpu_xmm2;
887 case dwarf_xmm3: return fpu_xmm3;
888 case dwarf_xmm4: return fpu_xmm4;
889 case dwarf_xmm5: return fpu_xmm5;
890 case dwarf_xmm6: return fpu_xmm6;
891 case dwarf_xmm7: return fpu_xmm7;
892 default:
893 break;
894 }
895 }
896 else if (kind == eRegisterKindGDB)
897 {
898 switch (reg)
899 {
900 case gdb_eax : return gpr_eax;
901 case gdb_ebx : return gpr_ebx;
902 case gdb_ecx : return gpr_ecx;
903 case gdb_edx : return gpr_edx;
904 case gdb_esi : return gpr_esi;
905 case gdb_edi : return gpr_edi;
906 case gdb_ebp : return gpr_ebp;
907 case gdb_esp : return gpr_esp;
908 case gdb_eip : return gpr_eip;
909 case gdb_eflags : return gpr_eflags;
910 case gdb_cs : return gpr_cs;
911 case gdb_ss : return gpr_ss;
912 case gdb_ds : return gpr_ds;
913 case gdb_es : return gpr_es;
914 case gdb_fs : return gpr_fs;
915 case gdb_gs : return gpr_gs;
916 case gdb_stmm0 : return fpu_stmm0;
917 case gdb_stmm1 : return fpu_stmm1;
918 case gdb_stmm2 : return fpu_stmm2;
919 case gdb_stmm3 : return fpu_stmm3;
920 case gdb_stmm4 : return fpu_stmm4;
921 case gdb_stmm5 : return fpu_stmm5;
922 case gdb_stmm6 : return fpu_stmm6;
923 case gdb_stmm7 : return fpu_stmm7;
924 case gdb_fctrl : return fpu_fctrl;
925 case gdb_fstat : return fpu_fstat;
926 case gdb_ftag : return fpu_ftag;
927 case gdb_fiseg : return fpu_fiseg;
928 case gdb_fioff : return fpu_fioff;
929 case gdb_foseg : return fpu_foseg;
930 case gdb_fooff : return fpu_fooff;
931 case gdb_fop : return fpu_fop;
932 case gdb_xmm0 : return fpu_xmm0;
933 case gdb_xmm1 : return fpu_xmm1;
934 case gdb_xmm2 : return fpu_xmm2;
935 case gdb_xmm3 : return fpu_xmm3;
936 case gdb_xmm4 : return fpu_xmm4;
937 case gdb_xmm5 : return fpu_xmm5;
938 case gdb_xmm6 : return fpu_xmm6;
939 case gdb_xmm7 : return fpu_xmm7;
940 case gdb_mxcsr : return fpu_mxcsr;
941 default:
942 break;
943 }
944 }
945 else if (kind == eRegisterKindLLDB)
946 {
947 return reg;
948 }
949 return LLDB_INVALID_REGNUM;
950 }
951
952
953 bool
HardwareSingleStep(bool enable)954 RegisterContextDarwin_i386::HardwareSingleStep (bool enable)
955 {
956 if (ReadGPR(false) != 0)
957 return false;
958
959 const uint32_t trace_bit = 0x100u;
960 if (enable)
961 {
962 // If the trace bit is already set, there is nothing to do
963 if (gpr.eflags & trace_bit)
964 return true;
965 else
966 gpr.eflags |= trace_bit;
967 }
968 else
969 {
970 // If the trace bit is already cleared, there is nothing to do
971 if (gpr.eflags & trace_bit)
972 gpr.eflags &= ~trace_bit;
973 else
974 return true;
975 }
976
977 return WriteGPR() == 0;
978 }
979
980
981
982