Searched defs:RCID (Results 1 – 10 of 10) sorted by relevance
203 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID()
5550 const MCInstrDesc &TID, unsigned RCID, in adjustAllocatableRegClass()5626 unsigned RCID = Desc.operands()[OpNo].RegClass; in getOpRegClass() local5635 unsigned RCID = get(MI.getOpcode()).operands()[OpIdx].RegClass; in legalizeOpWithMove() local9036 const auto RCID = MI.getDesc().operands()[Idx].RegClass; in isBufferSMRD() local
378 unsigned RCID = N->getConstantOperandVal(0); in getOperandRegClass() local
809 int RCID = Desc.operands()[OpNo].RegClass; in printRegularOperand() local895 int RCID = Desc.operands()[OpNo].RegClass; in printRegularOperand() local
1596 unsigned RCID; in handleSpecialFP() local
970 unsigned RCID; in getRegClassConstraint() local1836 unsigned RCID; in print() local
1766 unsigned RCID; in createMIROperandComment() local
270 bool isRegOrInline(unsigned RCID, MVT type) const { in isRegOrInline()274 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods()414 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods()2826 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg() local
2401 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth()2547 unsigned RCID = Desc.operands()[OpNo].RegClass; in getRegOperandSize() local
216 unsigned RCID = getRegClassIDForVecVT(ContainerVT); in RISCVTargetLowering() local