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Searched defs:RC (Results 1 – 25 of 270) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); in mask() local
123 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) in getPhysRegBitWidth() local
131 const TargetRegisterClass &RC, unsigned Idx) const { in composeWithSubRegIndex() argument
281 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
288 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
289 -> BT::RegisterCell { in evaluate()
298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
333 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
349 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
356 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); in evaluate() local
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DHexagonConstPropagation.cpp719 LatticeCell RC = Cells.get(DefR.Reg); in visitNonBranch() local
1081 LatticeCell &RC) { in getCell()
1391 LatticeCell RC; in evaluateANDrr() local
1407 LatticeCell RC; in evaluateANDri() local
1458 LatticeCell RC; in evaluateORrr() local
1474 LatticeCell RC; in evaluateORri() local
1523 LatticeCell RC; in evaluateXORrr() local
1942 LatticeCell RC; in evaluate() local
1964 LatticeCell RC; in evaluate() local
1998 LatticeCell RC = Outputs.get(DefR.Reg); in evaluate() local
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DHexagonBitSimplify.cpp358 bool HexagonBitSimplify::isZero(const BitTracker::RegisterCell &RC, in isZero()
367 bool HexagonBitSimplify::getConst(const BitTracker::RegisterCell &RC, in getConst()
437 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg); in getSubregMask() local
929 auto *RC = MRI.getRegClass(RR.Reg); in getFinalVRegClass() local
935 auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void { in getFinalVRegClass()
1290 const TargetRegisterClass *RC = HBS::getFinalVRegClass(RR, MRI); in computeUsedBits() local
1440 Register ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C, in genTfrConst()
1586 const BitTracker::RegisterCell &RC = BT.lookup(R); in findMatch() local
1721 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg); in propagateRegCopy() local
1731 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg); in propagateRegCopy() local
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/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h186 static bool isSGPRClass(const TargetRegisterClass *RC) { in isSGPRClass()
198 static bool isVGPRClass(const TargetRegisterClass *RC) { in isVGPRClass()
203 static bool isAGPRClass(const TargetRegisterClass *RC) { in isAGPRClass()
208 bool isVectorSuperClass(const TargetRegisterClass *RC) const { in isVectorSuperClass()
213 bool isVSSuperClass(const TargetRegisterClass *RC) const { in isVSSuperClass()
218 static bool hasVGPRs(const TargetRegisterClass *RC) { in hasVGPRs()
223 static bool hasAGPRs(const TargetRegisterClass *RC) { in hasAGPRs()
228 static bool hasSGPRs(const TargetRegisterClass *RC) { in hasSGPRs()
233 static bool hasVectorRegisters(const TargetRegisterClass *RC) { in hasVectorRegisters()
289 bool isDivergentRegClass(const TargetRegisterClass *RC) const override { in isDivergentRegClass()
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h78 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
94 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
111 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
127 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost()
135 unsigned getLastCostChange(const TargetRegisterClass *RC) const { in getLastCostChange()
DTargetRegisterInfo.h124 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
129 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
136 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
141 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
279 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
285 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
291 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign()
296 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
304 bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const { in isTypeLegalForClass()
318 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { in legalclasstypes_begin()
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/openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/
DWebAssemblyExplicitLocals.cpp88 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode()
107 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { in getLocalGetOpcode()
126 static unsigned getLocalSetOpcode(const TargetRegisterClass *RC) { in getLocalSetOpcode()
145 static unsigned getLocalTeeOpcode(const TargetRegisterClass *RC) { in getLocalTeeOpcode()
164 static MVT typeForRegClass(const TargetRegisterClass *RC) { in typeForRegClass()
274 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
307 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
379 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
/openbsd/src/gnu/llvm/llvm/utils/TableGen/
DRegisterBankEmitter.cpp72 void addRegisterClass(const CodeGenRegisterClass *RC) { in addRegisterClass()
170 const CodeGenRegisterClass *RC, const Twine &Kind, in visitRegisterBankClasses()
221 for (const auto &RC : Bank.register_classes()) in emitBaseClassImplementation() local
228 for (const auto &RC : RCs) { in emitBaseClassImplementation() local
244 const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegsSize(); in emitBaseClassImplementation() local
285 for (const CodeGenRegisterClass *RC : in run() local
289 [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) { in run()
DRegisterInfoEmitter.cpp146 for (const auto &RC : RegisterClasses) in runEnums() local
217 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
1047 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1083 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1201 if (llvm::any_of(RegisterClasses, [](const auto &RC) { return RC.getBaseClassOrder(); })) { in runTargetHeader()
1211 for (const auto &RC : RegisterClasses) { in runTargetHeader() local
1248 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1261 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1305 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1349 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
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DCodeGenRegisters.cpp982 CodeGenRegisterClass &RC = *I; in computeSubClasses() local
1006 for (auto &RC : RegClasses) { in computeSubClasses() local
1022 for (auto &RC : RegClasses) in computeSubClasses() local
1050 for (auto &RC : RegClasses) in getMatchingSubClassWithSubRegs() local
1060 for (auto &RC: RegClasses) { in getMatchingSubClassWithSubRegs() local
1250 CodeGenRegisterClass &RC = RegClasses.back(); in CodeGenRegBank() local
1261 for (auto &RC : RegClasses) in CodeGenRegBank() local
1302 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) { in addToMaps()
1314 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC, in getOrCreateSubClass()
1330 if (CodeGenRegisterClass *RC = Def2RC.lookup(Def)) in getRegClass() local
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/openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp449 const TargetRegisterClass *RC, in PPCEmitLoad()
606 const TargetRegisterClass *RC = in SelectLoad() local
623 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
987 auto RC = MRI.getRegClass(SrcReg); in SelectFPTrunc() local
1051 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1130 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1174 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1225 auto RC = MRI.getRegClass(SrcReg); in SelectFPToI() local
1280 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1442 const TargetRegisterClass *RC = in processCallArgs() local
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/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
264 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
317 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
383 const TargetRegisterClass *RC = in expandExtractElementF64() local
421 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
719 const TargetRegisterClass *RC = in emitEpilogue() local
834 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
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DMipsMachineFunction.cpp78 const TargetRegisterClass *RC; in initGlobalBaseReg() local
159 const TargetRegisterClass &RC = in createEhDataRegsFI() local
174 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI() local
201 const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
DMipsInstrInfo.h139 const TargetRegisterClass *RC, in storeRegToStackSlot()
147 int FrameIndex, const TargetRegisterClass *RC, in loadRegFromStackSlot()
/openbsd/src/gnu/llvm/llvm/lib/Target/XCore/
DXCoreMachineFunctionInfo.cpp45 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
63 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
76 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DSwiftErrorValueTracking.cpp36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVReg() local
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVRegDefAt() local
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in createEntriesInEntryBlock() local
240 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in propagateVRegs() local
DLiveStacks.cpp54 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
79 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
DRegisterBank.cpp35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify() local
105 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print() local
DTargetRegisterInfo.cpp219 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass() local
237 for (const TargetRegisterClass *RC : regclasses()) { in getMinimalPhysRegClassLLT() local
249 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
353 const TargetRegisterClass *RC = in getCommonSuperRegClass() local
504 const TargetRegisterClass *RC{}; in getRegSizeInBits() local
525 const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, in getCoveringSubRegIndexes()
DRegAllocBase.cpp127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg()); in allocatePhysRegs() local
184 const TargetRegisterClass &RC = *MRI->getRegClass(Reg); in enqueue() local
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp59 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue() local
359 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta() local
363 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta() local
477 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
488 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
/openbsd/src/gnu/llvm/llvm/include/llvm/IR/
DConstantFolder.h46 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
58 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
71 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
100 auto *RC = dyn_cast<Constant>(RHS); in FoldICmp() local
/openbsd/src/gnu/llvm/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.cpp29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName()
73 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr()
/openbsd/src/gnu/llvm/llvm/include/llvm/Analysis/
DTargetFolder.h57 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
69 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
82 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
104 auto *RC = dyn_cast<Constant>(RHS); in FoldICmp() local
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMFastISel.cpp297 const TargetRegisterClass *RC, in fastEmitInst_r()
319 const TargetRegisterClass *RC, in fastEmitInst_rr()
346 const TargetRegisterClass *RC, in fastEmitInst_ri()
371 const TargetRegisterClass *RC, in fastEmitInst_i()
462 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : in ARMMaterializeInt() local
478 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : in ARMMaterializeInt() local
531 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass in ARMMaterializeGV() local
657 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca() local
831 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass in ARMSimplifyAddress() local
904 const TargetRegisterClass *RC; in ARMEmitLoad() local
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