1 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Kevin E. Martin <martin@valinux.com> 29 * Gareth Hughes <gareth@valinux.com> 30 * Keith Whitwell <keith@tungstengraphics.com> 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: stable/9/sys/dev/drm2/radeon/radeon_drm.h 254885 2013-08-25 19:37:15Z dumbbell $"); 35 36 #ifndef __RADEON_DRM_H__ 37 #define __RADEON_DRM_H__ 38 39 #include <dev/drm2/drm.h> 40 41 /* WARNING: If you change any of these defines, make sure to change the 42 * defines in the X server file (radeon_sarea.h) 43 */ 44 #ifndef __RADEON_SAREA_DEFINES__ 45 #define __RADEON_SAREA_DEFINES__ 46 47 /* Old style state flags, required for sarea interface (1.1 and 1.2 48 * clears) and 1.2 drm_vertex2 ioctl. 49 */ 50 #define RADEON_UPLOAD_CONTEXT 0x00000001 51 #define RADEON_UPLOAD_VERTFMT 0x00000002 52 #define RADEON_UPLOAD_LINE 0x00000004 53 #define RADEON_UPLOAD_BUMPMAP 0x00000008 54 #define RADEON_UPLOAD_MASKS 0x00000010 55 #define RADEON_UPLOAD_VIEWPORT 0x00000020 56 #define RADEON_UPLOAD_SETUP 0x00000040 57 #define RADEON_UPLOAD_TCL 0x00000080 58 #define RADEON_UPLOAD_MISC 0x00000100 59 #define RADEON_UPLOAD_TEX0 0x00000200 60 #define RADEON_UPLOAD_TEX1 0x00000400 61 #define RADEON_UPLOAD_TEX2 0x00000800 62 #define RADEON_UPLOAD_TEX0IMAGES 0x00001000 63 #define RADEON_UPLOAD_TEX1IMAGES 0x00002000 64 #define RADEON_UPLOAD_TEX2IMAGES 0x00004000 65 #define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ 66 #define RADEON_REQUIRE_QUIESCENCE 0x00010000 67 #define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ 68 #define RADEON_UPLOAD_ALL 0x003effff 69 #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 70 71 /* New style per-packet identifiers for use in cmd_buffer ioctl with 72 * the RADEON_EMIT_PACKET command. Comments relate new packets to old 73 * state bits and the packet size: 74 */ 75 #define RADEON_EMIT_PP_MISC 0 /* context/7 */ 76 #define RADEON_EMIT_PP_CNTL 1 /* context/3 */ 77 #define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ 78 #define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ 79 #define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ 80 #define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ 81 #define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ 82 #define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ 83 #define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ 84 #define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ 85 #define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ 86 #define RADEON_EMIT_RE_MISC 11 /* misc/1 */ 87 #define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ 88 #define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ 89 #define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ 90 #define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ 91 #define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ 92 #define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ 93 #define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ 94 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ 95 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ 96 #define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ 97 #define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ 98 #define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ 99 #define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ 100 #define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ 101 #define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ 102 #define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ 103 #define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ 104 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ 105 #define R200_EMIT_TFACTOR_0 30 /* tf/7 */ 106 #define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ 107 #define R200_EMIT_VAP_CTL 32 /* vap/1 */ 108 #define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ 109 #define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ 110 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ 111 #define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ 112 #define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ 113 #define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ 114 #define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ 115 #define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ 116 #define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ 117 #define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ 118 #define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ 119 #define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ 120 #define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ 121 #define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ 122 #define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ 123 #define R200_EMIT_VTE_CNTL 48 /* vte/1 */ 124 #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ 125 #define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ 126 #define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ 127 #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ 128 #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ 129 #define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ 130 #define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ 131 #define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ 132 #define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ 133 #define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ 134 #define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ 135 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ 136 #define R200_EMIT_PP_CUBIC_FACES_0 61 137 #define R200_EMIT_PP_CUBIC_OFFSETS_0 62 138 #define R200_EMIT_PP_CUBIC_FACES_1 63 139 #define R200_EMIT_PP_CUBIC_OFFSETS_1 64 140 #define R200_EMIT_PP_CUBIC_FACES_2 65 141 #define R200_EMIT_PP_CUBIC_OFFSETS_2 66 142 #define R200_EMIT_PP_CUBIC_FACES_3 67 143 #define R200_EMIT_PP_CUBIC_OFFSETS_3 68 144 #define R200_EMIT_PP_CUBIC_FACES_4 69 145 #define R200_EMIT_PP_CUBIC_OFFSETS_4 70 146 #define R200_EMIT_PP_CUBIC_FACES_5 71 147 #define R200_EMIT_PP_CUBIC_OFFSETS_5 72 148 #define RADEON_EMIT_PP_TEX_SIZE_0 73 149 #define RADEON_EMIT_PP_TEX_SIZE_1 74 150 #define RADEON_EMIT_PP_TEX_SIZE_2 75 151 #define R200_EMIT_RB3D_BLENDCOLOR 76 152 #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 153 #define RADEON_EMIT_PP_CUBIC_FACES_0 78 154 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 155 #define RADEON_EMIT_PP_CUBIC_FACES_1 80 156 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 157 #define RADEON_EMIT_PP_CUBIC_FACES_2 82 158 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 159 #define R200_EMIT_PP_TRI_PERF_CNTL 84 160 #define R200_EMIT_PP_AFS_0 85 161 #define R200_EMIT_PP_AFS_1 86 162 #define R200_EMIT_ATF_TFACTOR 87 163 #define R200_EMIT_PP_TXCTLALL_0 88 164 #define R200_EMIT_PP_TXCTLALL_1 89 165 #define R200_EMIT_PP_TXCTLALL_2 90 166 #define R200_EMIT_PP_TXCTLALL_3 91 167 #define R200_EMIT_PP_TXCTLALL_4 92 168 #define R200_EMIT_PP_TXCTLALL_5 93 169 #define R200_EMIT_VAP_PVS_CNTL 94 170 #define RADEON_MAX_STATE_PACKETS 95 171 172 /* Commands understood by cmd_buffer ioctl. More can be added but 173 * obviously these can't be removed or changed: 174 */ 175 #define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ 176 #define RADEON_CMD_SCALARS 2 /* emit scalar data */ 177 #define RADEON_CMD_VECTORS 3 /* emit vector data */ 178 #define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ 179 #define RADEON_CMD_PACKET3 5 /* emit hw packet */ 180 #define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ 181 #define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ 182 #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: 183 * doesn't make the cpu wait, just 184 * the graphics hardware */ 185 #define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ 186 187 typedef union { 188 int i; 189 struct { 190 unsigned char cmd_type, pad0, pad1, pad2; 191 } header; 192 struct { 193 unsigned char cmd_type, packet_id, pad0, pad1; 194 } packet; 195 struct { 196 unsigned char cmd_type, offset, stride, count; 197 } scalars; 198 struct { 199 unsigned char cmd_type, offset, stride, count; 200 } vectors; 201 struct { 202 unsigned char cmd_type, addr_lo, addr_hi, count; 203 } veclinear; 204 struct { 205 unsigned char cmd_type, buf_idx, pad0, pad1; 206 } dma; 207 struct { 208 unsigned char cmd_type, flags, pad0, pad1; 209 } wait; 210 } drm_radeon_cmd_header_t; 211 212 #define RADEON_WAIT_2D 0x1 213 #define RADEON_WAIT_3D 0x2 214 215 /* Allowed parameters for R300_CMD_PACKET3 216 */ 217 #define R300_CMD_PACKET3_CLEAR 0 218 #define R300_CMD_PACKET3_RAW 1 219 220 /* Commands understood by cmd_buffer ioctl for R300. 221 * The interface has not been stabilized, so some of these may be removed 222 * and eventually reordered before stabilization. 223 */ 224 #define R300_CMD_PACKET0 1 225 #define R300_CMD_VPU 2 /* emit vertex program upload */ 226 #define R300_CMD_PACKET3 3 /* emit a packet3 */ 227 #define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ 228 #define R300_CMD_CP_DELAY 5 229 #define R300_CMD_DMA_DISCARD 6 230 #define R300_CMD_WAIT 7 231 # define R300_WAIT_2D 0x1 232 # define R300_WAIT_3D 0x2 233 /* these two defines are DOING IT WRONG - however 234 * we have userspace which relies on using these. 235 * The wait interface is backwards compat new 236 * code should use the NEW_WAIT defines below 237 * THESE ARE NOT BIT FIELDS 238 */ 239 # define R300_WAIT_2D_CLEAN 0x3 240 # define R300_WAIT_3D_CLEAN 0x4 241 242 # define R300_NEW_WAIT_2D_3D 0x3 243 # define R300_NEW_WAIT_2D_2D_CLEAN 0x4 244 # define R300_NEW_WAIT_3D_3D_CLEAN 0x6 245 # define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 246 247 #define R300_CMD_SCRATCH 8 248 #define R300_CMD_R500FP 9 249 250 typedef union { 251 unsigned int u; 252 struct { 253 unsigned char cmd_type, pad0, pad1, pad2; 254 } header; 255 struct { 256 unsigned char cmd_type, count, reglo, reghi; 257 } packet0; 258 struct { 259 unsigned char cmd_type, count, adrlo, adrhi; 260 } vpu; 261 struct { 262 unsigned char cmd_type, packet, pad0, pad1; 263 } packet3; 264 struct { 265 unsigned char cmd_type, packet; 266 unsigned short count; /* amount of packet2 to emit */ 267 } delay; 268 struct { 269 unsigned char cmd_type, buf_idx, pad0, pad1; 270 } dma; 271 struct { 272 unsigned char cmd_type, flags, pad0, pad1; 273 } wait; 274 struct { 275 unsigned char cmd_type, reg, n_bufs, flags; 276 } scratch; 277 struct { 278 unsigned char cmd_type, count, adrlo, adrhi_flags; 279 } r500fp; 280 } drm_r300_cmd_header_t; 281 282 #define RADEON_FRONT 0x1 283 #define RADEON_BACK 0x2 284 #define RADEON_DEPTH 0x4 285 #define RADEON_STENCIL 0x8 286 #define RADEON_CLEAR_FASTZ 0x80000000 287 #define RADEON_USE_HIERZ 0x40000000 288 #define RADEON_USE_COMP_ZBUF 0x20000000 289 290 #define R500FP_CONSTANT_TYPE (1 << 1) 291 #define R500FP_CONSTANT_CLAMP (1 << 2) 292 293 /* Primitive types 294 */ 295 #define RADEON_POINTS 0x1 296 #define RADEON_LINES 0x2 297 #define RADEON_LINE_STRIP 0x3 298 #define RADEON_TRIANGLES 0x4 299 #define RADEON_TRIANGLE_FAN 0x5 300 #define RADEON_TRIANGLE_STRIP 0x6 301 302 /* Vertex/indirect buffer size 303 */ 304 #define RADEON_BUFFER_SIZE 65536 305 306 /* Byte offsets for indirect buffer data 307 */ 308 #define RADEON_INDEX_PRIM_OFFSET 20 309 310 #define RADEON_SCRATCH_REG_OFFSET 32 311 312 #define R600_SCRATCH_REG_OFFSET 256 313 314 #define RADEON_NR_SAREA_CLIPRECTS 12 315 316 /* There are 2 heaps (local/GART). Each region within a heap is a 317 * minimum of 64k, and there are at most 64 of them per heap. 318 */ 319 #define RADEON_LOCAL_TEX_HEAP 0 320 #define RADEON_GART_TEX_HEAP 1 321 #define RADEON_NR_TEX_HEAPS 2 322 #define RADEON_NR_TEX_REGIONS 64 323 #define RADEON_LOG_TEX_GRANULARITY 16 324 325 #define RADEON_MAX_TEXTURE_LEVELS 12 326 #define RADEON_MAX_TEXTURE_UNITS 3 327 328 #define RADEON_MAX_SURFACES 8 329 330 /* Blits have strict offset rules. All blit offset must be aligned on 331 * a 1K-byte boundary. 332 */ 333 #define RADEON_OFFSET_SHIFT 10 334 #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 335 #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 336 337 #endif /* __RADEON_SAREA_DEFINES__ */ 338 339 typedef struct { 340 unsigned int red; 341 unsigned int green; 342 unsigned int blue; 343 unsigned int alpha; 344 } radeon_color_regs_t; 345 346 typedef struct { 347 /* Context state */ 348 unsigned int pp_misc; /* 0x1c14 */ 349 unsigned int pp_fog_color; 350 unsigned int re_solid_color; 351 unsigned int rb3d_blendcntl; 352 unsigned int rb3d_depthoffset; 353 unsigned int rb3d_depthpitch; 354 unsigned int rb3d_zstencilcntl; 355 356 unsigned int pp_cntl; /* 0x1c38 */ 357 unsigned int rb3d_cntl; 358 unsigned int rb3d_coloroffset; 359 unsigned int re_width_height; 360 unsigned int rb3d_colorpitch; 361 unsigned int se_cntl; 362 363 /* Vertex format state */ 364 unsigned int se_coord_fmt; /* 0x1c50 */ 365 366 /* Line state */ 367 unsigned int re_line_pattern; /* 0x1cd0 */ 368 unsigned int re_line_state; 369 370 unsigned int se_line_width; /* 0x1db8 */ 371 372 /* Bumpmap state */ 373 unsigned int pp_lum_matrix; /* 0x1d00 */ 374 375 unsigned int pp_rot_matrix_0; /* 0x1d58 */ 376 unsigned int pp_rot_matrix_1; 377 378 /* Mask state */ 379 unsigned int rb3d_stencilrefmask; /* 0x1d7c */ 380 unsigned int rb3d_ropcntl; 381 unsigned int rb3d_planemask; 382 383 /* Viewport state */ 384 unsigned int se_vport_xscale; /* 0x1d98 */ 385 unsigned int se_vport_xoffset; 386 unsigned int se_vport_yscale; 387 unsigned int se_vport_yoffset; 388 unsigned int se_vport_zscale; 389 unsigned int se_vport_zoffset; 390 391 /* Setup state */ 392 unsigned int se_cntl_status; /* 0x2140 */ 393 394 /* Misc state */ 395 unsigned int re_top_left; /* 0x26c0 */ 396 unsigned int re_misc; 397 } drm_radeon_context_regs_t; 398 399 typedef struct { 400 /* Zbias state */ 401 unsigned int se_zbias_factor; /* 0x1dac */ 402 unsigned int se_zbias_constant; 403 } drm_radeon_context2_regs_t; 404 405 /* Setup registers for each texture unit 406 */ 407 typedef struct { 408 unsigned int pp_txfilter; 409 unsigned int pp_txformat; 410 unsigned int pp_txoffset; 411 unsigned int pp_txcblend; 412 unsigned int pp_txablend; 413 unsigned int pp_tfactor; 414 unsigned int pp_border_color; 415 } drm_radeon_texture_regs_t; 416 417 typedef struct { 418 unsigned int start; 419 unsigned int finish; 420 unsigned int prim:8; 421 unsigned int stateidx:8; 422 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ 423 unsigned int vc_format; /* vertex format */ 424 } drm_radeon_prim_t; 425 426 typedef struct { 427 drm_radeon_context_regs_t context; 428 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 429 drm_radeon_context2_regs_t context2; 430 unsigned int dirty; 431 } drm_radeon_state_t; 432 433 typedef struct { 434 /* The channel for communication of state information to the 435 * kernel on firing a vertex buffer with either of the 436 * obsoleted vertex/index ioctls. 437 */ 438 drm_radeon_context_regs_t context_state; 439 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 440 unsigned int dirty; 441 unsigned int vertsize; 442 unsigned int vc_format; 443 444 /* The current cliprects, or a subset thereof. 445 */ 446 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; 447 unsigned int nbox; 448 449 /* Counters for client-side throttling of rendering clients. 450 */ 451 unsigned int last_frame; 452 unsigned int last_dispatch; 453 unsigned int last_clear; 454 455 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 456 1]; 457 unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 458 int ctx_owner; 459 int pfState; /* number of 3d windows (0,1,2ormore) */ 460 int pfCurrentPage; /* which buffer is being displayed? */ 461 int crtc2_base; /* CRTC2 frame offset */ 462 int tiling_enabled; /* set by drm, read by 2d + 3d clients */ 463 } drm_radeon_sarea_t; 464 465 /* WARNING: If you change any of these defines, make sure to change the 466 * defines in the Xserver file (xf86drmRadeon.h) 467 * 468 * KW: actually it's illegal to change any of this (backwards compatibility). 469 */ 470 471 /* Radeon specific ioctls 472 * The device specific ioctl range is 0x40 to 0x79. 473 */ 474 #define DRM_RADEON_CP_INIT 0x00 475 #define DRM_RADEON_CP_START 0x01 476 #define DRM_RADEON_CP_STOP 0x02 477 #define DRM_RADEON_CP_RESET 0x03 478 #define DRM_RADEON_CP_IDLE 0x04 479 #define DRM_RADEON_RESET 0x05 480 #define DRM_RADEON_FULLSCREEN 0x06 481 #define DRM_RADEON_SWAP 0x07 482 #define DRM_RADEON_CLEAR 0x08 483 #define DRM_RADEON_VERTEX 0x09 484 #define DRM_RADEON_INDICES 0x0A 485 #define DRM_RADEON_NOT_USED 486 #define DRM_RADEON_STIPPLE 0x0C 487 #define DRM_RADEON_INDIRECT 0x0D 488 #define DRM_RADEON_TEXTURE 0x0E 489 #define DRM_RADEON_VERTEX2 0x0F 490 #define DRM_RADEON_CMDBUF 0x10 491 #define DRM_RADEON_GETPARAM 0x11 492 #define DRM_RADEON_FLIP 0x12 493 #define DRM_RADEON_ALLOC 0x13 494 #define DRM_RADEON_FREE 0x14 495 #define DRM_RADEON_INIT_HEAP 0x15 496 #define DRM_RADEON_IRQ_EMIT 0x16 497 #define DRM_RADEON_IRQ_WAIT 0x17 498 #define DRM_RADEON_CP_RESUME 0x18 499 #define DRM_RADEON_SETPARAM 0x19 500 #define DRM_RADEON_SURF_ALLOC 0x1a 501 #define DRM_RADEON_SURF_FREE 0x1b 502 /* KMS ioctl */ 503 #define DRM_RADEON_GEM_INFO 0x1c 504 #define DRM_RADEON_GEM_CREATE 0x1d 505 #define DRM_RADEON_GEM_MMAP 0x1e 506 #define DRM_RADEON_GEM_PREAD 0x21 507 #define DRM_RADEON_GEM_PWRITE 0x22 508 #define DRM_RADEON_GEM_SET_DOMAIN 0x23 509 #define DRM_RADEON_GEM_WAIT_IDLE 0x24 510 #define DRM_RADEON_CS 0x26 511 #define DRM_RADEON_INFO 0x27 512 #define DRM_RADEON_GEM_SET_TILING 0x28 513 #define DRM_RADEON_GEM_GET_TILING 0x29 514 #define DRM_RADEON_GEM_BUSY 0x2a 515 #define DRM_RADEON_GEM_VA 0x2b 516 517 #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 518 #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) 519 #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 520 #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 521 #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 522 #define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) 523 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 524 #define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) 525 #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 526 #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 527 #define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 528 #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 529 #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 530 #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 531 #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 532 #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 533 #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 534 #define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) 535 #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 536 #define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 537 #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 538 #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 539 #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 540 #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 541 #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 542 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 543 #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) 544 /* KMS */ 545 #define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) 546 #define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) 547 #define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) 548 #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) 549 #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) 550 #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) 551 #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) 552 #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) 553 #define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) 554 #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) 555 #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) 556 #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) 557 #define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) 558 559 typedef struct drm_radeon_init { 560 enum { 561 RADEON_INIT_CP = 0x01, 562 RADEON_CLEANUP_CP = 0x02, 563 RADEON_INIT_R200_CP = 0x03, 564 RADEON_INIT_R300_CP = 0x04, 565 RADEON_INIT_R600_CP = 0x05 566 } func; 567 unsigned long sarea_priv_offset; 568 int is_pci; 569 int cp_mode; 570 int gart_size; 571 int ring_size; 572 int usec_timeout; 573 574 unsigned int fb_bpp; 575 unsigned int front_offset, front_pitch; 576 unsigned int back_offset, back_pitch; 577 unsigned int depth_bpp; 578 unsigned int depth_offset, depth_pitch; 579 580 unsigned long fb_offset; 581 unsigned long mmio_offset; 582 unsigned long ring_offset; 583 unsigned long ring_rptr_offset; 584 unsigned long buffers_offset; 585 unsigned long gart_textures_offset; 586 } drm_radeon_init_t; 587 588 typedef struct drm_radeon_cp_stop { 589 int flush; 590 int idle; 591 } drm_radeon_cp_stop_t; 592 593 typedef struct drm_radeon_fullscreen { 594 enum { 595 RADEON_INIT_FULLSCREEN = 0x01, 596 RADEON_CLEANUP_FULLSCREEN = 0x02 597 } func; 598 } drm_radeon_fullscreen_t; 599 600 #define CLEAR_X1 0 601 #define CLEAR_Y1 1 602 #define CLEAR_X2 2 603 #define CLEAR_Y2 3 604 #define CLEAR_DEPTH 4 605 606 typedef union drm_radeon_clear_rect { 607 float f[5]; 608 unsigned int ui[5]; 609 } drm_radeon_clear_rect_t; 610 611 typedef struct drm_radeon_clear { 612 unsigned int flags; 613 unsigned int clear_color; 614 unsigned int clear_depth; 615 unsigned int color_mask; 616 unsigned int depth_mask; /* misnamed field: should be stencil */ 617 drm_radeon_clear_rect_t __user *depth_boxes; 618 } drm_radeon_clear_t; 619 620 typedef struct drm_radeon_vertex { 621 int prim; 622 int idx; /* Index of vertex buffer */ 623 int count; /* Number of vertices in buffer */ 624 int discard; /* Client finished with buffer? */ 625 } drm_radeon_vertex_t; 626 627 typedef struct drm_radeon_indices { 628 int prim; 629 int idx; 630 int start; 631 int end; 632 int discard; /* Client finished with buffer? */ 633 } drm_radeon_indices_t; 634 635 /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices 636 * - allows multiple primitives and state changes in a single ioctl 637 * - supports driver change to emit native primitives 638 */ 639 typedef struct drm_radeon_vertex2 { 640 int idx; /* Index of vertex buffer */ 641 int discard; /* Client finished with buffer? */ 642 int nr_states; 643 drm_radeon_state_t __user *state; 644 int nr_prims; 645 drm_radeon_prim_t __user *prim; 646 } drm_radeon_vertex2_t; 647 648 /* v1.3 - obsoletes drm_radeon_vertex2 649 * - allows arbitrarily large cliprect list 650 * - allows updating of tcl packet, vector and scalar state 651 * - allows memory-efficient description of state updates 652 * - allows state to be emitted without a primitive 653 * (for clears, ctx switches) 654 * - allows more than one dma buffer to be referenced per ioctl 655 * - supports tcl driver 656 * - may be extended in future versions with new cmd types, packets 657 */ 658 typedef struct drm_radeon_cmd_buffer { 659 int bufsz; 660 char __user *buf; 661 int nbox; 662 struct drm_clip_rect __user *boxes; 663 } drm_radeon_cmd_buffer_t; 664 665 typedef struct drm_radeon_tex_image { 666 unsigned int x, y; /* Blit coordinates */ 667 unsigned int width, height; 668 const void __user *data; 669 } drm_radeon_tex_image_t; 670 671 typedef struct drm_radeon_texture { 672 unsigned int offset; 673 int pitch; 674 int format; 675 int width; /* Texture image coordinates */ 676 int height; 677 drm_radeon_tex_image_t __user *image; 678 } drm_radeon_texture_t; 679 680 typedef struct drm_radeon_stipple { 681 unsigned int __user *mask; 682 } drm_radeon_stipple_t; 683 684 typedef struct drm_radeon_indirect { 685 int idx; 686 int start; 687 int end; 688 int discard; 689 } drm_radeon_indirect_t; 690 691 /* enum for card type parameters */ 692 #define RADEON_CARD_PCI 0 693 #define RADEON_CARD_AGP 1 694 #define RADEON_CARD_PCIE 2 695 696 /* 1.3: An ioctl to get parameters that aren't available to the 3d 697 * client any other way. 698 */ 699 #define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ 700 #define RADEON_PARAM_LAST_FRAME 2 701 #define RADEON_PARAM_LAST_DISPATCH 3 702 #define RADEON_PARAM_LAST_CLEAR 4 703 /* Added with DRM version 1.6. */ 704 #define RADEON_PARAM_IRQ_NR 5 705 #define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ 706 /* Added with DRM version 1.8. */ 707 #define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ 708 #define RADEON_PARAM_STATUS_HANDLE 8 709 #define RADEON_PARAM_SAREA_HANDLE 9 710 #define RADEON_PARAM_GART_TEX_HANDLE 10 711 #define RADEON_PARAM_SCRATCH_OFFSET 11 712 #define RADEON_PARAM_CARD_TYPE 12 713 #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ 714 #define RADEON_PARAM_FB_LOCATION 14 /* FB location */ 715 #define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ 716 #define RADEON_PARAM_DEVICE_ID 16 717 #define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ 718 719 typedef struct drm_radeon_getparam { 720 int param; 721 void __user *value; 722 } drm_radeon_getparam_t; 723 724 /* 1.6: Set up a memory manager for regions of shared memory: 725 */ 726 #define RADEON_MEM_REGION_GART 1 727 #define RADEON_MEM_REGION_FB 2 728 729 typedef struct drm_radeon_mem_alloc { 730 int region; 731 int alignment; 732 int size; 733 int __user *region_offset; /* offset from start of fb or GART */ 734 } drm_radeon_mem_alloc_t; 735 736 typedef struct drm_radeon_mem_free { 737 int region; 738 int region_offset; 739 } drm_radeon_mem_free_t; 740 741 typedef struct drm_radeon_mem_init_heap { 742 int region; 743 int size; 744 int start; 745 } drm_radeon_mem_init_heap_t; 746 747 /* 1.6: Userspace can request & wait on irq's: 748 */ 749 typedef struct drm_radeon_irq_emit { 750 int __user *irq_seq; 751 } drm_radeon_irq_emit_t; 752 753 typedef struct drm_radeon_irq_wait { 754 int irq_seq; 755 } drm_radeon_irq_wait_t; 756 757 /* 1.10: Clients tell the DRM where they think the framebuffer is located in 758 * the card's address space, via a new generic ioctl to set parameters 759 */ 760 761 typedef struct drm_radeon_setparam { 762 unsigned int param; 763 int64_t value; 764 } drm_radeon_setparam_t; 765 766 #define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ 767 #define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ 768 #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ 769 #define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ 770 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ 771 #define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ 772 /* 1.14: Clients can allocate/free a surface 773 */ 774 typedef struct drm_radeon_surface_alloc { 775 unsigned int address; 776 unsigned int size; 777 unsigned int flags; 778 } drm_radeon_surface_alloc_t; 779 780 typedef struct drm_radeon_surface_free { 781 unsigned int address; 782 } drm_radeon_surface_free_t; 783 784 #define DRM_RADEON_VBLANK_CRTC1 1 785 #define DRM_RADEON_VBLANK_CRTC2 2 786 787 /* 788 * Kernel modesetting world below. 789 */ 790 #define RADEON_GEM_DOMAIN_CPU 0x1 791 #define RADEON_GEM_DOMAIN_GTT 0x2 792 #define RADEON_GEM_DOMAIN_VRAM 0x4 793 794 struct drm_radeon_gem_info { 795 uint64_t gart_size; 796 uint64_t vram_size; 797 uint64_t vram_visible; 798 }; 799 800 #define RADEON_GEM_NO_BACKING_STORE 1 801 802 struct drm_radeon_gem_create { 803 uint64_t size; 804 uint64_t alignment; 805 uint32_t handle; 806 uint32_t initial_domain; 807 uint32_t flags; 808 }; 809 810 #define RADEON_TILING_MACRO 0x1 811 #define RADEON_TILING_MICRO 0x2 812 #define RADEON_TILING_SWAP_16BIT 0x4 813 #define RADEON_TILING_SWAP_32BIT 0x8 814 /* this object requires a surface when mapped - i.e. front buffer */ 815 #define RADEON_TILING_SURFACE 0x10 816 #define RADEON_TILING_MICRO_SQUARE 0x20 817 #define RADEON_TILING_EG_BANKW_SHIFT 8 818 #define RADEON_TILING_EG_BANKW_MASK 0xf 819 #define RADEON_TILING_EG_BANKH_SHIFT 12 820 #define RADEON_TILING_EG_BANKH_MASK 0xf 821 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 822 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf 823 #define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 824 #define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf 825 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 826 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf 827 828 struct drm_radeon_gem_set_tiling { 829 uint32_t handle; 830 uint32_t tiling_flags; 831 uint32_t pitch; 832 }; 833 834 struct drm_radeon_gem_get_tiling { 835 uint32_t handle; 836 uint32_t tiling_flags; 837 uint32_t pitch; 838 }; 839 840 struct drm_radeon_gem_mmap { 841 uint32_t handle; 842 uint32_t pad; 843 uint64_t offset; 844 uint64_t size; 845 uint64_t addr_ptr; 846 }; 847 848 struct drm_radeon_gem_set_domain { 849 uint32_t handle; 850 uint32_t read_domains; 851 uint32_t write_domain; 852 }; 853 854 struct drm_radeon_gem_wait_idle { 855 uint32_t handle; 856 uint32_t pad; 857 }; 858 859 struct drm_radeon_gem_busy { 860 uint32_t handle; 861 uint32_t domain; 862 }; 863 864 struct drm_radeon_gem_pread { 865 /** Handle for the object being read. */ 866 uint32_t handle; 867 uint32_t pad; 868 /** Offset into the object to read from */ 869 uint64_t offset; 870 /** Length of data to read */ 871 uint64_t size; 872 /** Pointer to write the data into. */ 873 /* void *, but pointers are not 32/64 compatible */ 874 uint64_t data_ptr; 875 }; 876 877 struct drm_radeon_gem_pwrite { 878 /** Handle for the object being written to. */ 879 uint32_t handle; 880 uint32_t pad; 881 /** Offset into the object to write to */ 882 uint64_t offset; 883 /** Length of data to write */ 884 uint64_t size; 885 /** Pointer to read the data from. */ 886 /* void *, but pointers are not 32/64 compatible */ 887 uint64_t data_ptr; 888 }; 889 890 #define RADEON_VA_MAP 1 891 #define RADEON_VA_UNMAP 2 892 893 #define RADEON_VA_RESULT_OK 0 894 #define RADEON_VA_RESULT_ERROR 1 895 #define RADEON_VA_RESULT_VA_EXIST 2 896 897 #define RADEON_VM_PAGE_VALID (1 << 0) 898 #define RADEON_VM_PAGE_READABLE (1 << 1) 899 #define RADEON_VM_PAGE_WRITEABLE (1 << 2) 900 #define RADEON_VM_PAGE_SYSTEM (1 << 3) 901 #define RADEON_VM_PAGE_SNOOPED (1 << 4) 902 903 struct drm_radeon_gem_va { 904 uint32_t handle; 905 uint32_t operation; 906 uint32_t vm_id; 907 uint32_t flags; 908 uint64_t offset; 909 }; 910 911 #define RADEON_CHUNK_ID_RELOCS 0x01 912 #define RADEON_CHUNK_ID_IB 0x02 913 #define RADEON_CHUNK_ID_FLAGS 0x03 914 #define RADEON_CHUNK_ID_CONST_IB 0x04 915 916 /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ 917 #define RADEON_CS_KEEP_TILING_FLAGS 0x01 918 #define RADEON_CS_USE_VM 0x02 919 #define RADEON_CS_END_OF_FRAME 0x04 /* a hint from userspace which CS is the last one */ 920 /* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */ 921 #define RADEON_CS_RING_GFX 0 922 #define RADEON_CS_RING_COMPUTE 1 923 #define RADEON_CS_RING_DMA 2 924 /* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */ 925 /* 0 = normal, + = higher priority, - = lower priority */ 926 927 struct drm_radeon_cs_chunk { 928 uint32_t chunk_id; 929 uint32_t length_dw; 930 uint64_t chunk_data; 931 }; 932 933 /* drm_radeon_cs_reloc.flags */ 934 935 struct drm_radeon_cs_reloc { 936 uint32_t handle; 937 uint32_t read_domains; 938 uint32_t write_domain; 939 uint32_t flags; 940 }; 941 942 struct drm_radeon_cs { 943 uint32_t num_chunks; 944 uint32_t cs_id; 945 /* this points to uint64_t * which point to cs chunks */ 946 uint64_t chunks; 947 /* updates to the limits after this CS ioctl */ 948 uint64_t gart_limit; 949 uint64_t vram_limit; 950 }; 951 952 #define RADEON_INFO_DEVICE_ID 0x00 953 #define RADEON_INFO_NUM_GB_PIPES 0x01 954 #define RADEON_INFO_NUM_Z_PIPES 0x02 955 #define RADEON_INFO_ACCEL_WORKING 0x03 956 #define RADEON_INFO_CRTC_FROM_ID 0x04 957 #define RADEON_INFO_ACCEL_WORKING2 0x05 958 #define RADEON_INFO_TILING_CONFIG 0x06 959 #define RADEON_INFO_WANT_HYPERZ 0x07 960 #define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ 961 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ 962 #define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */ 963 #define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ 964 #define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */ 965 #define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ 966 /* virtual address start, va < start are reserved by the kernel */ 967 #define RADEON_INFO_VA_START 0x0e 968 /* maximum size of ib using the virtual memory cs */ 969 #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f 970 /* max pipes - needed for compute shaders */ 971 #define RADEON_INFO_MAX_PIPES 0x10 972 /* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */ 973 #define RADEON_INFO_TIMESTAMP 0x11 974 /* max shader engines (SE) - needed for geometry shaders, etc. */ 975 #define RADEON_INFO_MAX_SE 0x12 976 /* max SH per SE */ 977 #define RADEON_INFO_MAX_SH_PER_SE 0x13 978 979 struct drm_radeon_info { 980 uint32_t request; 981 uint32_t pad; 982 uint64_t value; 983 }; 984 985 #endif 986