1 /* $OpenBSD: psl.h,v 1.18 2003/06/02 23:27:54 millert Exp $ */
2 /* $NetBSD: psl.h,v 1.12 1997/03/10 21:49:11 pk Exp $ */
3
4 /*
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This software was developed by the Computer Systems Engineering group
9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10 * contributed to Berkeley.
11 *
12 * All advertising materials mentioning features or use of this software
13 * must display the following acknowledgement:
14 * This product includes software developed by the University of
15 * California, Lawrence Berkeley Laboratory.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. Neither the name of the University nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * SUCH DAMAGE.
40 *
41 * @(#)psl.h 8.1 (Berkeley) 6/11/93
42 */
43
44 #ifndef PSR_IMPL
45
46 /*
47 * SPARC Process Status Register (in psl.h for hysterical raisins).
48 *
49 * The picture in the Sun manuals looks like this:
50 * 1 1
51 * 31 28 27 24 23 20 19 14 3 2 11 8 7 6 5 4 0
52 * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
53 * | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP |
54 * | | |n z v c| |C|F| | |S|T| |
55 * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
56 */
57
58 #define PSR_IMPL 0xf0000000 /* implementation */
59 #define PSR_VER 0x0f000000 /* version */
60 #define PSR_ICC 0x00f00000 /* integer condition codes */
61 #define PSR_N 0x00800000 /* negative */
62 #define PSR_Z 0x00400000 /* zero */
63 #define PSR_O 0x00200000 /* overflow */
64 #define PSR_C 0x00100000 /* carry */
65 #define PSR_EC 0x00002000 /* coprocessor enable */
66 #define PSR_EF 0x00001000 /* FP enable */
67 #define PSR_PIL 0x00000f00 /* interrupt level */
68 #define PSR_S 0x00000080 /* supervisor (kernel) mode */
69 #define PSR_PS 0x00000040 /* previous supervisor mode (traps) */
70 #define PSR_ET 0x00000020 /* trap enable */
71 #define PSR_CWP 0x0000001f /* current window pointer */
72
73 #define PSR_BITS "\20\16EC\15EF\10S\7PS\6ET"
74
75 /*
76 * Various interrupt levels.
77 */
78 #define IPL_NONE 0
79 #define IPL_SOFTINT 1
80 #define IPL_SOFTCLOCK IPL_SOFTINT /* softclock() interrupts */
81 #define IPL_SOFTNET IPL_SOFTINT /* soft network interrupts */
82 #define IPL_AUSOFT 4 /* audio soft interrupts */
83 #define IPL_FDSOFT 4 /* floppy soft interrupts */
84 #define IPL_BIO 5 /* block devices are at 5 and below */
85 #define IPL_TTY 6 /* tty soft interrupts */
86 #define IPL_NET 7 /* network hardware at 7 or below */
87 #define IPL_VM 7 /* max(BIO, NET, TTY) */
88 #define IPL_FB 9 /* framebuffer interrupts */
89 #define IPL_CLOCK 10 /* hardclock() */
90 #define IPL_FD 11 /* hard floppy interrupts. */
91 #define IPL_ZS 12 /* zs interrupts */
92 /*
93 * XXX - this is called AUHARD instead of AUDIO because of some confusion
94 * with how MI audio code handles this. Stay tuned for a change in the future
95 */
96 #define IPL_AUHARD 13 /* hard audio interrupts */
97 #define IPL_STATCLOCK 14 /* statclock() */
98
99 #if defined(_KERNEL) && !defined(_LOCORE)
100
101 static __inline int getpsr(void);
102 static __inline void setpsr(int);
103 static __inline int spl0(void);
104 static __inline int splhigh(void);
105 static __inline void splx(int);
106 static __inline int getmid(void);
107
108 /*
109 * GCC pseudo-functions for manipulating PSR (primarily PIL field).
110 */
111 static __inline int
getpsr()112 getpsr()
113 {
114 int psr;
115
116 __asm __volatile("rd %%psr,%0" : "=r" (psr));
117 return (psr);
118 }
119
120 static __inline int
getmid()121 getmid()
122 {
123 int mid;
124
125 __asm __volatile("rd %%tbr,%0" : "=r" (mid));
126 return ((mid >> 20) & 0x3);
127 }
128
129 static __inline void
setpsr(newpsr)130 setpsr(newpsr)
131 int newpsr;
132 {
133 __asm __volatile("wr %0,0,%%psr" : : "r" (newpsr));
134 __asm __volatile("nop");
135 __asm __volatile("nop");
136 __asm __volatile("nop");
137 }
138
139 static __inline int
spl0()140 spl0()
141 {
142 int psr, oldipl;
143
144 /*
145 * wrpsr xors two values: we choose old psr and old ipl here,
146 * which gives us the same value as the old psr but with all
147 * the old PIL bits turned off.
148 */
149 __asm __volatile("rd %%psr,%0" : "=r" (psr));
150 oldipl = psr & PSR_PIL;
151 __asm __volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl));
152
153 /*
154 * Three instructions must execute before we can depend
155 * on the bits to be changed.
156 */
157 __asm __volatile("nop; nop; nop");
158 return (oldipl);
159 }
160
161 #ifdef DIAGNOSTIC
162 /*
163 * Although this function is implemented in MI code, it must be in this MD
164 * header because we don't want this header to include MI includes.
165 */
166 void splassert_fail(int, int, const char *);
167 extern int splassert_ctl;
168 void splassert_check(int, const char *);
169 #define splassert(__wantipl) do { \
170 if (__predict_false(splassert_ctl > 0)) { \
171 splassert_check(__wantipl, __func__); \
172 } \
173 } while (0)
174 #else
175 #define splassert(wantipl) do { /* nada */ } while (0)
176 #endif
177
178 /*
179 * PIL 1 through 14 can use this macro.
180 * (spl0 and splhigh are special since they put all 0s or all 1s
181 * into the ipl field.)
182 */
183 #define SPL(name, newipl) \
184 static __inline int name(void); \
185 static __inline int name() \
186 { \
187 int psr, oldipl; \
188 __asm __volatile("rd %%psr,%0" : "=r" (psr)); \
189 oldipl = psr & PSR_PIL; \
190 psr &= ~oldipl; \
191 __asm __volatile("wr %0,%1,%%psr" : : \
192 "r" (psr), "n" ((newipl) << 8)); \
193 __asm __volatile("nop; nop; nop"); \
194 __asm __volatile("":::"memory"); /* protect from reordering */ \
195 return (oldipl); \
196 }
197 /* A non-priority-decreasing version of SPL */
198 #define SPLHOLD(name, newipl) \
199 static __inline int name(void); \
200 static __inline int name() \
201 { \
202 int psr, oldipl; \
203 __asm __volatile("rd %%psr,%0" : "=r" (psr)); \
204 oldipl = psr & PSR_PIL; \
205 if ((newipl << 8) <= oldipl) \
206 return oldipl; \
207 psr &= ~oldipl; \
208 __asm __volatile("wr %0,%1,%%psr" : : \
209 "r" (psr), "n" ((newipl) << 8)); \
210 __asm __volatile("nop; nop; nop"); \
211 __asm __volatile("":::"memory"); /* protect from reordering */ \
212 return (oldipl); \
213 }
214
SPLHOLD(splsoftint,IPL_SOFTINT)215 SPLHOLD(splsoftint, IPL_SOFTINT)
216 #define splsoftclock splsoftint
217 #define splsoftnet splsoftint
218 SPL(spllowersoftclock, IPL_SOFTCLOCK)
219 SPLHOLD(splausoft, IPL_AUSOFT)
220 SPLHOLD(splfdsoft, IPL_FDSOFT)
221 SPLHOLD(splbio, IPL_BIO)
222 SPLHOLD(splnet, IPL_NET)
223 SPLHOLD(spltty, IPL_TTY)
224 SPLHOLD(splvm, IPL_VM)
225 /* XXX - the following two should die. */
226 #define splimp splvm
227 SPLHOLD(splclock, IPL_CLOCK)
228 SPLHOLD(splfd, IPL_FD)
229 SPLHOLD(splzs, IPL_ZS)
230 SPLHOLD(splaudio, IPL_AUHARD)
231 SPLHOLD(splstatclock, IPL_STATCLOCK)
232
233 static __inline int splhigh()
234 {
235 int psr, oldipl;
236
237 __asm __volatile("rd %%psr,%0" : "=r" (psr));
238 __asm __volatile("wr %0,0,%%psr" : : "r" (psr | PSR_PIL));
239 __asm __volatile("and %1,%2,%0; nop; nop" : "=r" (oldipl) : \
240 "r" (psr), "n" (PSR_PIL));
241 __asm __volatile("":::"memory"); /* protect from reordering */
242 return (oldipl);
243 }
244
245 /* splx does not have a return value */
splx(newipl)246 static __inline void splx(newipl)
247 int newipl;
248 {
249 int psr;
250
251 __asm __volatile("":::"memory"); /* protect from reordering */
252 __asm __volatile("rd %%psr,%0" : "=r" (psr));
253 __asm __volatile("wr %0,%1,%%psr" : : \
254 "r" (psr & ~PSR_PIL), "rn" (newipl));
255 __asm __volatile("nop; nop; nop");
256 }
257 #endif /* KERNEL && !_LOCORE */
258
259 #endif /* PSR_IMPL */
260