1 /* Moxie Simulator definition.
2    Copyright (C) 2009-2024 Free Software Foundation, Inc.
3 
4 This file is part of the GNU simulators.
5 
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
10 
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 GNU General Public License for more details.
15 
16 You should have received a copy of the GNU General Public License
17 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
18 
19 #ifndef SH_SIM_H
20 #define SH_SIM_H
21 
22 typedef struct
23 {
24   int regs[20];
25 } regstacktype;
26 
27 typedef union
28 {
29 
30   struct
31   {
32     int regs[16];
33     int pc;
34 
35     /* System registers.  For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
36        which are located in fregs.  Probably should include pc too - to avoid
37        alignment repercussions.  */
38     union {
39       struct {
40           int mach;
41           int macl;
42           int pr;
43           int dummy3, dummy4;
44           int fpul; /* A1 for sh-dsp -  but only for movs etc.  */
45           int fpscr; /* dsr for sh-dsp */
46 
47           /* sh3e / sh-dsp */
48           union fregs_u {
49             float f[16];
50             double d[8];
51             int i[16];
52           } fregs[2];
53       };
54       int sregs[39];
55     };
56 
57     /* Control registers; on the SH4, ldc / stc is privileged, except when
58        accessing gbr.  */
59     union
60       {
61           struct
62             {
63               int sr;
64               int gbr;
65               int vbr;
66               int ssr;
67               int spc;
68               int mod;
69               /* sh-dsp */
70               int rs;
71               int re;
72               /* sh3 */
73               int bank[8];
74               int dbr;                  /* debug base register */
75               int sgr;                  /* saved gr15 */
76               int ldst;                 /* load/store flag (boolean) */
77               int tbr;
78               int ibcr;                 /* sh2a bank control register */
79               int ibnr;                 /* sh2a bank number register */
80             };
81           int cregs[16];
82       };
83 
84     unsigned char *insn_end;
85 
86     int ticks;
87     int stalls;
88     int memstalls;
89     int cycles;
90     int insts;
91 
92     int prevlock;
93     int thislock;
94     int exception;
95 
96     int end_of_registers;
97 
98     int msize;
99 #define PROFILE_FREQ 1
100 #define PROFILE_SHIFT 2
101     int profile;
102     unsigned short *profile_hist;
103     unsigned char *memory;
104     int xyram_select, xram_start, yram_start;
105     unsigned char *xmem;
106     unsigned char *ymem;
107     unsigned char *xmem_offset;
108     unsigned char *ymem_offset;
109     unsigned long bfd_mach;
110     regstacktype *regstack;
111   } asregs;
112   int asints[40];
113 } saved_state_type;
114 
115 /* TODO: Move into sim_cpu.  */
116 extern saved_state_type saved_state;
117 
118 #endif
119