1 /*-
2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: stable/10/sys/dev/mlx5/mlx5_en/en.h 359855 2020-04-13 09:02:17Z hselasky $
26 */
27
28 #ifndef _MLX5_EN_H_
29 #define _MLX5_EN_H_
30
31 #include <linux/kmod.h>
32 #include <linux/page.h>
33 #include <linux/slab.h>
34 #include <linux/if_vlan.h>
35 #include <linux/if_ether.h>
36 #include <linux/vmalloc.h>
37 #include <linux/moduleparam.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41
42 #include <netinet/in_systm.h>
43 #include <netinet/in.h>
44 #include <netinet/if_ether.h>
45 #include <netinet/ip.h>
46 #include <netinet/ip6.h>
47 #include <netinet/tcp.h>
48 #include <netinet/tcp_lro.h>
49 #include <netinet/udp.h>
50 #include <net/ethernet.h>
51 #include <sys/buf_ring.h>
52
53 #if (__FreeBSD_version >= 1100000)
54 #include "opt_rss.h"
55 #endif
56
57 #ifdef RSS
58 #include <net/rss_config.h>
59 #include <netinet/in_rss.h>
60 #endif
61
62 #include <machine/bus.h>
63
64 #ifdef HAVE_TURBO_LRO
65 #include "tcp_tlro.h"
66 #endif
67
68 #include <dev/mlx5/driver.h>
69 #include <dev/mlx5/qp.h>
70 #include <dev/mlx5/cq.h>
71 #include <dev/mlx5/vport.h>
72 #include <dev/mlx5/diagnostics.h>
73
74 #include <dev/mlx5/mlx5_core/wq.h>
75 #include <dev/mlx5/mlx5_core/transobj.h>
76 #include <dev/mlx5/mlx5_core/mlx5_core.h>
77
78 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7
79 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
80 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe
81
82 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7
83 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
84 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe
85
86 #define MLX5E_MAX_RX_SEGS 7
87
88 #ifndef MLX5E_MAX_RX_BYTES
89 #define MLX5E_MAX_RX_BYTES MCLBYTES
90 #endif
91
92 #if (MLX5E_MAX_RX_SEGS == 1)
93 /* FreeBSD HW LRO is limited by 16KB - the size of max mbuf */
94 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES
95 #else
96 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \
97 MIN(65535, MLX5E_MAX_RX_SEGS * MLX5E_MAX_RX_BYTES)
98 #endif
99 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
100 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
101 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
102 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
103 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
104 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
105 #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7
106 #define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE
107 #define MLX5E_HW2SW_MTU(hwmtu) \
108 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
109 #define MLX5E_SW2HW_MTU(swmtu) \
110 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
111 #define MLX5E_SW2MB_MTU(swmtu) \
112 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN)
113 #define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */
114 #define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet
115 * jumbo frames */
116
117 #define MLX5E_BUDGET_MAX 8192 /* RX and TX */
118 #define MLX5E_RX_BUDGET_MAX 256
119 #define MLX5E_SQ_BF_BUDGET 16
120 #define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */
121
122 #define MLX5E_MAX_TX_NUM_TC 8 /* units */
123 #define MLX5E_MAX_TX_HEADER 128 /* bytes */
124 #define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */
125 #define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */
126 #define MLX5E_MAX_TX_MBUF_FRAGS \
127 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \
128 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \
129 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */
130 #define MLX5E_MAX_TX_INLINE \
131 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \
132 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */
133
134 MALLOC_DECLARE(M_MLX5EN);
135
136 struct mlx5_core_dev;
137 struct mlx5e_cq;
138
139 typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *);
140
141 #define MLX5E_STATS_COUNT(a,b,c,d) a
142 #define MLX5E_STATS_VAR(a,b,c,d) b;
143 #define MLX5E_STATS_DESC(a,b,c,d) c, d,
144
145 #define MLX5E_VPORT_STATS(m) \
146 /* HW counters */ \
147 m(+1, u64 rx_packets, "rx_packets", "Received packets") \
148 m(+1, u64 rx_bytes, "rx_bytes", "Received bytes") \
149 m(+1, u64 tx_packets, "tx_packets", "Transmitted packets") \
150 m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes") \
151 m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \
152 m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes") \
153 m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \
154 m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \
155 m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \
156 m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \
157 m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \
158 m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \
159 m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \
160 m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \
161 m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \
162 m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \
163 m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \
164 m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \
165 m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \
166 m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \
167 m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \
168 /* SW counters */ \
169 m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets") \
170 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes") \
171 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \
172 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \
173 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \
174 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \
175 m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \
176 m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \
177 m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \
178 m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \
179 m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \
180 m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors")
181
182 #define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT))
183
184 struct mlx5e_vport_stats {
185 struct sysctl_ctx_list ctx;
186 u64 arg [0];
187 MLX5E_VPORT_STATS(MLX5E_STATS_VAR)
188 u32 rx_out_of_buffer_prev;
189 };
190
191 #define MLX5E_PPORT_IEEE802_3_STATS(m) \
192 m(+1, u64 frames_tx, "frames_tx", "Frames transmitted") \
193 m(+1, u64 frames_rx, "frames_rx", "Frames received") \
194 m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors") \
195 m(+1, u64 alignment_err, "alignment_err", "Alignment errors") \
196 m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted") \
197 m(+1, u64 octets_received, "octets_received", "Bytes received") \
198 m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \
199 m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \
200 m(+1, u64 multicast_rx, "multicast_rx", "Multicast received") \
201 m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received") \
202 m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \
203 m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \
204 m(+1, u64 too_long_errors, "too_long_errors", "Too long errors") \
205 m(+1, u64 symbol_err, "symbol_err", "Symbol errors") \
206 m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \
207 m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received") \
208 m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \
209 m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \
210 m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted")
211
212 #define MLX5E_PPORT_RFC2819_STATS(m) \
213 m(+1, u64 drop_events, "drop_events", "Dropped events") \
214 m(+1, u64 octets, "octets", "Octets") \
215 m(+1, u64 pkts, "pkts", "Packets") \
216 m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets") \
217 m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets") \
218 m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \
219 m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets") \
220 m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets") \
221 m(+1, u64 fragments, "fragments", "Fragments") \
222 m(+1, u64 jabbers, "jabbers", "Jabbers") \
223 m(+1, u64 collisions, "collisions", "Collisions")
224
225 #define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \
226 m(+1, u64 p64octets, "p64octets", "Bytes") \
227 m(+1, u64 p65to127octets, "p65to127octets", "Bytes") \
228 m(+1, u64 p128to255octets, "p128to255octets", "Bytes") \
229 m(+1, u64 p256to511octets, "p256to511octets", "Bytes") \
230 m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes") \
231 m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes") \
232 m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes") \
233 m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes") \
234 m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes") \
235 m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes")
236
237 #define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
238 m(+1, u64 in_octets, "in_octets", "In octets") \
239 m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \
240 m(+1, u64 in_discards, "in_discards", "In discards") \
241 m(+1, u64 in_errors, "in_errors", "In errors") \
242 m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \
243 m(+1, u64 out_octets, "out_octets", "Out octets") \
244 m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \
245 m(+1, u64 out_discards, "out_discards", "Out discards") \
246 m(+1, u64 out_errors, "out_errors", "Out errors") \
247 m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \
248 m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \
249 m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \
250 m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets")
251
252 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \
253 m(+1, u64 time_since_last_clear, "time_since_last_clear", \
254 "Time since the last counters clear event (msec)") \
255 m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors") \
256 m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter") \
257 m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0", \
258 "Indicates the number of PRBS errors on lane 0") \
259 m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1", \
260 "Indicates the number of PRBS errors on lane 1") \
261 m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2", \
262 "Indicates the number of PRBS errors on lane 2") \
263 m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3", \
264 "Indicates the number of PRBS errors on lane 3") \
265 m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \
266 "FEC correctable block counter lane 0") \
267 m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \
268 "FEC correctable block counter lane 1") \
269 m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \
270 "FEC correctable block counter lane 2") \
271 m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \
272 "FEC correctable block counter lane 3") \
273 m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks", \
274 "FEC correcable block counter") \
275 m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \
276 "FEC uncorrecable block counter") \
277 m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks", \
278 "The number of RS-FEC blocks received that had no errors") \
279 m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks", \
280 "The number of corrected RS-FEC blocks received that had" \
281 "exactly 1 error symbol") \
282 m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total", \
283 "Port FEC corrected symbol counter") \
284 m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \
285 "FEC corrected symbol counter lane 0") \
286 m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \
287 "FEC corrected symbol counter lane 1") \
288 m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \
289 "FEC corrected symbol counter lane 2") \
290 m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \
291 "FEC corrected symbol counter lane 3") \
292
293 /*
294 * Make sure to update mlx5e_update_pport_counters()
295 * when adding a new MLX5E_PPORT_STATS block
296 */
297 #define MLX5E_PPORT_STATS(m) \
298 MLX5E_PPORT_IEEE802_3_STATS(m) \
299 MLX5E_PPORT_RFC2819_STATS(m)
300
301 #define MLX5E_PORT_STATS_DEBUG(m) \
302 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \
303 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
304 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m)
305
306 #define MLX5E_PPORT_IEEE802_3_STATS_NUM \
307 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT))
308 #define MLX5E_PPORT_RFC2819_STATS_NUM \
309 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT))
310 #define MLX5E_PPORT_STATS_NUM \
311 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT))
312
313 #define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \
314 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT))
315 #define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \
316 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT))
317 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \
318 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT))
319 #define MLX5E_PORT_STATS_DEBUG_NUM \
320 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT))
321
322 struct mlx5e_pport_stats {
323 struct sysctl_ctx_list ctx;
324 u64 arg [0];
325 MLX5E_PPORT_STATS(MLX5E_STATS_VAR)
326 };
327
328 struct mlx5e_port_stats_debug {
329 struct sysctl_ctx_list ctx;
330 u64 arg [0];
331 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR)
332 };
333
334 #define MLX5E_RQ_STATS(m) \
335 m(+1, u64 packets, "packets", "Received packets") \
336 m(+1, u64 csum_none, "csum_none", "Received packets") \
337 m(+1, u64 lro_packets, "lro_packets", "Received packets") \
338 m(+1, u64 lro_bytes, "lro_bytes", "Received packets") \
339 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \
340 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \
341 m(+1, u64 wqe_err, "wqe_err", "Received packets")
342
343 #define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT))
344
345 struct mlx5e_rq_stats {
346 struct sysctl_ctx_list ctx;
347 u64 arg [0];
348 MLX5E_RQ_STATS(MLX5E_STATS_VAR)
349 };
350
351 #define MLX5E_SQ_STATS(m) \
352 m(+1, u64 packets, "packets", "Transmitted packets") \
353 m(+1, u64 tso_packets, "tso_packets", "Transmitted packets") \
354 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes") \
355 m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets") \
356 m(+1, u64 defragged, "defragged", "Transmitted packets") \
357 m(+1, u64 dropped, "dropped", "Transmitted packets") \
358 m(+1, u64 enobuf, "enobuf", "Transmitted packets") \
359 m(+1, u64 nop, "nop", "Transmitted packets")
360
361 #define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT))
362
363 struct mlx5e_sq_stats {
364 struct sysctl_ctx_list ctx;
365 u64 arg [0];
366 MLX5E_SQ_STATS(MLX5E_STATS_VAR)
367 };
368
369 struct mlx5e_stats {
370 struct mlx5e_vport_stats vport;
371 struct mlx5e_pport_stats pport;
372 struct mlx5e_port_stats_debug port_stats_debug;
373 };
374
375 struct mlx5e_rq_param {
376 u32 rqc [MLX5_ST_SZ_DW(rqc)];
377 struct mlx5_wq_param wq;
378 };
379
380 struct mlx5e_sq_param {
381 u32 sqc [MLX5_ST_SZ_DW(sqc)];
382 struct mlx5_wq_param wq;
383 };
384
385 struct mlx5e_cq_param {
386 u32 cqc [MLX5_ST_SZ_DW(cqc)];
387 struct mlx5_wq_param wq;
388 };
389
390 struct mlx5e_params {
391 u8 log_sq_size;
392 u8 log_rq_size;
393 u16 num_channels;
394 u8 default_vlan_prio;
395 u8 num_tc;
396 u8 rx_cq_moderation_mode;
397 u8 tx_cq_moderation_mode;
398 u16 rx_cq_moderation_usec;
399 u16 rx_cq_moderation_pkts;
400 u16 tx_cq_moderation_usec;
401 u16 tx_cq_moderation_pkts;
402 u16 min_rx_wqes;
403 bool hw_lro_en;
404 bool cqe_zipping_en;
405 u32 lro_wqe_sz;
406 u16 rx_hash_log_tbl_sz;
407 u32 tx_pauseframe_control;
408 u32 rx_pauseframe_control;
409 u16 tx_max_inline;
410 u8 tx_min_inline_mode;
411 u8 channels_rsss;
412 };
413
414 #define MLX5E_PARAMS(m) \
415 m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \
416 m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \
417 m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size") \
418 m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \
419 m(+1, u64 channels, "channels", "Default number of channels") \
420 m(+1, u64 channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \
421 m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \
422 m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \
423 m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \
424 m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \
425 m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE mode 1: CQE mode") \
426 m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \
427 m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \
428 m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \
429 m(+1, u64 tx_bufring_disable, "tx_bufring_disable", "0: Enable bufring 1: Disable bufring") \
430 m(+1, u64 tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \
431 m(+1, u64 tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \
432 m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") \
433 m(+1, u64 cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \
434 m(+1, u64 diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \
435 m(+1, u64 diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \
436 m(+1, u64 hw_mtu, "hw_mtu", "Current hardware MTU value")
437
438 #define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT))
439
440 struct mlx5e_params_ethtool {
441 u64 arg [0];
442 MLX5E_PARAMS(MLX5E_STATS_VAR)
443 };
444
445 /* EEPROM Standards for plug in modules */
446 #ifndef MLX5E_ETH_MODULE_SFF_8472
447 #define MLX5E_ETH_MODULE_SFF_8472 0x1
448 #define MLX5E_ETH_MODULE_SFF_8472_LEN 128
449 #endif
450
451 #ifndef MLX5E_ETH_MODULE_SFF_8636
452 #define MLX5E_ETH_MODULE_SFF_8636 0x2
453 #define MLX5E_ETH_MODULE_SFF_8636_LEN 256
454 #endif
455
456 #ifndef MLX5E_ETH_MODULE_SFF_8436
457 #define MLX5E_ETH_MODULE_SFF_8436 0x3
458 #define MLX5E_ETH_MODULE_SFF_8436_LEN 256
459 #endif
460
461 /* EEPROM I2C Addresses */
462 #define MLX5E_I2C_ADDR_LOW 0x50
463 #define MLX5E_I2C_ADDR_HIGH 0x51
464
465 #define MLX5E_EEPROM_LOW_PAGE 0x0
466 #define MLX5E_EEPROM_HIGH_PAGE 0x3
467
468 #define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128
469 #define MLX5E_EEPROM_PAGE_LENGTH 256
470
471 #define MLX5E_EEPROM_INFO_BYTES 0x3
472
473 struct mlx5e_cq {
474 /* data path - accessed per cqe */
475 struct mlx5_cqwq wq;
476
477 /* data path - accessed per HW polling */
478 struct mlx5_core_cq mcq;
479
480 /* control */
481 struct mlx5e_priv *priv;
482 struct mlx5_wq_ctrl wq_ctrl;
483 } __aligned(MLX5E_CACHELINE_SIZE);
484
485 struct mlx5e_rq_mbuf {
486 bus_dmamap_t dma_map;
487 caddr_t data;
488 struct mbuf *mbuf;
489 };
490
491 struct mlx5e_rq {
492 /* data path */
493 struct mlx5_wq_ll wq;
494 struct mtx mtx;
495 bus_dma_tag_t dma_tag;
496 u32 wqe_sz;
497 u32 nsegs;
498 struct mlx5e_rq_mbuf *mbuf;
499 struct ifnet *ifp;
500 struct mlx5e_rq_stats stats;
501 struct mlx5e_cq cq;
502 #ifdef HAVE_TURBO_LRO
503 struct tlro_ctrl lro;
504 #else
505 struct lro_ctrl lro;
506 #endif
507 volatile int enabled;
508 int ix;
509
510 /* control */
511 struct mlx5_wq_ctrl wq_ctrl;
512 u32 rqn;
513 struct mlx5e_channel *channel;
514 struct callout watchdog;
515 } __aligned(MLX5E_CACHELINE_SIZE);
516
517 struct mlx5e_sq_mbuf {
518 bus_dmamap_t dma_map;
519 struct mbuf *mbuf;
520 u32 num_bytes;
521 u32 num_wqebbs;
522 };
523
524 enum {
525 MLX5E_SQ_READY,
526 MLX5E_SQ_FULL
527 };
528
529 struct mlx5e_sq {
530 /* data path */
531 struct mtx lock;
532 bus_dma_tag_t dma_tag;
533 struct mtx comp_lock;
534
535 /* dirtied @completion */
536 u16 cc;
537
538 /* dirtied @xmit */
539 u16 pc __aligned(MLX5E_CACHELINE_SIZE);
540 u16 bf_offset;
541 u16 cev_counter; /* completion event counter */
542 u16 cev_factor; /* completion event factor */
543 u16 cev_next_state; /* next completion event state */
544 #define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */
545 #define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */
546 #define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */
547 u16 stopped; /* set if SQ is stopped */
548 struct callout cev_callout;
549 union {
550 u32 d32[2];
551 u64 d64;
552 } doorbell;
553 struct mlx5e_sq_stats stats;
554
555 struct mlx5e_cq cq;
556 struct task sq_task;
557 struct taskqueue *sq_tq;
558
559 /* pointers to per packet info: write@xmit, read@completion */
560 struct mlx5e_sq_mbuf *mbuf;
561 struct buf_ring *br;
562
563 /* read only */
564 struct mlx5_wq_cyc wq;
565 struct mlx5_uar uar;
566 struct ifnet *ifp;
567 u32 sqn;
568 u32 bf_buf_size;
569 u32 mkey_be;
570 u16 max_inline;
571 u8 min_inline_mode;
572 u8 vlan_inline_cap;
573
574 /* control path */
575 struct mlx5_wq_ctrl wq_ctrl;
576 struct mlx5e_priv *priv;
577 int tc;
578 unsigned int queue_state;
579 } __aligned(MLX5E_CACHELINE_SIZE);
580
581 static inline bool
mlx5e_sq_has_room_for(struct mlx5e_sq * sq,u16 n)582 mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
583 {
584 u16 cc = sq->cc;
585 u16 pc = sq->pc;
586
587 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc);
588 }
589
590 struct mlx5e_channel {
591 /* data path */
592 struct mlx5e_rq rq;
593 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC];
594 struct ifnet *ifp;
595 u32 mkey_be;
596 u8 num_tc;
597
598 /* control */
599 struct mlx5e_priv *priv;
600 int ix;
601 int cpu;
602 } __aligned(MLX5E_CACHELINE_SIZE);
603
604 enum mlx5e_traffic_types {
605 MLX5E_TT_IPV4_TCP,
606 MLX5E_TT_IPV6_TCP,
607 MLX5E_TT_IPV4_UDP,
608 MLX5E_TT_IPV6_UDP,
609 MLX5E_TT_IPV4_IPSEC_AH,
610 MLX5E_TT_IPV6_IPSEC_AH,
611 MLX5E_TT_IPV4_IPSEC_ESP,
612 MLX5E_TT_IPV6_IPSEC_ESP,
613 MLX5E_TT_IPV4,
614 MLX5E_TT_IPV6,
615 MLX5E_TT_ANY,
616 MLX5E_NUM_TT,
617 };
618
619 enum {
620 MLX5E_RQT_SPREADING = 0,
621 MLX5E_RQT_DEFAULT_RQ = 1,
622 MLX5E_NUM_RQT = 2,
623 };
624
625 struct mlx5e_eth_addr_info {
626 u8 addr [ETH_ALEN + 2];
627 u32 tt_vec;
628 u32 ft_ix[MLX5E_NUM_TT]; /* flow table index per traffic type */
629 };
630
631 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
632
633 struct mlx5e_eth_addr_hash_node;
634
635 struct mlx5e_eth_addr_hash_head {
636 struct mlx5e_eth_addr_hash_node *lh_first;
637 };
638
639 struct mlx5e_eth_addr_db {
640 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE];
641 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE];
642 struct mlx5e_eth_addr_info broadcast;
643 struct mlx5e_eth_addr_info allmulti;
644 struct mlx5e_eth_addr_info promisc;
645 bool broadcast_enabled;
646 bool allmulti_enabled;
647 bool promisc_enabled;
648 };
649
650 enum {
651 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
652 MLX5E_STATE_OPENED,
653 };
654
655 struct mlx5e_vlan_db {
656 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
657 u32 active_vlans_ft_ix[VLAN_N_VID];
658 u32 untagged_rule_ft_ix;
659 u32 any_vlan_rule_ft_ix;
660 bool filter_disabled;
661 };
662
663 struct mlx5e_flow_table {
664 void *vlan;
665 void *main;
666 };
667
668 struct mlx5e_priv {
669 struct mlx5_core_dev *mdev; /* must be first */
670
671 /* priv data path fields - start */
672 int order_base_2_num_channels;
673 int queue_mapping_channel_mask;
674 int num_tc;
675 int default_vlan_prio;
676 /* priv data path fields - end */
677
678 unsigned long state;
679 int gone;
680 #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock)
681 #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock)
682 #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock)
683 struct sx state_lock; /* Protects Interface state */
684 struct mlx5_uar cq_uar;
685 u32 pdn;
686 u32 tdn;
687 struct mlx5_core_mr mr;
688
689 struct mlx5e_channel *volatile *channel;
690 u32 tisn[MLX5E_MAX_TX_NUM_TC];
691 u32 rqtn;
692 u32 tirn[MLX5E_NUM_TT];
693
694 struct mlx5e_flow_table ft;
695 struct mlx5e_eth_addr_db eth_addr;
696 struct mlx5e_vlan_db vlan;
697
698 struct mlx5e_params params;
699 struct mlx5e_params_ethtool params_ethtool;
700 union mlx5_core_pci_diagnostics params_pci;
701 union mlx5_core_general_diagnostics params_general;
702 struct mtx async_events_mtx; /* sync hw events */
703 struct work_struct update_stats_work;
704 struct work_struct update_carrier_work;
705 struct work_struct set_rx_mode_work;
706 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock)
707
708 struct ifnet *ifp;
709 struct sysctl_ctx_list sysctl_ctx;
710 struct sysctl_oid *sysctl_ifnet;
711 struct sysctl_oid *sysctl_hw;
712 int sysctl_debug;
713 struct mlx5e_stats stats;
714 int counter_set_id;
715
716 eventhandler_tag vlan_detach;
717 eventhandler_tag vlan_attach;
718 struct ifmedia media;
719 int media_status_last;
720 int media_active_last;
721
722 struct callout watchdog;
723 };
724
725 #define MLX5E_NET_IP_ALIGN 2
726
727 struct mlx5e_tx_wqe {
728 struct mlx5_wqe_ctrl_seg ctrl;
729 struct mlx5_wqe_eth_seg eth;
730 };
731
732 struct mlx5e_rx_wqe {
733 struct mlx5_wqe_srq_next_seg next;
734 struct mlx5_wqe_data_seg data[];
735 };
736
737 /* the size of the structure above must be power of two */
738 CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe)));
739
740 struct mlx5e_eeprom {
741 int lock_bit;
742 int i2c_addr;
743 int page_num;
744 int device_addr;
745 int module_num;
746 int len;
747 int type;
748 int page_valid;
749 u32 *data;
750 };
751
752 enum mlx5e_link_mode {
753 MLX5E_1000BASE_CX_SGMII = 0,
754 MLX5E_1000BASE_KX = 1,
755 MLX5E_10GBASE_CX4 = 2,
756 MLX5E_10GBASE_KX4 = 3,
757 MLX5E_10GBASE_KR = 4,
758 MLX5E_20GBASE_KR2 = 5,
759 MLX5E_40GBASE_CR4 = 6,
760 MLX5E_40GBASE_KR4 = 7,
761 MLX5E_56GBASE_R4 = 8,
762 MLX5E_10GBASE_CR = 12,
763 MLX5E_10GBASE_SR = 13,
764 MLX5E_10GBASE_LR = 14,
765 MLX5E_40GBASE_SR4 = 15,
766 MLX5E_40GBASE_LR4 = 16,
767 MLX5E_100GBASE_CR4 = 20,
768 MLX5E_100GBASE_SR4 = 21,
769 MLX5E_100GBASE_KR4 = 22,
770 MLX5E_100GBASE_LR4 = 23,
771 MLX5E_100BASE_TX = 24,
772 MLX5E_100BASE_T = 25,
773 MLX5E_10GBASE_T = 26,
774 MLX5E_25GBASE_CR = 27,
775 MLX5E_25GBASE_KR = 28,
776 MLX5E_25GBASE_SR = 29,
777 MLX5E_50GBASE_CR2 = 30,
778 MLX5E_50GBASE_KR2 = 31,
779 MLX5E_LINK_MODES_NUMBER,
780 };
781
782 #define MLX5E_PROT_MASK(link_mode) (1 << (link_mode))
783 #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL)
784
785 int mlx5e_xmit(struct ifnet *, struct mbuf *);
786
787 int mlx5e_open_locked(struct ifnet *);
788 int mlx5e_close_locked(struct ifnet *);
789
790 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event);
791 void mlx5e_rx_cq_comp(struct mlx5_core_cq *);
792 void mlx5e_tx_cq_comp(struct mlx5_core_cq *);
793 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
794 void mlx5e_tx_que(void *context, int pending);
795
796 int mlx5e_open_flow_table(struct mlx5e_priv *priv);
797 void mlx5e_close_flow_table(struct mlx5e_priv *priv);
798 void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv);
799 void mlx5e_set_rx_mode_work(struct work_struct *work);
800
801 void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16);
802 void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16);
803 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
804 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
805 int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv);
806 void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv);
807
808 static inline void
mlx5e_tx_notify_hw(struct mlx5e_sq * sq,u32 * wqe,int bf_sz)809 mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz)
810 {
811 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
812
813 /* ensure wqe is visible to device before updating doorbell record */
814 wmb();
815
816 *sq->wq.db = cpu_to_be32(sq->pc);
817
818 /*
819 * Ensure the doorbell record is visible to device before ringing
820 * the doorbell:
821 */
822 wmb();
823
824 if (bf_sz) {
825 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz);
826
827 /* flush the write-combining mapped buffer */
828 wmb();
829
830 } else {
831 mlx5_write64(wqe, sq->uar.map + ofst,
832 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock));
833 }
834
835 sq->bf_offset ^= sq->bf_buf_size;
836 }
837
838 static inline void
mlx5e_cq_arm(struct mlx5e_cq * cq,spinlock_t * dblock)839 mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock)
840 {
841 struct mlx5_core_cq *mcq;
842
843 mcq = &cq->mcq;
844 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc);
845 }
846
847 extern const struct ethtool_ops mlx5e_ethtool_ops;
848 void mlx5e_create_ethtool(struct mlx5e_priv *);
849 void mlx5e_create_stats(struct sysctl_ctx_list *,
850 struct sysctl_oid_list *, const char *,
851 const char **, unsigned, u64 *);
852 void mlx5e_send_nop(struct mlx5e_sq *, u32);
853 void mlx5e_sq_cev_timeout(void *);
854 int mlx5e_refresh_channel_params(struct mlx5e_priv *);
855 int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *,
856 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix);
857 void mlx5e_close_cq(struct mlx5e_cq *);
858 void mlx5e_free_sq_db(struct mlx5e_sq *);
859 int mlx5e_alloc_sq_db(struct mlx5e_sq *);
860 int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num);
861 int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state);
862 void mlx5e_disable_sq(struct mlx5e_sq *);
863 void mlx5e_drain_sq(struct mlx5e_sq *);
864 u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev);
865
866 #endif /* _MLX5_EN_H_ */
867