1 /* CPU data header for m32r. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright 1996-2005 Free Software Foundation, Inc. 6 7 This file is part of the GNU Binutils and/or GDB, the GNU debugger. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2, or (at your option) 12 any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23 */ 24 25 #ifndef M32R_CPU_H 26 #define M32R_CPU_H 27 28 #define CGEN_ARCH m32r 29 30 /* Given symbol S, return m32r_cgen_<S>. */ 31 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) 32 #define CGEN_SYM(s) m32r##_cgen_##s 33 #else 34 #define CGEN_SYM(s) m32r/**/_cgen_/**/s 35 #endif 36 37 38 /* Selected cpu families. */ 39 #define HAVE_CPU_M32RBF 40 #define HAVE_CPU_M32RXF 41 #define HAVE_CPU_M32R2F 42 43 #define CGEN_INSN_LSB0_P 0 44 45 /* Minimum size of any insn (in bytes). */ 46 #define CGEN_MIN_INSN_SIZE 2 47 48 /* Maximum size of any insn (in bytes). */ 49 #define CGEN_MAX_INSN_SIZE 4 50 51 #define CGEN_INT_INSN_P 1 52 53 /* Maximum number of syntax elements in an instruction. */ 54 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 55 56 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 57 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 58 we can't hash on everything up to the space. */ 59 #define CGEN_MNEMONIC_OPERANDS 60 61 /* Maximum number of fields in an instruction. */ 62 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 63 64 /* Enums. */ 65 66 /* Enum declaration for insn format enums. */ 67 typedef enum insn_op1 { 68 OP1_0, OP1_1, OP1_2, OP1_3 69 , OP1_4, OP1_5, OP1_6, OP1_7 70 , OP1_8, OP1_9, OP1_10, OP1_11 71 , OP1_12, OP1_13, OP1_14, OP1_15 72 } INSN_OP1; 73 74 /* Enum declaration for op2 enums. */ 75 typedef enum insn_op2 { 76 OP2_0, OP2_1, OP2_2, OP2_3 77 , OP2_4, OP2_5, OP2_6, OP2_7 78 , OP2_8, OP2_9, OP2_10, OP2_11 79 , OP2_12, OP2_13, OP2_14, OP2_15 80 } INSN_OP2; 81 82 /* Enum declaration for . */ 83 typedef enum gr_names { 84 H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 85 , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4 86 , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8 87 , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12 88 , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 89 } GR_NAMES; 90 91 /* Enum declaration for . */ 92 typedef enum cr_names { 93 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 94 , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5 95 , H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3 96 , H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7 97 , H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11 98 , H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15 99 } CR_NAMES; 100 101 /* Attributes. */ 102 103 /* Enum declaration for machine type selection. */ 104 typedef enum mach_attr { 105 MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2 106 , MACH_MAX 107 } MACH_ATTR; 108 109 /* Enum declaration for instruction set selection. */ 110 typedef enum isa_attr { 111 ISA_M32R, ISA_MAX 112 } ISA_ATTR; 113 114 /* Enum declaration for parallel execution pipeline selection. */ 115 typedef enum pipe_attr { 116 PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS 117 , PIPE_O_OS 118 } PIPE_ATTR; 119 120 /* Number of architecture variants. */ 121 #define MAX_ISAS 1 122 #define MAX_MACHS ((int) MACH_MAX) 123 124 /* Ifield support. */ 125 126 /* Ifield attribute indices. */ 127 128 /* Enum declaration for cgen_ifld attrs. */ 129 typedef enum cgen_ifld_attr { 130 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 131 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS 132 , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS 133 } CGEN_IFLD_ATTR; 134 135 /* Number of non-boolean elements in cgen_ifld_attr. */ 136 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 137 138 /* Enum declaration for m32r ifield types. */ 139 typedef enum ifield_type { 140 M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2 141 , M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8 142 , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3, M32R_F_UIMM4 143 , M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16, M32R_F_UIMM24 144 , M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16, M32R_F_DISP24 145 , M32R_F_OP23, M32R_F_OP3, M32R_F_ACC, M32R_F_ACCS 146 , M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4, M32R_F_BIT14 147 , M32R_F_IMM1, M32R_F_MAX 148 } IFIELD_TYPE; 149 150 #define MAX_IFLD ((int) M32R_F_MAX) 151 152 /* Hardware attribute indices. */ 153 154 /* Enum declaration for cgen_hw attrs. */ 155 typedef enum cgen_hw_attr { 156 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 157 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS 158 } CGEN_HW_ATTR; 159 160 /* Number of non-boolean elements in cgen_hw_attr. */ 161 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 162 163 /* Enum declaration for m32r hardware types. */ 164 typedef enum cgen_hw_type { 165 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 166 , HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16 167 , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM 168 , HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW 169 , HW_H_BBPSW, HW_H_LOCK, HW_MAX 170 } CGEN_HW_TYPE; 171 172 #define MAX_HW ((int) HW_MAX) 173 174 /* Operand attribute indices. */ 175 176 /* Enum declaration for cgen_operand attrs. */ 177 typedef enum cgen_operand_attr { 178 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 179 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 180 , CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31 181 , CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS 182 } CGEN_OPERAND_ATTR; 183 184 /* Number of non-boolean elements in cgen_operand_attr. */ 185 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 186 187 /* Enum declaration for m32r operand types. */ 188 typedef enum cgen_operand_type { 189 M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1 190 , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8 191 , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5 192 , M32R_OPERAND_UIMM8, M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD 193 , M32R_OPERAND_ACCS, M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16 194 , M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8 195 , M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM 196 , M32R_OPERAND_MAX 197 } CGEN_OPERAND_TYPE; 198 199 /* Number of operands types. */ 200 #define MAX_OPERANDS 28 201 202 /* Maximum number of operands referenced by any insn. */ 203 #define MAX_OPERAND_INSTANCES 11 204 205 /* Insn attribute indices. */ 206 207 /* Enum declaration for cgen_insn attrs. */ 208 typedef enum cgen_insn_attr { 209 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 210 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 211 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL 212 , CGEN_INSN_SPECIAL_M32R, CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 213 , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS 214 } CGEN_INSN_ATTR; 215 216 /* Number of non-boolean elements in cgen_insn_attr. */ 217 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 218 219 /* cgen.h uses things we just defined. */ 220 #include "opcode/cgen.h" 221 222 extern const struct cgen_ifld m32r_cgen_ifld_table[]; 223 224 /* Attributes. */ 225 extern const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[]; 226 extern const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[]; 227 extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[]; 228 extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[]; 229 230 /* Hardware decls. */ 231 232 extern CGEN_KEYWORD m32r_cgen_opval_gr_names; 233 extern CGEN_KEYWORD m32r_cgen_opval_cr_names; 234 extern CGEN_KEYWORD m32r_cgen_opval_h_accums; 235 236 extern const CGEN_HW_ENTRY m32r_cgen_hw_table[]; 237 238 239 240 #endif /* M32R_CPU_H */ 241