1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Please try to maintain the following order within this file unless it makes
24 * sense to do otherwise. From top to bottom:
25 * 1. typedefs
26 * 2. #defines, and macros
27 * 3. structure definitions
28 * 4. function prototypes
29 *
30 * Within each section, please try to order by generation in ascending order,
31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
32 */
33
34 #ifndef __I915_GEM_GTT_H__
35 #define __I915_GEM_GTT_H__
36
37 #include <linux/io-mapping.h>
38 #include <linux/mm.h>
39 #include <linux/pagevec.h>
40
41 #include "i915_gem_timeline.h"
42 #include "i915_gem_request.h"
43 #include "i915_selftest.h"
44
45 #define I915_GTT_PAGE_SIZE_4K BIT(12)
46 #define I915_GTT_PAGE_SIZE_64K BIT(16)
47 #define I915_GTT_PAGE_SIZE_2M BIT(21)
48
49 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
50 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
51
52 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
53
54 #define I915_FENCE_REG_NONE -1
55 #define I915_MAX_NUM_FENCES 32
56 /* 32 fences + sign bit for FENCE_REG_NONE */
57 #define I915_MAX_NUM_FENCE_BITS 6
58
59 struct drm_i915_file_private;
60 struct drm_i915_fence_reg;
61
62 typedef u32 gen6_pte_t;
63 typedef u64 gen8_pte_t;
64 typedef u64 gen8_pde_t;
65 typedef u64 gen8_ppgtt_pdpe_t;
66 typedef u64 gen8_ppgtt_pml4e_t;
67
68 #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT)
69
70 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
71 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
72 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
73 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
74 #define GEN6_PTE_CACHE_LLC (2 << 1)
75 #define GEN6_PTE_UNCACHED (1 << 1)
76 #define GEN6_PTE_VALID (1 << 0)
77
78 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len)))
79 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
80 #define I915_PDES 512
81 #define I915_PDE_MASK (I915_PDES - 1)
82 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
83
84 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
85 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
86 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
87 #define GEN6_PDE_SHIFT 22
88 #define GEN6_PDE_VALID (1 << 0)
89
90 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
91
92 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
93 #define BYT_PTE_WRITEABLE (1 << 1)
94
95 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits
96 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
97 */
98 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
99 (((bits) & 0x8) << (11 - 3)))
100 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
101 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
102 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
103 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
104 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
105 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
106 #define HSW_PTE_UNCACHED (0)
107 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
108 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
109
110 /* GEN8 32b style address is defined as a 3 level page table:
111 * 31:30 | 29:21 | 20:12 | 11:0
112 * PDPE | PDE | PTE | offset
113 * The difference as compared to normal x86 3 level page table is the PDPEs are
114 * programmed via register.
115 */
116 #define GEN8_3LVL_PDPES 4
117 #define GEN8_PDE_SHIFT 21
118 #define GEN8_PDE_MASK 0x1ff
119 #define GEN8_PTE_SHIFT 12
120 #define GEN8_PTE_MASK 0x1ff
121 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t))
122
123 /* GEN8 48b style address is defined as a 4 level page table:
124 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0
125 * PML4E | PDPE | PDE | PTE | offset
126 */
127 #define GEN8_PML4ES_PER_PML4 512
128 #define GEN8_PML4E_SHIFT 39
129 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1)
130 #define GEN8_PDPE_SHIFT 30
131 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page
132 * tables */
133 #define GEN8_PDPE_MASK 0x1ff
134
135 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD)
136 #define PPAT_CACHED_PDE 0 /* WB LLC */
137 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */
138 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */
139
140 #define CHV_PPAT_SNOOP (1<<6)
141 #define GEN8_PPAT_AGE(x) ((x)<<4)
142 #define GEN8_PPAT_LLCeLLC (3<<2)
143 #define GEN8_PPAT_LLCELLC (2<<2)
144 #define GEN8_PPAT_LLC (1<<2)
145 #define GEN8_PPAT_WB (3<<0)
146 #define GEN8_PPAT_WT (2<<0)
147 #define GEN8_PPAT_WC (1<<0)
148 #define GEN8_PPAT_UC (0<<0)
149 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
150 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
151
152 #define GEN8_PPAT_GET_CA(x) ((x) & 3)
153 #define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2))
154 #define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4))
155 #define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6))
156
157 #define GEN8_PDE_IPS_64K BIT(11)
158 #define GEN8_PDE_PS_2M BIT(7)
159
160 struct sg_table;
161
162 struct intel_rotation_info {
163 struct intel_rotation_plane_info {
164 /* tiles */
165 unsigned int width, height, stride, offset;
166 } plane[2];
167 } __packed;
168
assert_intel_rotation_info_is_packed(void)169 static inline void assert_intel_rotation_info_is_packed(void)
170 {
171 BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int));
172 }
173
174 struct intel_partial_info {
175 u64 offset;
176 unsigned int size;
177 } __packed;
178
assert_intel_partial_info_is_packed(void)179 static inline void assert_intel_partial_info_is_packed(void)
180 {
181 BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int));
182 }
183
184 enum i915_ggtt_view_type {
185 I915_GGTT_VIEW_NORMAL = 0,
186 I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
187 I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
188 };
189
assert_i915_ggtt_view_type_is_unique(void)190 static inline void assert_i915_ggtt_view_type_is_unique(void)
191 {
192 /* As we encode the size of each branch inside the union into its type,
193 * we have to be careful that each branch has a unique size.
194 */
195 switch ((enum i915_ggtt_view_type)0) {
196 case I915_GGTT_VIEW_NORMAL:
197 case I915_GGTT_VIEW_PARTIAL:
198 case I915_GGTT_VIEW_ROTATED:
199 /* gcc complains if these are identical cases */
200 break;
201 }
202 }
203
204 struct i915_ggtt_view {
205 enum i915_ggtt_view_type type;
206 union {
207 /* Members need to contain no holes/padding */
208 struct intel_partial_info partial;
209 struct intel_rotation_info rotated;
210 };
211 };
212
213 enum i915_cache_level;
214
215 struct i915_vma;
216
217 struct i915_page_dma {
218 struct page *page;
219 int order;
220 union {
221 dma_addr_t daddr;
222
223 /* For gen6/gen7 only. This is the offset in the GGTT
224 * where the page directory entries for PPGTT begin
225 */
226 u32 ggtt_offset;
227 };
228 };
229
230 #define px_base(px) (&(px)->base)
231 #define px_page(px) (px_base(px)->page)
232 #define px_dma(px) (px_base(px)->daddr)
233
234 struct i915_page_table {
235 struct i915_page_dma base;
236 unsigned int used_ptes;
237 };
238
239 struct i915_page_directory {
240 struct i915_page_dma base;
241
242 struct i915_page_table *page_table[I915_PDES]; /* PDEs */
243 unsigned int used_pdes;
244 };
245
246 struct i915_page_directory_pointer {
247 struct i915_page_dma base;
248 struct i915_page_directory **page_directory;
249 unsigned int used_pdpes;
250 };
251
252 struct i915_pml4 {
253 struct i915_page_dma base;
254 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4];
255 };
256
257 struct i915_address_space {
258 struct drm_mm mm;
259 struct i915_gem_timeline timeline;
260 struct drm_i915_private *i915;
261 struct device *dma;
262 /* Every address space belongs to a struct file - except for the global
263 * GTT that is owned by the driver (and so @file is set to NULL). In
264 * principle, no information should leak from one context to another
265 * (or between files/processes etc) unless explicitly shared by the
266 * owner. Tracking the owner is important in order to free up per-file
267 * objects along with the file, to aide resource tracking, and to
268 * assign blame.
269 */
270 struct drm_i915_file_private *file;
271 struct list_head global_link;
272 u64 total; /* size addr space maps (ex. 2GB for ggtt) */
273 u64 reserved; /* size addr space reserved */
274
275 bool closed;
276
277 struct i915_page_dma scratch_page;
278 struct i915_page_table *scratch_pt;
279 struct i915_page_directory *scratch_pd;
280 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */
281
282 /**
283 * List of objects currently involved in rendering.
284 *
285 * Includes buffers having the contents of their GPU caches
286 * flushed, not necessarily primitives. last_read_req
287 * represents when the rendering involved will be completed.
288 *
289 * A reference is held on the buffer while on this list.
290 */
291 struct list_head active_list;
292
293 /**
294 * LRU list of objects which are not in the ringbuffer and
295 * are ready to unbind, but are still in the GTT.
296 *
297 * last_read_req is NULL while an object is in this list.
298 *
299 * A reference is not held on the buffer while on this list,
300 * as merely being GTT-bound shouldn't prevent its being
301 * freed, and we'll pull it off the list in the free path.
302 */
303 struct list_head inactive_list;
304
305 /**
306 * List of vma that have been unbound.
307 *
308 * A reference is not held on the buffer while on this list.
309 */
310 struct list_head unbound_list;
311
312 struct pagevec free_pages;
313 bool pt_kmap_wc;
314
315 /* FIXME: Need a more generic return type */
316 gen6_pte_t (*pte_encode)(dma_addr_t addr,
317 enum i915_cache_level level,
318 u32 flags); /* Create a valid PTE */
319 /* flags for pte_encode */
320 #define PTE_READ_ONLY (1<<0)
321 int (*allocate_va_range)(struct i915_address_space *vm,
322 u64 start, u64 length);
323 void (*clear_range)(struct i915_address_space *vm,
324 u64 start, u64 length);
325 void (*insert_page)(struct i915_address_space *vm,
326 dma_addr_t addr,
327 u64 offset,
328 enum i915_cache_level cache_level,
329 u32 flags);
330 void (*insert_entries)(struct i915_address_space *vm,
331 struct i915_vma *vma,
332 enum i915_cache_level cache_level,
333 u32 flags);
334 void (*cleanup)(struct i915_address_space *vm);
335 /** Unmap an object from an address space. This usually consists of
336 * setting the valid PTE entries to a reserved scratch page. */
337 void (*unbind_vma)(struct i915_vma *vma);
338 /* Map an object into an address space with the given cache flags. */
339 int (*bind_vma)(struct i915_vma *vma,
340 enum i915_cache_level cache_level,
341 u32 flags);
342 int (*set_pages)(struct i915_vma *vma);
343 void (*clear_pages)(struct i915_vma *vma);
344
345 I915_SELFTEST_DECLARE(struct fault_attr fault_attr);
346 };
347
348 #define i915_is_ggtt(V) (!(V)->file)
349
350 static inline bool
i915_vm_is_48bit(const struct i915_address_space * vm)351 i915_vm_is_48bit(const struct i915_address_space *vm)
352 {
353 return (vm->total - 1) >> 32;
354 }
355
356 static inline bool
i915_vm_has_scratch_64K(struct i915_address_space * vm)357 i915_vm_has_scratch_64K(struct i915_address_space *vm)
358 {
359 return vm->scratch_page.order == get_order(I915_GTT_PAGE_SIZE_64K);
360 }
361
362 /* The Graphics Translation Table is the way in which GEN hardware translates a
363 * Graphics Virtual Address into a Physical Address. In addition to the normal
364 * collateral associated with any va->pa translations GEN hardware also has a
365 * portion of the GTT which can be mapped by the CPU and remain both coherent
366 * and correct (in cases like swizzling). That region is referred to as GMADR in
367 * the spec.
368 */
369 struct i915_ggtt {
370 struct i915_address_space base;
371 struct io_mapping mappable; /* Mapping to our CPU mappable region */
372
373 phys_addr_t mappable_base; /* PA of our GMADR */
374 u64 mappable_end; /* End offset that we can CPU map */
375
376 /* Stolen memory is segmented in hardware with different portions
377 * offlimits to certain functions.
378 *
379 * The drm_mm is initialised to the total accessible range, as found
380 * from the PCI config. On Broadwell+, this is further restricted to
381 * avoid the first page! The upper end of stolen memory is reserved for
382 * hardware functions and similarly removed from the accessible range.
383 */
384 u32 stolen_size; /* Total size of stolen memory */
385 u32 stolen_usable_size; /* Total size minus reserved ranges */
386 u32 stolen_reserved_base;
387 u32 stolen_reserved_size;
388
389 /** "Graphics Stolen Memory" holds the global PTEs */
390 void __iomem *gsm;
391 void (*invalidate)(struct drm_i915_private *dev_priv);
392
393 bool do_idle_maps;
394
395 int mtrr;
396
397 struct drm_mm_node error_capture;
398 };
399
400 struct i915_hw_ppgtt {
401 struct i915_address_space base;
402 struct kref ref;
403 struct drm_mm_node node;
404 unsigned long pd_dirty_rings;
405 union {
406 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */
407 struct i915_page_directory_pointer pdp; /* GEN8+ */
408 struct i915_page_directory pd; /* GEN6-7 */
409 };
410
411 gen6_pte_t __iomem *pd_addr;
412
413 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
414 struct drm_i915_gem_request *req);
415 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
416 };
417
418 /*
419 * gen6_for_each_pde() iterates over every pde from start until start+length.
420 * If start and start+length are not perfectly divisible, the macro will round
421 * down and up as needed. Start=0 and length=2G effectively iterates over
422 * every PDE in the system. The macro modifies ALL its parameters except 'pd',
423 * so each of the other parameters should preferably be a simple variable, or
424 * at most an lvalue with no side-effects!
425 */
426 #define gen6_for_each_pde(pt, pd, start, length, iter) \
427 for (iter = gen6_pde_index(start); \
428 length > 0 && iter < I915_PDES && \
429 (pt = (pd)->page_table[iter], true); \
430 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \
431 temp = min(temp - start, length); \
432 start += temp, length -= temp; }), ++iter)
433
434 #define gen6_for_all_pdes(pt, pd, iter) \
435 for (iter = 0; \
436 iter < I915_PDES && \
437 (pt = (pd)->page_table[iter], true); \
438 ++iter)
439
i915_pte_index(u64 address,unsigned int pde_shift)440 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)
441 {
442 const u32 mask = NUM_PTE(pde_shift) - 1;
443
444 return (address >> PAGE_SHIFT) & mask;
445 }
446
447 /* Helper to counts the number of PTEs within the given length. This count
448 * does not cross a page table boundary, so the max value would be
449 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
450 */
i915_pte_count(u64 addr,u64 length,unsigned int pde_shift)451 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)
452 {
453 const u64 mask = ~((1ULL << pde_shift) - 1);
454 u64 end;
455
456 WARN_ON(length == 0);
457 WARN_ON(offset_in_page(addr|length));
458
459 end = addr + length;
460
461 if ((addr & mask) != (end & mask))
462 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
463
464 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
465 }
466
i915_pde_index(u64 addr,u32 shift)467 static inline u32 i915_pde_index(u64 addr, u32 shift)
468 {
469 return (addr >> shift) & I915_PDE_MASK;
470 }
471
gen6_pte_index(u32 addr)472 static inline u32 gen6_pte_index(u32 addr)
473 {
474 return i915_pte_index(addr, GEN6_PDE_SHIFT);
475 }
476
gen6_pte_count(u32 addr,u32 length)477 static inline u32 gen6_pte_count(u32 addr, u32 length)
478 {
479 return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
480 }
481
gen6_pde_index(u32 addr)482 static inline u32 gen6_pde_index(u32 addr)
483 {
484 return i915_pde_index(addr, GEN6_PDE_SHIFT);
485 }
486
487 static inline unsigned int
i915_pdpes_per_pdp(const struct i915_address_space * vm)488 i915_pdpes_per_pdp(const struct i915_address_space *vm)
489 {
490 if (i915_vm_is_48bit(vm))
491 return GEN8_PML4ES_PER_PML4;
492
493 return GEN8_3LVL_PDPES;
494 }
495
496 /* Equivalent to the gen6 version, For each pde iterates over every pde
497 * between from start until start + length. On gen8+ it simply iterates
498 * over every page directory entry in a page directory.
499 */
500 #define gen8_for_each_pde(pt, pd, start, length, iter) \
501 for (iter = gen8_pde_index(start); \
502 length > 0 && iter < I915_PDES && \
503 (pt = (pd)->page_table[iter], true); \
504 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \
505 temp = min(temp - start, length); \
506 start += temp, length -= temp; }), ++iter)
507
508 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \
509 for (iter = gen8_pdpe_index(start); \
510 length > 0 && iter < i915_pdpes_per_pdp(vm) && \
511 (pd = (pdp)->page_directory[iter], true); \
512 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \
513 temp = min(temp - start, length); \
514 start += temp, length -= temp; }), ++iter)
515
516 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \
517 for (iter = gen8_pml4e_index(start); \
518 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \
519 (pdp = (pml4)->pdps[iter], true); \
520 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \
521 temp = min(temp - start, length); \
522 start += temp, length -= temp; }), ++iter)
523
gen8_pte_index(u64 address)524 static inline u32 gen8_pte_index(u64 address)
525 {
526 return i915_pte_index(address, GEN8_PDE_SHIFT);
527 }
528
gen8_pde_index(u64 address)529 static inline u32 gen8_pde_index(u64 address)
530 {
531 return i915_pde_index(address, GEN8_PDE_SHIFT);
532 }
533
gen8_pdpe_index(u64 address)534 static inline u32 gen8_pdpe_index(u64 address)
535 {
536 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
537 }
538
gen8_pml4e_index(u64 address)539 static inline u32 gen8_pml4e_index(u64 address)
540 {
541 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK;
542 }
543
gen8_pte_count(u64 address,u64 length)544 static inline u64 gen8_pte_count(u64 address, u64 length)
545 {
546 return i915_pte_count(address, length, GEN8_PDE_SHIFT);
547 }
548
549 static inline dma_addr_t
i915_page_dir_dma_addr(const struct i915_hw_ppgtt * ppgtt,const unsigned n)550 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
551 {
552 return px_dma(ppgtt->pdp.page_directory[n]);
553 }
554
555 static inline struct i915_ggtt *
i915_vm_to_ggtt(struct i915_address_space * vm)556 i915_vm_to_ggtt(struct i915_address_space *vm)
557 {
558 GEM_BUG_ON(!i915_is_ggtt(vm));
559 return container_of(vm, struct i915_ggtt, base);
560 }
561
562 #define INTEL_MAX_PPAT_ENTRIES 8
563 #define INTEL_PPAT_PERFECT_MATCH (~0U)
564
565 struct intel_ppat;
566
567 struct intel_ppat_entry {
568 struct intel_ppat *ppat;
569 struct kref ref;
570 u8 value;
571 };
572
573 struct intel_ppat {
574 struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES];
575 DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES);
576 DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES);
577 unsigned int max_entries;
578 u8 clear_value;
579 /*
580 * Return a score to show how two PPAT values match,
581 * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match
582 */
583 unsigned int (*match)(u8 src, u8 dst);
584 void (*update_hw)(struct drm_i915_private *i915);
585
586 struct drm_i915_private *i915;
587 };
588
589 const struct intel_ppat_entry *
590 intel_ppat_get(struct drm_i915_private *i915, u8 value);
591 void intel_ppat_put(const struct intel_ppat_entry *entry);
592
593 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915);
594 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915);
595
596 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
597 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
598 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
599 void i915_ggtt_enable_guc(struct drm_i915_private *i915);
600 void i915_ggtt_disable_guc(struct drm_i915_private *i915);
601 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv);
602 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv);
603
604 int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv);
605 void i915_ppgtt_release(struct kref *kref);
606 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv,
607 struct drm_i915_file_private *fpriv,
608 const char *name);
609 void i915_ppgtt_close(struct i915_address_space *vm);
i915_ppgtt_get(struct i915_hw_ppgtt * ppgtt)610 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
611 {
612 if (ppgtt)
613 kref_get(&ppgtt->ref);
614 }
i915_ppgtt_put(struct i915_hw_ppgtt * ppgtt)615 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
616 {
617 if (ppgtt)
618 kref_put(&ppgtt->ref, i915_ppgtt_release);
619 }
620
621 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
622 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
623 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
624
625 int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
626 struct sg_table *pages);
627 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
628 struct sg_table *pages);
629
630 int i915_gem_gtt_reserve(struct i915_address_space *vm,
631 struct drm_mm_node *node,
632 u64 size, u64 offset, unsigned long color,
633 unsigned int flags);
634
635 int i915_gem_gtt_insert(struct i915_address_space *vm,
636 struct drm_mm_node *node,
637 u64 size, u64 alignment, unsigned long color,
638 u64 start, u64 end, unsigned int flags);
639
640 /* Flags used by pin/bind&friends. */
641 #define PIN_NONBLOCK BIT(0)
642 #define PIN_MAPPABLE BIT(1)
643 #define PIN_ZONE_4G BIT(2)
644 #define PIN_NONFAULT BIT(3)
645 #define PIN_NOEVICT BIT(4)
646
647 #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */
648 #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */
649 #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */
650 #define PIN_UPDATE BIT(8)
651
652 #define PIN_HIGH BIT(9)
653 #define PIN_OFFSET_BIAS BIT(10)
654 #define PIN_OFFSET_FIXED BIT(11)
655 #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE)
656
657 #endif
658