1 /*- 2 * Copyright (c) 2001 Jake Burkholder. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _MACHINE_INTR_MACHDEP_H_ 30 #define _MACHINE_INTR_MACHDEP_H_ 31 32 #define IRSR_BUSY (1 << 5) 33 34 #define PIL_MAX (1 << 4) 35 #define IV_MAX (1 << 11) 36 37 #define IR_FREE (PIL_MAX * 2) 38 39 #define IH_SHIFT PTR_SHIFT 40 #define IQE_SHIFT 5 41 #define IV_SHIFT 6 42 43 #define PIL_LOW 1 /* stray interrupts */ 44 #define PIL_PREEMPT 2 /* preempt idle thread CPU IPI */ 45 #define PIL_ITHREAD 3 /* interrupts that use ithreads */ 46 #define PIL_RENDEZVOUS 4 /* SMP rendezvous IPI */ 47 #define PIL_AST 5 /* asynchronous trap IPI */ 48 #define PIL_HARDCLOCK 6 /* hardclock broadcast */ 49 #define PIL_FILTER 11 /* filter interrupts */ 50 #define PIL_BRIDGE 12 /* bridge interrupts */ 51 #define PIL_STOP 13 /* stop CPU IPI */ 52 #define PIL_TICK 14 /* tick interrupts */ 53 54 #ifndef LOCORE 55 56 #define INTR_BRIDGE INTR_MD1 57 58 struct trapframe; 59 60 typedef void ih_func_t(struct trapframe *); 61 typedef void iv_func_t(void *); 62 63 struct intr_request { 64 struct intr_request *ir_next; 65 iv_func_t *ir_func; 66 void *ir_arg; 67 u_int ir_vec; 68 u_int ir_pri; 69 }; 70 71 struct intr_controller { 72 void (*ic_enable)(void *); 73 void (*ic_disable)(void *); 74 void (*ic_assign)(void *); 75 void (*ic_clear)(void *); 76 }; 77 78 struct intr_vector { 79 iv_func_t *iv_func; 80 void *iv_arg; 81 const struct intr_controller *iv_ic; 82 void *iv_icarg; 83 struct intr_event *iv_event; 84 u_int iv_pri; 85 u_int iv_vec; 86 u_int iv_mid; 87 u_int iv_refcnt; 88 u_int iv_pad[2]; 89 }; 90 91 extern ih_func_t *intr_handlers[]; 92 extern struct intr_vector intr_vectors[]; 93 94 #ifdef SMP 95 void intr_add_cpu(u_int cpu); 96 #endif 97 int intr_bind(int vec, u_char cpu); 98 int intr_describe(int vec, void *ih, const char *descr); 99 void intr_setup(int level, ih_func_t *ihf, int pri, iv_func_t *ivf, 100 void *iva); 101 void intr_init1(void); 102 void intr_init2(void); 103 int intr_controller_register(int vec, const struct intr_controller *ic, 104 void *icarg); 105 int inthand_add(const char *name, int vec, int (*filt)(void *), 106 void (*handler)(void *), void *arg, int flags, void **cookiep); 107 int inthand_remove(int vec, void *cookie); 108 109 ih_func_t intr_fast; 110 111 #endif /* !LOCORE */ 112 113 #endif /* !_MACHINE_INTR_MACHDEP_H_ */ 114