1 /* $NetBSD: pte_motorola.h,v 1.10 2024/01/01 22:47:58 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1986, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: Utah $Hdr: pte.h 1.13 92/01/20$ 37 * 38 * @(#)pte.h 8.1 (Berkeley) 6/10/93 39 */ 40 41 #ifndef _MACHINE_PTE_H_ 42 #define _MACHINE_PTE_H_ 43 44 #include <m68k/mmu_51.h> 45 #include <m68k/mmu_40.h> 46 47 /* 48 * m68k motorola MMU segment/page table entries 49 */ 50 51 typedef u_int st_entry_t; /* segment table entry */ 52 typedef u_int pt_entry_t; /* page table entry */ 53 54 #define PT_ENTRY_NULL NULL 55 #define ST_ENTRY_NULL NULL 56 57 #define PG_SHIFT PGSHIFT 58 59 /* 60 * "Segment" Table Entry bits, defined in terms of the 68851 bits 61 * (compatible 68040 bits noted in comments). 62 */ 63 #define SG_V DT51_SHORT /* == UTE40_RESIDENT */ 64 #define SG_NV DT51_INVALID /* == UTE40_INVALID */ 65 #define SG_RO DTE51_WP /* == UTE40_W */ 66 #define SG_RW 0x00000000 67 #define SG_PROT DTE51_WP 68 #define SG_U DTE51_U /* == UTE40_U */ 69 #define SG_FRAME ((~0U) << PG_SHIFT) 70 #define SG_ISHIFT ((PG_SHIFT << 1) - 2) /* 24 or 22 */ 71 #define SG_IMASK ((~0U) << SG_ISHIFT) 72 #define SG_PSHIFT PG_SHIFT 73 #define SG_PMASK (((~0U) << SG_PSHIFT) & ~SG_IMASK) 74 75 /* 68040 additions */ 76 #define SG4_MASK1 0xfe000000U 77 #define SG4_SHIFT1 25 78 #define SG4_MASK2 0x01fc0000U 79 #define SG4_SHIFT2 18 80 #define SG4_MASK3 (((~0U) << PG_SHIFT) & ~(SG4_MASK1 | SG4_MASK2)) 81 #define SG4_SHIFT3 PG_SHIFT 82 #define SG4_ADDR1 0xfffffe00 83 #define SG4_ADDR2 ((~0U) << (20 - PG_SHIFT)) 84 #define SG4_LEV1SIZE 128 85 #define SG4_LEV2SIZE 128 86 #define SG4_LEV3SIZE (1U << (SG4_SHIFT2 - PG_SHIFT)) /* 64 or 32 */ 87 88 /* 89 * Page Table Entry bits, defined in terms of the 68851 bits 90 * (compatible 68040 bits noted in comments). 91 */ 92 #define PG_V DT51_PAGE /* == PTE40_RESIDENT */ 93 #define PG_NV DT51_INVALID /* == PTE40_INVALID */ 94 #define PG_RO PTE51_WP /* == PTE40_W */ 95 #define PG_RW 0x00000000 96 #define PG_PROT PG_RO 97 #define PG_U PTE51_U /* == PTE40_U */ 98 #define PG_M PTE51_M /* == PTE40_M */ 99 #define PG_CI PTE51_CI 100 #define PG_W __BIT(8) /* 851 unused bit XXX040 PTE40_U0 */ 101 #define PG_FRAME ((~0U) << PG_SHIFT) 102 #define PG_PFNUM(x) (((uintptr_t)(x) & PG_FRAME) >> PG_SHIFT) 103 104 /* 68040 additions */ 105 #define PG_CMASK PTE40_CM /* cache mode mask */ 106 #define PG_CWT PTE40_CM_WT /* writethrough caching */ 107 #define PG_CCB PTE40_CM_CB /* copyback caching */ 108 #define PG_CIS PTE40_CM_NC_SER /* cache inhibited serialized */ 109 #define PG_CIN PTE40_CM_NC /* cache inhibited nonserialized */ 110 #define PG_SO PTE40_S /* supervisor only */ 111 112 #define M68K_STSIZE (MAXUL2SIZE * SG4_LEV2SIZE * sizeof(st_entry_t)) 113 /* user process segment table size */ 114 #define M68K_MAX_PTSIZE (1U << (32 - PG_SHIFT + 2)) /* max size of UPT */ 115 #define M68K_MAX_KPTSIZE (M68K_MAX_PTSIZE >> 2) /* max memory to allocate to KPT */ 116 #define M68K_PTBASE 0x10000000 /* UPT map base address */ 117 #define M68K_PTMAXSIZE 0x70000000 /* UPT map maximum size */ 118 119 /* 120 * Kernel virtual address to page table entry and to physical address. 121 */ 122 123 #ifdef cesfic 124 #define kvtopte(va) \ 125 (&Sysmap[((unsigned)(va)) >> PGSHIFT]) 126 #else 127 #define kvtopte(va) \ 128 (&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT]) 129 #endif 130 131 #endif /* !_MACHINE_PTE_H_ */ 132