1 /* 2 * Copyright (c) 2019-2020 François Tigeot <ftigeot@wolfpond.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef UAPI_LINUX_PCIREGS_H 28 #define UAPI_LINUX_PCIREGS_H 29 30 #define PCI_EXP_RTCAP 30 31 32 #define PCI_EXP_FLAGS 2 33 #define PCI_EXP_FLAGS_VERS 0x000f 34 #define PCI_EXP_FLAGS_TYPE 0x00f0 35 36 #define PCI_EXP_DEVCAP 4 37 38 #define PCI_EXP_LNKCAP 12 39 40 #define PCI_EXP_DEVCTL 8 41 #define PCI_EXP_DEVCTL2 40 42 43 #define PCI_EXP_LNKSTA 18 44 #define PCI_EXP_LNKSTA2 50 45 46 #define PCI_EXP_SLTCAP 20 47 48 #define PCI_CAP_ID_EXP 0x10 49 50 #define PCI_EXP_TYPE_ENDPOINT 0x0 51 #define PCI_EXP_TYPE_LEG_END 0x1 52 #define PCI_EXP_TYPE_ROOT_PORT 0x4 53 #define PCI_EXP_TYPE_DOWNSTREAM 0x6 54 #define PCI_EXP_TYPE_RC_EC 0xa 55 56 #define PCI_EXP_SLTCTL 24 57 58 #define PCI_EXP_SLTSTA 26 59 60 #define PCI_EXP_FLAGS_SLOT 0x0100 61 62 #define PCI_EXP_RTCTL 28 63 64 #define PCI_EXP_RTSTA 32 65 66 #define PCI_EXP_DEVCAP2 36 67 68 #define PCI_EXP_LNKCAP2 44 69 70 #define PCI_EXP_LNKCAP_MLW 0x000003f0 71 72 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 73 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 74 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 75 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 76 77 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 78 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 79 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 80 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 81 82 #endif /* UAPI_LINUX_PCIREGS_H */ 83