1 /** $MirOS: src/sys/dev/pci/if_txvar.h,v 1.2 2005/03/06 21:27:48 tg Exp $ */ 2 /* $OpenBSD: if_txvar.h,v 1.12 2002/03/14 03:16:06 millert Exp $ */ 3 /* $FreeBSD: src/sys/pci/if_txvar.h,v 1.8 2001/02/07 20:11:02 semenu Exp $ */ 4 5 /*- 6 * Copyright (c) 1997 Semen Ustimenko 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Configuration 33 */ 34 /*#define EPIC_DEBUG 1*/ 35 /*#define EPIC_USEIOSPACE 1*/ 36 #define EARLY_RX 1 37 38 #define TX_RING_SIZE 16 /* Leave this a power of 2 */ 39 #define RX_RING_SIZE 16 /* And this too, to do not */ 40 /* confuse RX(TX)_RING_MASK */ 41 #define TX_RING_MASK (TX_RING_SIZE - 1) 42 #define RX_RING_MASK (RX_RING_SIZE - 1) 43 #define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN) 44 45 /* PCI aux configuration registers */ 46 #if defined(__FreeBSD__) 47 #define PCIR_BASEIO (PCIR_MAPS + 0x0) /* Base IO Address */ 48 #define PCIR_BASEMEM (PCIR_MAPS + 0x4) /* Base Memory Address */ 49 #else /* __OpenBSD__ */ 50 #define PCI_BASEIO (PCI_MAPS + 0x0) /* Base IO Address */ 51 #define PCI_BASEMEM (PCI_MAPS + 0x4) /* Base Memory Address */ 52 #endif /* __FreeBSD__ */ 53 54 /* PCI identification */ 55 #define SMC_VENDORID 0x10B8 56 #define SMC_DEVICEID_83C170 0x0005 57 58 /* EPIC's registers */ 59 #define COMMAND 0x0000 60 #define INTSTAT 0x0004 /* Interrupt status. See below */ 61 #define INTMASK 0x0008 /* Interrupt mask. See below */ 62 #define GENCTL 0x000C 63 #define NVCTL 0x0010 64 #define EECTL 0x0014 /* EEPROM control **/ 65 #define TEST1 0x001C /* XXXXX */ 66 #define CRCCNT 0x0020 /* CRC error counter */ 67 #define ALICNT 0x0024 /* FrameTooLang error counter */ 68 #define MPCNT 0x0028 /* MissedFrames error counters */ 69 #define MIICTL 0x0030 70 #define MIIDATA 0x0034 71 #define MIICFG 0x0038 72 #define IPG 0x003C 73 #define LAN0 0x0040 /* MAC address */ 74 #define LAN1 0x0044 /* MAC address */ 75 #define LAN2 0x0048 /* MAC address */ 76 #define ID_CHK 0x004C 77 #define MC0 0x0050 /* Multicast filter table */ 78 #define MC1 0x0054 /* Multicast filter table */ 79 #define MC2 0x0058 /* Multicast filter table */ 80 #define MC3 0x005C /* Multicast filter table */ 81 #define RXCON 0x0060 /* Rx control register */ 82 #define TXCON 0x0070 /* Tx control register */ 83 #define TXSTAT 0x0074 84 #define PRCDAR 0x0084 /* RxRing bus address */ 85 #define PRSTAT 0x00A4 86 #define PRCPTHR 0x00B0 87 #define PTCDAR 0x00C4 /* TxRing bus address */ 88 #define ETXTHR 0x00DC 89 90 #define COMMAND_STOP_RX 0x01 91 #define COMMAND_START_RX 0x02 92 #define COMMAND_TXQUEUED 0x04 93 #define COMMAND_RXQUEUED 0x08 94 #define COMMAND_NEXTFRAME 0x10 95 #define COMMAND_STOP_TDMA 0x20 96 #define COMMAND_STOP_RDMA 0x40 97 #define COMMAND_TXUGO 0x80 98 99 /* Interrupt register bits */ 100 #define INTSTAT_RCC 0x00000001 101 #define INTSTAT_HCC 0x00000002 102 #define INTSTAT_RQE 0x00000004 103 #define INTSTAT_OVW 0x00000008 104 #define INTSTAT_RXE 0x00000010 105 #define INTSTAT_TXC 0x00000020 106 #define INTSTAT_TCC 0x00000040 107 #define INTSTAT_TQE 0x00000080 108 #define INTSTAT_TXU 0x00000100 109 #define INTSTAT_CNT 0x00000200 110 #define INTSTAT_PREI 0x00000400 111 #define INTSTAT_RCT 0x00000800 112 #define INTSTAT_FATAL 0x00001000 /* One of DPE,APE,PMA,PTA happend */ 113 #define INTSTAT_UNUSED1 0x00002000 114 #define INTSTAT_UNUSED2 0x00004000 115 #define INTSTAT_GP2 0x00008000 /* PHY Event */ 116 #define INTSTAT_INT_ACTV 0x00010000 117 #define INTSTAT_RXIDLE 0x00020000 118 #define INTSTAT_TXIDLE 0x00040000 119 #define INTSTAT_RCIP 0x00080000 120 #define INTSTAT_TCIP 0x00100000 121 #define INTSTAT_RBE 0x00200000 122 #define INTSTAT_RCTS 0x00400000 123 #define INTSTAT_RSV 0x00800000 124 #define INTSTAT_DPE 0x01000000 /* PCI Fatal error */ 125 #define INTSTAT_APE 0x02000000 /* PCI Fatal error */ 126 #define INTSTAT_PMA 0x04000000 /* PCI Fatal error */ 127 #define INTSTAT_PTA 0x08000000 /* PCI Fatal error */ 128 129 #define GENCTL_SOFT_RESET 0x00000001 130 #define GENCTL_ENABLE_INTERRUPT 0x00000002 131 #define GENCTL_SOFTWARE_INTERRUPT 0x00000004 132 #define GENCTL_POWER_DOWN 0x00000008 133 #define GENCTL_ONECOPY 0x00000010 134 #define GENCTL_BIG_ENDIAN 0x00000020 135 #define GENCTL_RECEIVE_DMA_PRIORITY 0x00000040 136 #define GENCTL_TRANSMIT_DMA_PRIORITY 0x00000080 137 #define GENCTL_RECEIVE_FIFO_THRESHOLD128 0x00000300 138 #define GENCTL_RECEIVE_FIFO_THRESHOLD96 0x00000200 139 #define GENCTL_RECEIVE_FIFO_THRESHOLD64 0x00000100 140 #define GENCTL_RECEIVE_FIFO_THRESHOLD32 0x00000000 141 #define GENCTL_MEMORY_READ_LINE 0x00000400 142 #define GENCTL_MEMORY_READ_MULTIPLE 0x00000800 143 #define GENCTL_SOFTWARE1 0x00001000 144 #define GENCTL_SOFTWARE2 0x00002000 145 #define GENCTL_RESET_PHY 0x00004000 146 147 #define NVCTL_ENABLE_MEMORY_MAP 0x00000001 148 #define NVCTL_CLOCK_RUN_SUPPORTED 0x00000002 149 #define NVCTL_GP1_OUTPUT_ENABLE 0x00000004 150 #define NVCTL_GP2_OUTPUT_ENABLE 0x00000008 151 #define NVCTL_GP1 0x00000010 152 #define NVCTL_GP2 0x00000020 153 #define NVCTL_CARDBUS_MODE 0x00000040 154 #define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7) 155 156 #define RXCON_SAVE_ERRORED_PACKETS 0x00000001 157 #define RXCON_RECEIVE_RUNT_FRAMES 0x00000002 158 #define RXCON_RECEIVE_BROADCAST_FRAMES 0x00000004 159 #define RXCON_RECEIVE_MULTICAST_FRAMES 0x00000008 160 #define RXCON_RECEIVE_INVERSE_INDIVIDUAL_ADDRESS_FRAMES 0x00000010 161 #define RXCON_PROMISCUOUS_MODE 0x00000020 162 #define RXCON_MONITOR_MODE 0x00000040 163 #define RXCON_EARLY_RECEIVE_ENABLE 0x00000080 164 #define RXCON_EXTERNAL_BUFFER_DISABLE 0x00000000 165 #define RXCON_EXTERNAL_BUFFER_16K 0x00000100 166 #define RXCON_EXTERNAL_BUFFER_32K 0x00000200 167 #define RXCON_EXTERNAL_BUFFER_128K 0x00000300 168 169 #define TXCON_EARLY_TRANSMIT_ENABLE 0x00000001 170 #define TXCON_LOOPBACK_DISABLE 0x00000000 171 #define TXCON_LOOPBACK_MODE_INT 0x00000002 172 #define TXCON_LOOPBACK_MODE_PHY 0x00000004 173 #define TXCON_LOOPBACK_MODE 0x00000006 174 #define TXCON_FULL_DUPLEX 0x00000006 175 #define TXCON_SLOT_TIME 0x00000078 176 177 #define MIICFG_SERIAL_ENABLE 0x00000001 178 #define MIICFG_694_ENABLE 0x00000002 179 #define MIICFG_694_STATUS 0x00000004 180 #define MIICFG_PHY_PRESENT 0x00000008 181 #define MIICFG_SMI_ENABLE 0x00000010 182 183 #define TEST1_CLOCK_TEST 0x00000008 184 185 /* 186 * Some default values 187 */ 188 #define TXCON_DEFAULT (TXCON_SLOT_TIME | TXCON_EARLY_TRANSMIT_ENABLE) 189 #define TRANSMIT_THRESHOLD 0x300 190 191 #if defined(EARLY_RX) 192 #define RXCON_EARLY (RXCON_EARLY_RECEIVE_ENABLE | \ 193 RXCON_SAVE_ERRORED_PACKETS) 194 #else 195 #define RXCON_EARLY (0) 196 #endif 197 198 #define RXCON_DEFAULT (RXCON_EARLY | \ 199 RXCON_RECEIVE_MULTICAST_FRAMES | \ 200 RXCON_RECEIVE_BROADCAST_FRAMES) 201 202 /* 203 * Structures definition and Functions prototypes 204 */ 205 206 /* EPIC's hardware descriptors, must be aligned on dword in memory */ 207 /* NB: to make driver happy, this two structures MUST have thier sizes */ 208 /* be divisor of PAGE_SIZE */ 209 struct epic_tx_desc { 210 volatile u_int16_t status; 211 volatile u_int16_t txlength; 212 volatile u_int32_t bufaddr; 213 volatile u_int16_t buflength; 214 volatile u_int16_t control; 215 volatile u_int32_t next; 216 }; 217 struct epic_rx_desc { 218 volatile u_int16_t status; 219 volatile u_int16_t rxlength; 220 volatile u_int32_t bufaddr; 221 volatile u_int32_t buflength; 222 volatile u_int32_t next; 223 }; 224 225 /* This structure defines EPIC's fragment list, maximum number of frags */ 226 /* is 63. Let use maximum, becouse size of struct MUST be divisor of */ 227 /* PAGE_SIZE, and sometimes come mbufs with more than 30 frags */ 228 #define EPIC_MAX_FRAGS 63 229 struct epic_frag_list { 230 volatile u_int32_t numfrags; 231 struct { 232 volatile u_int32_t fragaddr; 233 volatile u_int32_t fraglen; 234 } frag[EPIC_MAX_FRAGS]; 235 volatile u_int32_t pad; /* align on 256 bytes */ 236 }; 237 238 /* This is driver's structure to define EPIC descriptors */ 239 struct epic_rx_buffer { 240 struct mbuf * mbuf; /* mbuf receiving packet */ 241 }; 242 243 struct epic_tx_buffer { 244 struct mbuf * mbuf; /* mbuf contained packet */ 245 }; 246 247 /* 248 * NB: ALIGN OF ABOVE STRUCTURES 249 * epic_rx_desc, epic_tx_desc, epic_frag_list - must be aligned on dword 250 */ 251 252 /* PHY, known by tx driver */ 253 #define EPIC_UNKN_PHY 0x0000 254 #define EPIC_QS6612_PHY 0x0001 255 #define EPIC_AC101_PHY 0x0002 256 #define EPIC_LXT970_PHY 0x0003 257 #define EPIC_SERIAL 0x0004 258 259 #define SMC9432DMT 0xA010 260 #define SMC9432TX 0xA011 261 #define SMC9032TXM 0xA012 262 #define SMC9032TX 0xA013 263 #define SMC9432TXPWR 0xA014 264 #define SMC9432BTX 0xA015 265 #define SMC9432FTX 0xA016 266 #define SMC9432FTX_SC 0xA017 267 #define SMC9432TX_XG_ADHOC 0xA020 268 #define SMC9434TX_XG_ADHOC 0xA021 269 #define SMC9432FTX_ADHOC 0xA022 270 #define SMC9432BTX1 0xA024 271 272 /* Driver status structure */ 273 typedef struct { 274 #if defined(__OpenBSD__) 275 struct device dev; 276 struct arpcom arpcom; 277 mii_data_t miibus; 278 struct timeout sc_tmo; 279 #else /* __FreeBSD__ */ 280 struct resource *res; 281 struct resource *irq; 282 283 device_t miibus; 284 device_t dev; 285 struct callout_handle stat_ch; 286 287 u_int32_t unit; 288 #endif 289 void *sc_ih; 290 bus_space_tag_t sc_st; 291 bus_space_handle_t sc_sh; 292 293 struct epic_rx_buffer rx_buffer[RX_RING_SIZE]; 294 struct epic_tx_buffer tx_buffer[TX_RING_SIZE]; 295 296 /* Each element of array MUST be aligned on dword */ 297 /* and bounded on PAGE_SIZE */ 298 struct epic_rx_desc *rx_desc; 299 struct epic_tx_desc *tx_desc; 300 struct epic_frag_list *tx_flist; 301 u_int32_t flags; 302 u_int32_t tx_threshold; 303 u_int32_t txcon; 304 u_int32_t miicfg; 305 u_int32_t cur_tx; 306 u_int32_t cur_rx; 307 u_int32_t dirty_tx; 308 u_int32_t pending_txs; 309 u_int16_t cardvend; 310 u_int16_t cardid; 311 struct mii_softc *physc; 312 u_int32_t phyid; 313 int serinst; 314 void *pool; 315 } epic_softc_t; 316 317 struct epic_type { 318 u_int16_t ven_id; 319 u_int16_t dev_id; 320 char *name; 321 }; 322 323 #if defined(EPIC_DEBUG) 324 #define dprintf(a) printf a 325 #else 326 #define dprintf(a) 327 #endif 328 329 #if defined(__FreeBSD__) 330 #define EPIC_FORMAT "tx%d" 331 #define EPIC_ARGS(sc) (sc->unit) 332 #define EPIC_BPFTAP_ARG(ifp) ifp 333 #else /* __OpenBSD__ */ 334 #define EPIC_FORMAT "%s" 335 #define EPIC_ARGS(sc) (sc->dev.dv_xname) 336 #define EPIC_BPFTAP_ARG(ifp) (ifp)->if_bpf 337 #endif 338 339 #define sc_if arpcom.ac_if 340 #define sc_macaddr arpcom.ac_enaddr 341 342 #define CSR_WRITE_4(sc,reg,val) \ 343 bus_space_write_4( (sc)->sc_st, (sc)->sc_sh, (reg), (val) ) 344 #define CSR_WRITE_2(sc,reg,val) \ 345 bus_space_write_2( (sc)->sc_st, (sc)->sc_sh, (reg), (val) ) 346 #define CSR_WRITE_1(sc,reg,val) \ 347 bus_space_write_1( (sc)->sc_st, (sc)->sc_sh, (reg), (val) ) 348 #define CSR_READ_4(sc,reg) \ 349 bus_space_read_4( (sc)->sc_st, (sc)->sc_sh, (reg) ) 350 #define CSR_READ_2(sc,reg) \ 351 bus_space_read_2( (sc)->sc_st, (sc)->sc_sh, (reg) ) 352 #define CSR_READ_1(sc,reg) \ 353 bus_space_read_1( (sc)->sc_st, (sc)->sc_sh, (reg) ) 354 355 #define PHY_READ_2(sc,phy,reg) \ 356 epic_read_phy_reg((sc),(phy),(reg)) 357 #define PHY_WRITE_2(sc,phy,reg,val) \ 358 epic_write_phy_reg((sc),(phy),(reg),(val)) 359 360 /* Macro to get either mbuf cluster or nothing */ 361 #define EPIC_MGETCLUSTER(m) \ 362 { MGETHDR((m),M_DONTWAIT,MT_DATA); \ 363 if (m) { \ 364 MCLGET((m),M_DONTWAIT); \ 365 if(!((m)->m_flags & M_EXT)) { \ 366 m_freem(m); \ 367 (m) = NULL; \ 368 } \ 369 } \ 370 } 371 /* 372 * Platform Independant Field Accessors 373 */ 374 #if defined(__OpenBSD__) 375 376 #define epic_dev(sc) (*sc) 377 #define epic_dev_ptr(sc) (void *)(sc) 378 379 #define epic_mii(sc) (sc->miibus) 380 #define epic_mii_ptr(sc) (&sc->miibus) 381 382 #else 383 384 #define epic_dev(dev) (*(device_get_softc(dev)) 385 #define epic_dev_ptr(dev) (device_get_softc(dev)) 386 387 #define epic_mii(sc) (*(device_get_softc(sc->miibus)) 388 #define epic_mii_ptr(sc) (device_get_softc(sc->miibus)) 389 390 #endif 391