1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright 1997, Stefan Esser <se@freebsd.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 */
28
29 #ifndef _PCIVAR_H_
30 #define _PCIVAR_H_
31
32 #include <sys/queue.h>
33 #include <sys/_eventhandler.h>
34
35 /* some PCI bus constants */
36 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
37 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
38 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
39
40 typedef uint64_t pci_addr_t;
41
42 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */
43 struct pcicfg_bridge {
44 uint8_t br_seclat;
45 uint8_t br_subbus;
46 uint8_t br_secbus;
47 uint8_t br_pribus;
48 uint16_t br_control;
49 };
50
51 /* Interesting values for PCI power management */
52 struct pcicfg_pp {
53 uint16_t pp_cap; /* PCI power management capabilities */
54 uint8_t pp_status; /* conf. space addr. of PM control/status reg */
55 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */
56 uint8_t pp_data; /* conf. space addr. of PM data reg */
57 };
58
59 struct pci_map {
60 pci_addr_t pm_value; /* Raw BAR value */
61 pci_addr_t pm_size;
62 uint16_t pm_reg;
63 STAILQ_ENTRY(pci_map) pm_link;
64 };
65
66 struct vpd_readonly {
67 char keyword[2];
68 char *value;
69 int len;
70 };
71
72 struct vpd_write {
73 char keyword[2];
74 char *value;
75 int start;
76 int len;
77 };
78
79 struct pcicfg_vpd {
80 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
81 char vpd_cached;
82 char *vpd_ident; /* string identifier */
83 int vpd_rocnt;
84 struct vpd_readonly *vpd_ros;
85 int vpd_wcnt;
86 struct vpd_write *vpd_w;
87 };
88
89 /* Interesting values for PCI MSI */
90 struct pcicfg_msi {
91 uint16_t msi_ctrl; /* Message Control */
92 uint8_t msi_location; /* Offset of MSI capability registers. */
93 uint8_t msi_msgnum; /* Number of messages */
94 int msi_alloc; /* Number of allocated messages. */
95 uint64_t msi_addr; /* Contents of address register. */
96 uint16_t msi_data; /* Contents of data register. */
97 u_int msi_handlers;
98 };
99
100 /* Interesting values for PCI MSI-X */
101 struct msix_vector {
102 uint64_t mv_address; /* Contents of address register. */
103 uint32_t mv_data; /* Contents of data register. */
104 int mv_irq;
105 };
106
107 struct msix_table_entry {
108 u_int mte_vector; /* 1-based index into msix_vectors array. */
109 u_int mte_handlers;
110 };
111
112 struct pcicfg_msix {
113 uint16_t msix_ctrl; /* Message Control */
114 uint16_t msix_msgnum; /* Number of messages */
115 uint8_t msix_location; /* Offset of MSI-X capability registers. */
116 uint8_t msix_table_bar; /* BAR containing vector table. */
117 uint8_t msix_pba_bar; /* BAR containing PBA. */
118 uint32_t msix_table_offset;
119 uint32_t msix_pba_offset;
120 int msix_alloc; /* Number of allocated vectors. */
121 int msix_table_len; /* Length of virtual table. */
122 struct msix_table_entry *msix_table; /* Virtual table. */
123 struct msix_vector *msix_vectors; /* Array of allocated vectors. */
124 struct resource *msix_table_res; /* Resource containing vector table. */
125 struct resource *msix_pba_res; /* Resource containing PBA. */
126 };
127
128 /* Interesting values for HyperTransport */
129 struct pcicfg_ht {
130 uint8_t ht_slave; /* Non-zero if device is an HT slave. */
131 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
132 uint16_t ht_msictrl; /* MSI mapping control */
133 uint64_t ht_msiaddr; /* MSI mapping base address */
134 };
135
136 /* Interesting values for PCI-express */
137 struct pcicfg_pcie {
138 uint8_t pcie_location; /* Offset of PCI-e capability registers. */
139 uint8_t pcie_type; /* Device type. */
140 uint16_t pcie_flags; /* Device capabilities register. */
141 uint16_t pcie_device_ctl; /* Device control register. */
142 uint16_t pcie_link_ctl; /* Link control register. */
143 uint16_t pcie_slot_ctl; /* Slot control register. */
144 uint16_t pcie_root_ctl; /* Root control register. */
145 uint16_t pcie_device_ctl2; /* Second device control register. */
146 uint16_t pcie_link_ctl2; /* Second link control register. */
147 uint16_t pcie_slot_ctl2; /* Second slot control register. */
148 };
149
150 struct pcicfg_pcix {
151 uint16_t pcix_command;
152 uint8_t pcix_location; /* Offset of PCI-X capability registers. */
153 };
154
155 struct pcicfg_vf {
156 int index;
157 };
158
159 struct pci_ea_entry {
160 int eae_bei;
161 uint32_t eae_flags;
162 uint64_t eae_base;
163 uint64_t eae_max_offset;
164 uint32_t eae_cfg_offset;
165 STAILQ_ENTRY(pci_ea_entry) eae_link;
166 };
167
168 struct pcicfg_ea {
169 int ea_location; /* Structure offset in Configuration Header */
170 STAILQ_HEAD(, pci_ea_entry) ea_entries; /* EA entries */
171 };
172
173 #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */
174
175 /* config header information common to all header types */
176 typedef struct pcicfg {
177 device_t dev; /* device which owns this */
178
179 STAILQ_HEAD(, pci_map) maps; /* BARs */
180
181 uint16_t subvendor; /* card vendor ID */
182 uint16_t subdevice; /* card device ID, assigned by card vendor */
183 uint16_t vendor; /* chip vendor ID */
184 uint16_t device; /* chip device ID, assigned by chip vendor */
185
186 uint16_t cmdreg; /* disable/enable chip and PCI options */
187 uint16_t statreg; /* supported PCI features and error state */
188
189 uint8_t baseclass; /* chip PCI class */
190 uint8_t subclass; /* chip PCI subclass */
191 uint8_t progif; /* chip PCI programming interface */
192 uint8_t revid; /* chip revision ID */
193
194 uint8_t hdrtype; /* chip config header type */
195 uint8_t cachelnsz; /* cache line size in 4byte units */
196 uint8_t intpin; /* PCI interrupt pin */
197 uint8_t intline; /* interrupt line (IRQ for PC arch) */
198
199 uint8_t mingnt; /* min. useful bus grant time in 250ns units */
200 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
201 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
202
203 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
204 uint8_t nummaps; /* actual number of PCI maps used */
205
206 uint32_t domain; /* PCI domain */
207 uint8_t bus; /* config space bus address */
208 uint8_t slot; /* config space slot address */
209 uint8_t func; /* config space function number */
210
211 uint32_t flags; /* flags defined above */
212
213 struct pcicfg_bridge bridge; /* Bridges */
214 struct pcicfg_pp pp; /* Power management */
215 struct pcicfg_vpd vpd; /* Vital product data */
216 struct pcicfg_msi msi; /* PCI MSI */
217 struct pcicfg_msix msix; /* PCI MSI-X */
218 struct pcicfg_ht ht; /* HyperTransport */
219 struct pcicfg_pcie pcie; /* PCI Express */
220 struct pcicfg_pcix pcix; /* PCI-X */
221 struct pcicfg_iov *iov; /* SR-IOV */
222 struct pcicfg_vf vf; /* SR-IOV Virtual Function */
223 struct pcicfg_ea ea; /* Enhanced Allocation */
224 } pcicfgregs;
225
226 /* additional type 1 device config header information (PCI to PCI bridge) */
227
228 typedef struct {
229 pci_addr_t pmembase; /* base address of prefetchable memory */
230 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
231 uint32_t membase; /* base address of memory window */
232 uint32_t memlimit; /* topmost address of memory window */
233 uint32_t iobase; /* base address of port window */
234 uint32_t iolimit; /* topmost address of port window */
235 uint16_t secstat; /* secondary bus status register */
236 uint16_t bridgectl; /* bridge control register */
237 uint8_t seclat; /* CardBus latency timer */
238 } pcih1cfgregs;
239
240 /* additional type 2 device config header information (CardBus bridge) */
241
242 typedef struct {
243 uint32_t membase0; /* base address of memory window */
244 uint32_t memlimit0; /* topmost address of memory window */
245 uint32_t membase1; /* base address of memory window */
246 uint32_t memlimit1; /* topmost address of memory window */
247 uint32_t iobase0; /* base address of port window */
248 uint32_t iolimit0; /* topmost address of port window */
249 uint32_t iobase1; /* base address of port window */
250 uint32_t iolimit1; /* topmost address of port window */
251 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
252 uint16_t secstat; /* secondary bus status register */
253 uint16_t bridgectl; /* bridge control register */
254 uint8_t seclat; /* CardBus latency timer */
255 } pcih2cfgregs;
256
257 extern uint32_t pci_numdevs;
258 extern int pci_enable_aspm;
259
260 /*
261 * The bitfield has to be stable and match the fields below (so that
262 * match_flag_vendor must be bit 0) so we have to do the endian dance. We can't
263 * use enums or #define constants because then the macros for subsetting matches
264 * wouldn't work. These tables are parsed by devmatch and others to connect
265 * modules with devices on the PCI bus.
266 */
267 struct pci_device_table {
268 #if BYTE_ORDER == LITTLE_ENDIAN
269 uint16_t
270 match_flag_vendor:1,
271 match_flag_device:1,
272 match_flag_subvendor:1,
273 match_flag_subdevice:1,
274 match_flag_class:1,
275 match_flag_subclass:1,
276 match_flag_revid:1,
277 match_flag_unused:9;
278 #else
279 uint16_t
280 match_flag_unused:9,
281 match_flag_revid:1,
282 match_flag_subclass:1,
283 match_flag_class:1,
284 match_flag_subdevice:1,
285 match_flag_subvendor:1,
286 match_flag_device:1,
287 match_flag_vendor:1;
288 #endif
289 uint16_t vendor;
290 uint16_t device;
291 uint16_t subvendor;
292 uint16_t subdevice;
293 uint16_t class_id;
294 uint16_t subclass;
295 uint16_t revid;
296 uint16_t unused;
297 uintptr_t driver_data;
298 char *descr;
299 };
300
301 #define PCI_DEV(v, d) \
302 .match_flag_vendor = 1, .vendor = (v), \
303 .match_flag_device = 1, .device = (d)
304 #define PCI_SUBDEV(sv, sd) \
305 .match_flag_subvendor = 1, .subvendor = (sv), \
306 .match_flag_subdevice = 1, .subdevice = (sd)
307 #define PCI_CLASS(x) \
308 .match_flag_class = 1, .class_id = (x)
309 #define PCI_SUBCLASS(x) \
310 .match_flag_subclass = 1, .subclass = (x)
311 #define PCI_REVID(x) \
312 .match_flag_revid = 1, .revid = (x)
313 #define PCI_DESCR(x) \
314 .descr = (x)
315 #define PCI_PNP_STR \
316 "M16:mask;U16:vendor;U16:device;U16:subvendor;U16:subdevice;" \
317 "U16:class;U16:subclass;U16:revid;"
318 #define PCI_PNP_INFO(table) \
319 MODULE_PNP_INFO(PCI_PNP_STR, pci, table, table, \
320 sizeof(table) / sizeof(table[0]))
321
322 const struct pci_device_table *pci_match_device(device_t child,
323 const struct pci_device_table *id, size_t nelt);
324 #define PCI_MATCH(child, table) \
325 pci_match_device(child, (table), nitems(table));
326
327 /* Only if the prerequisites are present */
328 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
329 struct pci_devinfo {
330 STAILQ_ENTRY(pci_devinfo) pci_links;
331 struct resource_list resources;
332 pcicfgregs cfg;
333 struct pci_conf conf;
334 };
335 #endif
336
337 #ifdef _SYS_BUS_H_
338
339 #include "pci_if.h"
340
341 enum pci_device_ivars {
342 PCI_IVAR_SUBVENDOR,
343 PCI_IVAR_SUBDEVICE,
344 PCI_IVAR_VENDOR,
345 PCI_IVAR_DEVICE,
346 PCI_IVAR_DEVID,
347 PCI_IVAR_CLASS,
348 PCI_IVAR_SUBCLASS,
349 PCI_IVAR_PROGIF,
350 PCI_IVAR_REVID,
351 PCI_IVAR_INTPIN,
352 PCI_IVAR_IRQ,
353 PCI_IVAR_DOMAIN,
354 PCI_IVAR_BUS,
355 PCI_IVAR_SLOT,
356 PCI_IVAR_FUNCTION,
357 PCI_IVAR_ETHADDR,
358 PCI_IVAR_CMDREG,
359 PCI_IVAR_CACHELNSZ,
360 PCI_IVAR_MINGNT,
361 PCI_IVAR_MAXLAT,
362 PCI_IVAR_LATTIMER
363 };
364
365 /*
366 * Simplified accessors for pci devices
367 */
368 #define PCI_ACCESSOR(var, ivar, type) \
369 __BUS_ACCESSOR(pci, var, PCI, ivar, type)
370
PCI_ACCESSOR(subvendor,SUBVENDOR,uint16_t)371 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
372 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
373 PCI_ACCESSOR(vendor, VENDOR, uint16_t)
374 PCI_ACCESSOR(device, DEVICE, uint16_t)
375 PCI_ACCESSOR(devid, DEVID, uint32_t)
376 PCI_ACCESSOR(class, CLASS, uint8_t)
377 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
378 PCI_ACCESSOR(progif, PROGIF, uint8_t)
379 PCI_ACCESSOR(revid, REVID, uint8_t)
380 PCI_ACCESSOR(intpin, INTPIN, uint8_t)
381 PCI_ACCESSOR(irq, IRQ, uint8_t)
382 PCI_ACCESSOR(domain, DOMAIN, uint32_t)
383 PCI_ACCESSOR(bus, BUS, uint8_t)
384 PCI_ACCESSOR(slot, SLOT, uint8_t)
385 PCI_ACCESSOR(function, FUNCTION, uint8_t)
386 PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
387 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
388 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
389 PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
390 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
391 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
392
393 #undef PCI_ACCESSOR
394
395 /*
396 * Operations on configuration space.
397 */
398 static __inline uint32_t
399 pci_read_config(device_t dev, int reg, int width)
400 {
401 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
402 }
403
404 static __inline void
pci_write_config(device_t dev,int reg,uint32_t val,int width)405 pci_write_config(device_t dev, int reg, uint32_t val, int width)
406 {
407 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
408 }
409
410 /*
411 * Ivars for pci bridges.
412 */
413
414 /*typedef enum pci_device_ivars pcib_device_ivars;*/
415 enum pcib_device_ivars {
416 PCIB_IVAR_DOMAIN,
417 PCIB_IVAR_BUS
418 };
419
420 #define PCIB_ACCESSOR(var, ivar, type) \
421 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
422
PCIB_ACCESSOR(domain,DOMAIN,uint32_t)423 PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
424 PCIB_ACCESSOR(bus, BUS, uint32_t)
425
426 #undef PCIB_ACCESSOR
427
428 /*
429 * PCI interrupt validation. Invalid interrupt values such as 0 or 128
430 * on i386 or other platforms should be mapped out in the MD pcireadconf
431 * code and not here, since the only MI invalid IRQ is 255.
432 */
433 #define PCI_INVALID_IRQ 255
434 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
435
436 /*
437 * Convenience functions.
438 *
439 * These should be used in preference to manually manipulating
440 * configuration space.
441 */
442 static __inline int
443 pci_enable_busmaster(device_t dev)
444 {
445 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
446 }
447
448 static __inline int
pci_disable_busmaster(device_t dev)449 pci_disable_busmaster(device_t dev)
450 {
451 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
452 }
453
454 static __inline int
pci_enable_io(device_t dev,int space)455 pci_enable_io(device_t dev, int space)
456 {
457 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
458 }
459
460 static __inline int
pci_disable_io(device_t dev,int space)461 pci_disable_io(device_t dev, int space)
462 {
463 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
464 }
465
466 static __inline int
pci_get_vpd_ident(device_t dev,const char ** identptr)467 pci_get_vpd_ident(device_t dev, const char **identptr)
468 {
469 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
470 }
471
472 static __inline int
pci_get_vpd_readonly(device_t dev,const char * kw,const char ** vptr)473 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr)
474 {
475 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr));
476 }
477
478 /*
479 * Check if the address range falls within the VGA defined address range(s)
480 */
481 static __inline int
pci_is_vga_ioport_range(rman_res_t start,rman_res_t end)482 pci_is_vga_ioport_range(rman_res_t start, rman_res_t end)
483 {
484
485 return (((start >= 0x3b0 && end <= 0x3bb) ||
486 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
487 }
488
489 static __inline int
pci_is_vga_memory_range(rman_res_t start,rman_res_t end)490 pci_is_vga_memory_range(rman_res_t start, rman_res_t end)
491 {
492
493 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
494 }
495
496 /*
497 * PCI power states are as defined by ACPI:
498 *
499 * D0 State in which device is on and running. It is receiving full
500 * power from the system and delivering full functionality to the user.
501 * D1 Class-specific low-power state in which device context may or may not
502 * be lost. Buses in D1 cannot do anything to the bus that would force
503 * devices on that bus to lose context.
504 * D2 Class-specific low-power state in which device context may or may
505 * not be lost. Attains greater power savings than D1. Buses in D2
506 * can cause devices on that bus to lose some context. Devices in D2
507 * must be prepared for the bus to be in D2 or higher.
508 * D3 State in which the device is off and not running. Device context is
509 * lost. Power can be removed from the device.
510 */
511 #define PCI_POWERSTATE_D0 0
512 #define PCI_POWERSTATE_D1 1
513 #define PCI_POWERSTATE_D2 2
514 #define PCI_POWERSTATE_D3 3
515 #define PCI_POWERSTATE_UNKNOWN -1
516
517 static __inline int
pci_set_powerstate(device_t dev,int state)518 pci_set_powerstate(device_t dev, int state)
519 {
520 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
521 }
522
523 static __inline int
pci_get_powerstate(device_t dev)524 pci_get_powerstate(device_t dev)
525 {
526 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
527 }
528
529 static __inline int
pci_find_cap(device_t dev,int capability,int * capreg)530 pci_find_cap(device_t dev, int capability, int *capreg)
531 {
532 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg));
533 }
534
535 static __inline int
pci_find_next_cap(device_t dev,int capability,int start,int * capreg)536 pci_find_next_cap(device_t dev, int capability, int start, int *capreg)
537 {
538 return (PCI_FIND_NEXT_CAP(device_get_parent(dev), dev, capability, start,
539 capreg));
540 }
541
542 static __inline int
pci_find_extcap(device_t dev,int capability,int * capreg)543 pci_find_extcap(device_t dev, int capability, int *capreg)
544 {
545 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
546 }
547
548 static __inline int
pci_find_next_extcap(device_t dev,int capability,int start,int * capreg)549 pci_find_next_extcap(device_t dev, int capability, int start, int *capreg)
550 {
551 return (PCI_FIND_NEXT_EXTCAP(device_get_parent(dev), dev, capability,
552 start, capreg));
553 }
554
555 static __inline int
pci_find_htcap(device_t dev,int capability,int * capreg)556 pci_find_htcap(device_t dev, int capability, int *capreg)
557 {
558 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg));
559 }
560
561 static __inline int
pci_find_next_htcap(device_t dev,int capability,int start,int * capreg)562 pci_find_next_htcap(device_t dev, int capability, int start, int *capreg)
563 {
564 return (PCI_FIND_NEXT_HTCAP(device_get_parent(dev), dev, capability,
565 start, capreg));
566 }
567
568 static __inline int
pci_alloc_msi(device_t dev,int * count)569 pci_alloc_msi(device_t dev, int *count)
570 {
571 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
572 }
573
574 static __inline int
pci_alloc_msix(device_t dev,int * count)575 pci_alloc_msix(device_t dev, int *count)
576 {
577 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
578 }
579
580 static __inline void
pci_enable_msi(device_t dev,uint64_t address,uint16_t data)581 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
582 {
583 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data);
584 }
585
586 static __inline void
pci_enable_msix(device_t dev,u_int index,uint64_t address,uint32_t data)587 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
588 {
589 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data);
590 }
591
592 static __inline void
pci_disable_msi(device_t dev)593 pci_disable_msi(device_t dev)
594 {
595 PCI_DISABLE_MSI(device_get_parent(dev), dev);
596 }
597
598 static __inline int
pci_remap_msix(device_t dev,int count,const u_int * vectors)599 pci_remap_msix(device_t dev, int count, const u_int *vectors)
600 {
601 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
602 }
603
604 static __inline int
pci_release_msi(device_t dev)605 pci_release_msi(device_t dev)
606 {
607 return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
608 }
609
610 static __inline int
pci_msi_count(device_t dev)611 pci_msi_count(device_t dev)
612 {
613 return (PCI_MSI_COUNT(device_get_parent(dev), dev));
614 }
615
616 static __inline int
pci_msix_count(device_t dev)617 pci_msix_count(device_t dev)
618 {
619 return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
620 }
621
622 static __inline int
pci_msix_pba_bar(device_t dev)623 pci_msix_pba_bar(device_t dev)
624 {
625 return (PCI_MSIX_PBA_BAR(device_get_parent(dev), dev));
626 }
627
628 static __inline int
pci_msix_table_bar(device_t dev)629 pci_msix_table_bar(device_t dev)
630 {
631 return (PCI_MSIX_TABLE_BAR(device_get_parent(dev), dev));
632 }
633
634 static __inline int
pci_get_id(device_t dev,enum pci_id_type type,uintptr_t * id)635 pci_get_id(device_t dev, enum pci_id_type type, uintptr_t *id)
636 {
637 return (PCI_GET_ID(device_get_parent(dev), dev, type, id));
638 }
639
640 /*
641 * This is the deprecated interface, there is no way to tell the difference
642 * between a failure and a valid value that happens to be the same as the
643 * failure value.
644 */
645 static __inline uint16_t
pci_get_rid(device_t dev)646 pci_get_rid(device_t dev)
647 {
648 uintptr_t rid;
649
650 if (pci_get_id(dev, PCI_ID_RID, &rid) != 0)
651 return (0);
652
653 return (rid);
654 }
655
656 static __inline void
pci_child_added(device_t dev)657 pci_child_added(device_t dev)
658 {
659
660 return (PCI_CHILD_ADDED(device_get_parent(dev), dev));
661 }
662
663 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
664 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
665 device_t pci_find_device(uint16_t, uint16_t);
666 device_t pci_find_class(uint8_t class, uint8_t subclass);
667 device_t pci_find_class_from(uint8_t class, uint8_t subclass, device_t devfrom);
668
669 /* Can be used by drivers to manage the MSI-X table. */
670 int pci_pending_msix(device_t dev, u_int index);
671
672 int pci_msi_device_blacklisted(device_t dev);
673 int pci_msix_device_blacklisted(device_t dev);
674
675 void pci_ht_map_msi(device_t dev, uint64_t addr);
676
677 device_t pci_find_pcie_root_port(device_t dev);
678 int pci_get_relaxed_ordering_enabled(device_t dev);
679 int pci_get_max_payload(device_t dev);
680 int pci_get_max_read_req(device_t dev);
681 void pci_restore_state(device_t dev);
682 void pci_save_state(device_t dev);
683 int pci_set_max_read_req(device_t dev, int size);
684 int pci_power_reset(device_t dev);
685 uint32_t pcie_read_config(device_t dev, int reg, int width);
686 void pcie_write_config(device_t dev, int reg, uint32_t value, int width);
687 uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask,
688 uint32_t value, int width);
689 void pcie_apei_error(device_t dev, int sev, uint8_t *aer);
690 bool pcie_flr(device_t dev, u_int max_delay, bool force);
691 int pcie_get_max_completion_timeout(device_t dev);
692 bool pcie_wait_for_pending_transactions(device_t dev, u_int max_delay);
693 int pcie_link_reset(device_t port, int pcie_location);
694
695 void pci_print_faulted_dev(void);
696
697 #endif /* _SYS_BUS_H_ */
698
699 /*
700 * cdev switch for control device, initialised in generic PCI code
701 */
702 extern struct cdevsw pcicdev;
703
704 /*
705 * List of all PCI devices, generation count for the list.
706 */
707 STAILQ_HEAD(devlist, pci_devinfo);
708
709 extern struct devlist pci_devq;
710 extern uint32_t pci_generation;
711
712 struct pci_map *pci_find_bar(device_t dev, int reg);
713 struct pci_map *pci_first_bar(device_t dev);
714 struct pci_map *pci_next_bar(struct pci_map *pm);
715 int pci_bar_enabled(device_t dev, struct pci_map *pm);
716 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev);
717
718 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000
719 #define VGA_PCI_BIOS_SHADOW_SIZE 131072
720
721 int vga_pci_is_boot_display(device_t dev);
722 void * vga_pci_map_bios(device_t dev, size_t *size);
723 void vga_pci_unmap_bios(device_t dev, void *bios);
724 int vga_pci_repost(device_t dev);
725
726 /**
727 * Global eventhandlers invoked when PCI devices are added or removed
728 * from the system.
729 */
730 typedef void (*pci_event_fn)(void *arg, device_t dev);
731 EVENTHANDLER_DECLARE(pci_add_device, pci_event_fn);
732 EVENTHANDLER_DECLARE(pci_delete_device, pci_event_fn);
733
734 #endif /* _PCIVAR_H_ */
735