1 /* $NetBSD: pcctworeg.h,v 1.3 2008/04/28 20:23:54 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Register definitions for the PCCchip2 device, and offset to the 34 * various subordinate devices which hang off it. 35 */ 36 #ifndef _MVME_PCCTWOREG_H 37 #define _MVME_PCCTWOREG_H 38 39 /* 40 * Offsets to the various devices which hang off the PCCChip2. 41 * Note that these are offsets from the base of the PCCChip2's 42 * own registers. 43 */ 44 #define PCCTWO_REG_OFF 0x00000 /* Offset of PCCChip2's own registers */ 45 #define PCCTWO_LPT_OFF 0x00000 /* Offset of parallel port registers */ 46 #define PCCTWO_SCC_OFF 0x03000 /* Offset of CD2401 Serial Comms chip */ 47 #define PCCTWO_IE_OFF 0x04000 /* Offset of 82596 LAN controller */ 48 #define PCCTWO_NCRSC_OFF 0x05000 /* Offset of NCR53C710 SCSI chip */ 49 50 /* 51 * The two devices on mvme1[67]2's MCchip 52 */ 53 #define MCCHIP_ZS0_OFF 0x03000 54 #define MCCHIP_ZS1_OFF 0x03800 55 56 /* 57 * This is needed to figure out the boot device. 58 * (The physical address of the boot device's registers are passed in 59 * from the Boot ROM) 60 */ 61 #define PCCTWO_PADDR(off) ((void *)(0xfff42000u + (off))) 62 63 64 /* 65 * The layout of the PCCchip2's Registers. 66 * Each one is 8-bits wide, unless otherwise indicated. 67 */ 68 #define PCC2REG_CHIP_ID 0x00 /* Chip ID */ 69 #define PCC2REG_CHIP_REVISION 0x01 /* Chip Revision */ 70 #define PCC2REG_GENERAL_CONTROL 0x02 /* General Control */ 71 #define PCC2REG_VECTOR_BASE 0x03 /* Vector Base */ 72 #define PCC2REG_TIMER1_COMPARE 0x04 /* Tick Timer 1 Compare (32-bit) */ 73 #define PCC2REG_TIMER1_COUNTER 0x08 /* Tick Timer 1 Counter (32-bit) */ 74 #define PCC2REG_TIMER2_COMPARE 0x0c /* Tick Timer 2 Compare (32-bit) */ 75 #define PCC2REG_TIMER2_COUNTER 0x10 /* Tick Timer 2 Counter (32-bit) */ 76 #define PCC2REG_PRESCALE_COUNT 0x14 /* Prescaler Count */ 77 #define PCC2REG_PRESCALE_ADJUST 0x15 /* Prescaler Clock Adjust */ 78 #define PCC2REG_TIMER2_CONTROL 0x16 /* Tick Timer 2 Control */ 79 #define PCC2REG_TIMER1_CONTROL 0x17 /* Tick Timer 1 Control */ 80 #define PCC2REG_GPIO_ICSR 0x18 /* GP Input Interrupt Control */ 81 #define PCC2REG_GPIO_CONTROL 0x19 /* GP Input/Output Control */ 82 #define PCC2REG_TIMER2_ICSR 0x1a /* Tick Timer 2 Interrupt Control */ 83 #define PCC2REG_TIMER1_ICSR 0x1b /* Tick Timer 1 Interrupt Control */ 84 #define PCC2REG_SCC_ERR_STATUS 0x1c /* SCC Error Status */ 85 #define PCC2REG_SCC_MODEM_ICSR 0x1d /* SCC Modem Interrupt Control */ 86 #define PCC2REG_SCC_TX_ICSR 0x1e /* SCC Transmit Interrupt Control */ 87 #define PCC2REG_SCC_RX_ICSR 0x1f /* SCC Receive Interrupt Control */ 88 #define PCC2REG_SCC_MODEM_PIACK 0x23 /* SCC Modem PIACK */ 89 #define PCC2REG_SCC_TX_PIACK 0x25 /* SCC Transmit PIACK */ 90 #define PCC2REG_SCC_RX_PIACK 0x27 /* SCC Receive PIACK */ 91 #define PCC2REG_ETH_ERR_STATUS 0x28 /* LANC Error Status */ 92 #define PCC2REG_ETH_ICSR 0x2a /* LANC Interrupt Control */ 93 #define PCC2REG_ETH_BERR_STATUS 0x2b /* LANC Bus Error Interrupt Ctrl */ 94 #define PCC2REG_SCSI_ERR_STATUS 0x2c /* SCSI Error Status */ 95 #define PCC2REG_SCSI_ICSR 0x2f /* SCSI Interrupt Control */ 96 #define PCC2REG_PRT_ACK_ICSR 0x30 /* Printer ACK Interrupt Control */ 97 #define PCC2REG_PRT_FAULT_ICSR 0x31 /* Printer FAULT Interrupt Ctrl */ 98 #define PCC2REG_PRT_SEL_ICSR 0x32 /* Printer SEL Interrupt Control */ 99 #define PCC2REG_PRT_PE_ICSR 0x33 /* Printer PE Interrupt Control */ 100 #define PCC2REG_PRT_BUSY_ICSR 0x34 /* Printer BUSY Interrupt Control */ 101 #define PCC2REG_PRT_INPUT_STATUS 0x36 /* Printer Input Status */ 102 #define PCC2REG_PRT_CONTROL 0x37 /* Printer Port Control */ 103 #define PCC2REG_CHIP_SPEED 0x38 /* Chip Speed (16-bit) */ 104 #define PCC2REG_PRT_DATA 0x3a /* Printer Data (16-bit) */ 105 #define PCC2REG_IRQ_LEVEL 0x3e /* Interrupt Priority Level */ 106 #define PCC2REG_IRQ_MASK 0x3f /* Interrupt Mask */ 107 108 /* 109 * Additions to the registers for the MCChip. Some of these overlap with 110 * the PCCchip2's registers, but only where hardware is not present, eg. 111 * the printer registers. 112 */ 113 #define MCCHIPREG_TIMER4_ICSR 0x18 /* Tick timer 4 interrupt control */ 114 #define MCCHIPREG_TIMER3_ICSR 0x19 /* Tick timer 4 interrupt control */ 115 #define MCCHIPREG_PARERR_ICSR 0x1c /* Parity error interrupt control */ 116 #define MCCHIPREG_SCC_ICSR 0x1d /* ZS-85230 interrupt control */ 117 #define MCCHIPREG_TIMER4_CTRL 0x1e /* Tick timer 4 control */ 118 #define MCCHIPREG_TIMER3_CTRL 0x1f /* Tick timer 3 control */ 119 #define MCCHIPREG_DRAM_BAR 0x20 /* DRAM Base Address (16-bits) */ 120 #define MCCHIPREG_SRAM_BAR 0x22 /* SRAM Base Address (16-bits) */ 121 #define MCCHIPREG_DRAM_SIZE 0x24 /* DRAM Size */ 122 #define MCCHIPREG_RAM_OPTIONS 0x25 /* DRAM/SRAM Options */ 123 #define MCCHIPREG_SRAM_SIZE 0x26 /* SRAM Size */ 124 #define MCCHIPREG_GP_INPUTS 0x2d /* General Purpose Inputs */ 125 #define MCCHIPREG_162_VERSION 0x2e /* MVME162-LX Series Version */ 126 #define MCCHIPREG_TIMER3_COMP 0x30 /* Tick Timer 3 Compare (32-bit) */ 127 #define MCCHIPREG_TIMER3_CNTR 0x34 /* Tick Timer 3 Counter (32-bit) */ 128 #define MCCHIPREG_TIMER4_COMP 0x38 /* Tick Timer 4 Compare (32-bit) */ 129 #define MCCHIPREG_TIMER4_CNTR 0x3c /* Tick Timer 4 Counter (32-bit) */ 130 #define MCCHIPREG_BUS_CLOCK 0x40 /* Bus Clock */ 131 #define MCCHIPREG_EPROM_TIMING 0x41 /* EPROM Access Time Control */ 132 #define MCCHIPREG_FLASH_TIMING 0x42 /* FLASH Access Time Control */ 133 #define MCCHIPREG_ABORT_ICSR 0x43 /* ABORT Switch Interrupt Control */ 134 #define MCCHIPREG_RESET_CONTROL 0x44 /* Reset Switch Control */ 135 #define MCCHIPREG_WDOG_CONTROL 0x45 /* Watchdog Timer Control */ 136 #define MCCHIPREG_TIMEBASE_SEL 0x46 /* Access & Watchdog Timebase Select */ 137 #define MCCHIPREG_DRAM_CONTROL 0x48 /* Parity DRAM Control */ 138 #define MCCHIPREG_MPU_STATUS 0x4a /* MPU Status */ 139 #define MCCHIPREG_PRESCALER 0x4c /* Prescaler Count Register (32-bits) */ 140 141 /* 142 * PCCchip2's register size is 0x40. MCchip's is 0x50. Plump for the latter. 143 */ 144 #define PCC2REG_SIZE 0x50 145 146 /* 147 * Convenience macroes for accessing the PCCChip2's registers 148 * through bus_space. 149 */ 150 #define pcc2_reg_read(sc,r) \ 151 bus_space_read_1((sc)->sc_bust, (sc)->sc_bush, (r)) 152 #define pcc2_reg_read16(sc,r) \ 153 bus_space_read_2((sc)->sc_bust, (sc)->sc_bush, (r)) 154 #define pcc2_reg_read32(sc,r) \ 155 bus_space_read_4((sc)->sc_bust, (sc)->sc_bush, (r)) 156 #define pcc2_reg_write(sc,r,v) \ 157 bus_space_write_1((sc)->sc_bust, (sc)->sc_bush, (r), (v)) 158 #define pcc2_reg_write16(sc,r,v) \ 159 bus_space_write_2((sc)->sc_bust, (sc)->sc_bush, (r), (v)) 160 #define pcc2_reg_write32(sc,r,v) \ 161 bus_space_write_4((sc)->sc_bust, (sc)->sc_bush, (r), (v)) 162 163 /* 164 * We use the interrupt vector bases suggested in the Motorola Docs... 165 * The first is written to the PCCChip2 for interrupt sources under 166 * its control. The second is written to the CD2401's Local Interrupt 167 * Vector Register. Thus, we don't use the Auto-Vector facilities 168 * for the CD2401, as recommended in the PCCChip2 Programmer's Guide. 169 * The third is used as a base for the ZS85230 serial chips on mvme162. 170 */ 171 #define PCCTWO_VECBASE 0x50 172 #define PCCTWO_SCC_VECBASE 0x5c 173 #define MCCHIP_ZS_VECBASE 0x5c 174 175 /* 176 * PCCchip2 Vector Encoding (Offsets from PCCTWO_VECBASE) 177 * The order 0x0 -> 0xf also indicates priority, with 0x0 lowest. 178 */ 179 #define PCCTWOV_PRT_BUSY 0x0 /* Printer Port 'BSY' */ 180 #define PCCTWOV_PRT_PE 0x1 /* Printer Port 'PE' (Paper Empty) */ 181 #define PCCTWOV_PRT_SELECT 0x2 /* Printer Port 'SELECT' */ 182 #define PCCTWOV_PRT_FAULT 0x3 /* Printer Port 'FAULT' */ 183 #define PCCTWOV_PRT_ACK 0x4 /* Printer Port 'ACK' */ 184 #define PCCTWOV_SCSI 0x5 /* SCSI Interrupt */ 185 #define PCCTWOV_LANC_ERR 0x6 /* LAN Controller Error */ 186 #define PCCTWOV_LANC_IRQ 0x7 /* LAN Controller Interrupt */ 187 #define PCCTWOV_TIMER2 0x8 /* Tick Timer 2 Interrupt */ 188 #define PCCTWOV_TIMER1 0x9 /* Tick Timer 1 Interrupt */ 189 #define PCCTWOV_GPIO 0xa /* General Purpose Input Interrupt */ 190 #define PCCTWOV_SCC_RX_EXCEP 0xc /* SCC Receive Exception */ 191 #define PCCTWOV_SCC_MODEM 0xd /* SCC Modem (Non-Auto-vector mode) */ 192 #define PCCTWOV_SCC_TX 0xe /* SCC Tx (Non-Auto-vector mode) */ 193 #define PCCTWOV_SCC_RX 0xf /* SCC Rx (Non-Auto-vector mode) */ 194 #define PCCTWOV_MAX 16 195 196 /* 197 * MCchip-specific Vector Encoding (Offsets from PCCTWO_VECBASE) 198 */ 199 #define MCCHIPV_TIMER4 0x3 /* Tick Timer 4 Interrupt */ 200 #define MCCHIPV_TIMER3 0x4 /* Tick Timer 3 Interrupt */ 201 #define MCCHIPV_PARITY_ERR 0xb /* Parity DRAM Error Exception */ 202 #define MCCHIPV_ZS0 0xc /* First ZS85230 Interrupt Vector */ 203 #define MCCHIPV_ZS1 0xc /* Second ZS85230 Interrupt Vector */ 204 #define MCCHIPV_ABORT 0xe /* Abort Switch */ 205 206 /* 207 * How to identify the PCCchip2 from an MCchip 208 */ 209 #define PCCTWO_CHIP_ID_PCC2 0x20 210 #define PCCTWO_CHIP_ID_MCCHIP 0x84 211 212 213 /* 214 * Bit Values for the General Control Register (PCC2REG_GENERAL_CONTROL) 215 */ 216 #define PCCTWO_GEN_CTRL_FAST (1u<<0) /* BBRAM Speed Control */ 217 #define PCCTWO_GEN_CTRL_MIEN (1u<<1) /* Master Interrupt Enable */ 218 #define PCCTWO_GEN_CTRL_C040 (1u<<2) /* Set when CPU is mc68k family */ 219 #define PCCTWO_GEN_CTRL_DR0 (1u<<3) /* Download ROM at 0 (mvme166 only) */ 220 221 222 /* 223 * Calculate the Prescaler Adjust value for a given 224 * value of BCLK in MHz. (PCC2REG_PRESCALE_ADJUST) 225 */ 226 #define PCCTWO_PRES_ADJ(mhz) (256 - (mhz)) 227 228 229 /* 230 * Calculate the Tick Timer Compare register value for 231 * a given number of micro-seconds. With the PCCChip2, 232 * this is simple since the Tick Counters already have 233 * a 1uS period. (PCC2REG_TIMER[12]_COMPARE) 234 */ 235 #define PCCTWO_TIMERFREQ 1000000 236 #define PCCTWO_US2LIM(us) (us) 237 #define PCCTWO_LIM2US(lim) (lim) 238 239 /* 240 * The Tick Timer Control Registers (PCC2REG_TIMER[12]_CONTROL) 241 */ 242 #define PCCTWO_TT_CTRL_CEN (1u<<0) /* Counter Enable */ 243 #define PCCTWO_TT_CTRL_COC (1u<<1) /* Clear On Compare */ 244 #define PCCTWO_TT_CTRL_COVF (1u<<2) /* Clear Overflow Counter */ 245 #define PCCTWO_TT_CTRL_OVF(r) ((r)>>4)/* Value of the Overflow Counter */ 246 247 248 /* 249 * All the Interrupt Control Registers (PCC2REG_*_ICSR) on the PCCChip2 250 * mostly share the same basic layout. These are defined as follows: 251 */ 252 #define PCCTWO_ICR_LEVEL_MASK 0x7 /* Mask for the interrupt level */ 253 #define PCCTWO_ICR_ICLR (1u<<3) /* Clear Int. (edge-sensitive mode) */ 254 #define PCCTWO_ICR_AVEC (1u<<3) /* Enable Auto-Vector Mode */ 255 #define PCCTWO_ICR_IEN (1u<<4) /* Interrupt Enable */ 256 #define PCCTWO_ICR_INT (1u<<5) /* Interrupt Active */ 257 #define PCCTWO_ICR_LEVEL (0u<<6) /* Level Triggered */ 258 #define PCCTWO_ICR_EDGE (1u<<6) /* Edge Triggered */ 259 #define PCCTWO_ICR_RISE_HIGH (0u<<7) /* Polarity: Rising Edge or Hi Level */ 260 #define PCCTWO_ICR_FALL_LOW (1u<<7) /* Polarity: Falling Edge or Lo Level */ 261 #define PCCTWO_ICR_SC_RD(r) ((r)>>6)/* Get Snoop Control Bits */ 262 #define PCCTWO_ICR_SC_WR(r) ((r)<<6)/* Write Snoop Control Bits */ 263 264 265 266 /* 267 * Most of the Error Status Registers (PCC2REG_*_ERR_STATUS) mostly 268 * follow the same layout. These error registers are used when a 269 * device (eg. SCC, LANC) is mastering the PCCChip2's local bus (for 270 * example, performing a DMA) and some error occurs. The bits are 271 * defined as follows: 272 */ 273 #define PCCTWO_ERR_SR_SCLR (1u<<0) /* Clear Error Status */ 274 #define PCCTWO_ERR_SR_LTO (1u<<1) /* Local Bus Timeout */ 275 #define PCCTWO_ERR_SR_EXT (1u<<2) /* External (VMEbus) Error */ 276 #define PCCTWO_ERR_SR_PRTY (1u<<3) /* DRAM Parity Error */ 277 #define PCCTWO_ERR_SR_RTRY (1u<<4) /* Retry Required */ 278 #define PCCTWO_ERR_SR_MASK 0x0Eu 279 280 281 /* 282 * General Purpose Input/Output Pin Control Register 283 * (PCC2REG_GPIO_CONTROL) 284 */ 285 #define PCCTWO_GPIO_CTRL_GPO (1u<<0) /* Controls the GP Output Pin */ 286 #define PCCTWO_GPIO_CTRL_GPOE (1u<<1) /* General Purpose Output Enable */ 287 #define PCCTWO_GPIO_CTRL_GPI (1u<<3) /* The current state of the GP Input */ 288 289 290 /* 291 * Printer Input Status Register (PCC2REG_PRT_INPUT_STATUS) 292 */ 293 #define PCCTWO_PRT_IN_SR_BSY (1u<<0) /* State of printer's BSY Input */ 294 #define PCCTWO_PRT_IN_SR_PE (1u<<1) /* State of printer's PE Input */ 295 #define PCCTWO_PRT_IN_SR_SEL (1u<<2) /* State of printer's SELECT Input */ 296 #define PCCTWO_PRT_IN_SR_FLT (1u<<3) /* State of printer's FAULT Input */ 297 #define PCCTWO_PRT_IN_SR_ACK (1u<<4) /* State of printer's ACK Input */ 298 #define PCCTWO_PRT_IN_SR_PINT (1u<<7) /* Printer Interrupt Status */ 299 300 301 /* 302 * Printer Port Control Register (PCC2REG_PRT_CONTROL) 303 */ 304 #define PCCTWO_PRT_CTRL_MAN (1u<<0) /* Manual Strobe Control */ 305 #define PCCTWO_PRT_CTRL_FAST (1u<<1) /* Fast Auto Strobe */ 306 #define PCCTWO_PRT_CTRL_STB (1u<<2) /* Strobe Pin, in manual control mode */ 307 #define PCCTWO_PRT_CTRL_INP (1u<<3) /* Printer Input Prime */ 308 #define PCCTWO_PRT_CTRL_DOEN (1u<<4) /* Printer Data Output Enable */ 309 310 #endif /* _MVME_PCCTWOREG_H */ 311