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Searched defs:Order (Results 1 – 25 of 76) sorted by relevance

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/freebsd-14-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDAllocationOrder.h32 ArrayRef<MCPhysReg> Order; variable
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder()
HDRegAllocGreedy.cpp398 AllocationOrder &Order, in tryAssign()
532 const AllocationOrder &Order, in getOrderLimit()
578 AllocationOrder &Order, in tryEvict()
869 const AllocationOrder &Order) { in calcGlobalSplitCost()
1061 AllocationOrder &Order, in tryRegionSplit()
1095 AllocationOrder &Order, in calculateRegionSplitCostAroundReg()
1172 AllocationOrder &Order, in calculateRegionSplitCost()
1234 AllocationOrder &Order) { in trySplitAroundHintReg()
1294 AllocationOrder &Order, in tryBlockSplit()
1415 AllocationOrder &Order, in tryInstructionSplit()
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HDAllocationOrder.cpp34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local
HDLocalStackSlotAllocation.cpp59 unsigned Order; member in __anonc19773f70111::FrameRef
323 unsigned Order = 0; in insertFrameReferenceRegisters() local
HDRegAllocBasic.cpp261 auto Order = in selectOrSplit() local
HDBreakFalseDeps.cpp156 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef() local
HDRegAllocEvictionAdvisor.cpp277 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
HDTargetRegisterInfo.cpp248 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC() local
420 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
HDCriticalAntiDepBreaker.cpp399 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister() local
HDMLRegAllocEvictAdvisor.cpp667 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
1088 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidatePosition()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
HDSDNodeDbgValue.h149 unsigned Order; variable
245 unsigned Order; variable
HDScheduleDAGSDNodes.cpp740 DenseMap<SDValue, Register> &VRBaseMap, unsigned Order) { in ProcessSDDbgValues()
788 unsigned Order = N->getIROrder(); in ProcessSourceNode() local
992 unsigned Order = Orders[i].first; in EmitSchedule() local
1038 unsigned Order = InstrOrder.first; in EmitSchedule() local
HDSelectionDAGDumper.cpp912 if (unsigned Order = getIROrder()) in print_details() local
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Support/
HDDynamicLibrary.cpp81 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup()
96 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup()
/freebsd-14-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDRegisterClassInfo.h36 std::unique_ptr<MCPhysReg[]> Order; member
HDScheduleDAG.h56 Order ///< Any other ordering dependency. enumerator
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
HDSystemZRegisterInfo.cpp57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints()
75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
/freebsd-14-stable/contrib/llvm-project/llvm/utils/TableGen/Common/
HDCodeGenRegisters.h569 unsigned Order = 0; // Cache the sort key. member
803 unsigned getRegSetIDAt(unsigned Order) const { in getRegSetIDAt()
807 const RegUnitSet &getRegSetAt(unsigned Order) const { in getRegSetAt()
/freebsd-14-stable/contrib/llvm-project/llvm/include/llvm/Frontend/OpenMP/
HDOMPIRBuilder.h246 explicit OffloadEntryInfo(OffloadingEntryInfoKinds Kind, unsigned Order, in OffloadEntryInfo()
272 unsigned Order = ~0u; variable
302 explicit OffloadEntryInfoTargetRegion(unsigned Order, Constant *Addr, in OffloadEntryInfoTargetRegion()
390 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, in OffloadEntryInfoDeviceGlobalVar()
393 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, Constant *Addr, in OffloadEntryInfoDeviceGlobalVar()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPULowerBufferFatPointers.cpp1032 void SplitPtrStructs::insertPreMemOpFence(AtomicOrdering Order, in insertPreMemOpFence()
1045 void SplitPtrStructs::insertPostMemOpFence(AtomicOrdering Order, in insertPostMemOpFence()
1060 AtomicOrdering Order, bool IsVolatile, in handleMemoryInst()
1215 AtomicOrdering Order = AI.getMergedOrdering(); in visitAtomicCmpXchgInst() local
HDAMDGPUInsertDelayAlu.cpp247 SmallVector<const_iterator, 8> Order; in dump() local
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
HDCodeLayout.cpp1001 std::vector<uint64_t> Order; in concatChains() local
1368 std::vector<uint64_t> Order; in concatChains() local
1428 double codelayout::calcExtTspScore(ArrayRef<uint64_t> Order, in calcExtTspScore()
1454 std::vector<uint64_t> Order(NodeSizes.size()); in calcExtTspScore() local
/freebsd-14-stable/contrib/llvm-project/llvm/utils/TableGen/
HDRegisterInfoEmitter.cpp1009 ArrayRef<Record *> Order = RC.getOrder(); in runMCDesc() local
1045 ArrayRef<Record *> Order = RC.getOrder(); in runMCDesc() local
1211 ArrayRef<Record *> Order = RC.getOrder(); in runTargetDesc() local
/freebsd-14-stable/contrib/llvm-project/clang/lib/CodeGen/
HDCGAtomic.cpp528 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp()
762 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp()
855 llvm::Value *Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr() local
/freebsd-14-stable/contrib/llvm-project/clang/lib/Format/
HDQualifierAlignmentFixer.cpp582 const std::vector<std::string> &Order, std::vector<std::string> &LeftOrder, in prepareLeftRightOrderingForQualifierAlignmentFixer()

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