| /freebsd-12-stable/contrib/llvm-project/llvm/tools/llvm-tapi-diff/ |
| D | DiffEngine.cpp | 24 StringRef setOrderIndicator(InterfaceInputOrder Order) { in setOrderIndicator()
121 InterfaceInputOrder Order) { in addDiffForTargSlice()
140 std::string Name, InterfaceInputOrder Order) { in getSingleAttrDiff()
153 std::string Name, InterfaceInputOrder Order) { in getSingleAttrDiff()
164 std::string Name, InterfaceInputOrder Order) { in getSingleAttrDiff()
189 const T &Val, InterfaceInputOrder Order) { in diffAttribute()
194 InterfaceInputOrder Order) { in getSingleIF()
235 DiffOutput &Result, InterfaceInputOrder Order) { in findAndAddDiff()
254 DiffOutput &Result, InterfaceInputOrder Order) { in findAndAddDiff()
267 DiffOutput &Result, InterfaceInputOrder Order) { in findAndAddDiff()
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| D | DiffEngine.h | 65 DiffScalarVal(InterfaceInputOrder Order, T Val) in DiffScalarVal()
84 SymScalar(InterfaceInputOrder Order, const MachO::Symbol *Sym) in SymScalar()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | AllocationOrder.h | 32 ArrayRef<MCPhysReg> Order; variable
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder()
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| D | RegAllocGreedy.cpp | 819 AllocationOrder &Order, in tryAssign()
873 auto Order = in canReassign() local
1086 MCRegister RAGreedy::getCheapestEvicteeWeight(const AllocationOrder &Order, in getCheapestEvicteeWeight()
1169 MCRegister RAGreedy::tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, in tryEvict()
1544 const AllocationOrder &Order) { in splitCanCauseEvictionChain()
1603 const AllocationOrder &Order) { in splitCanCauseLocalSpill()
1624 const AllocationOrder &Order, in calcGlobalSplitCost()
1856 AllocationOrder &Order, in tryRegionSplit()
1900 AllocationOrder &Order, in calculateRegionSplitCost()
2046 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryBlockSplit()
[all …]
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| D | AllocationOrder.cpp | 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local
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| D | LocalStackSlotAllocation.cpp | 59 unsigned Order; member in __anon7fcaf9750111::FrameRef
302 unsigned Order = 0; in insertFrameReferenceRegisters() local
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| D | BreakFalseDeps.cpp | 153 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef() local
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| D | RegAllocBasic.cpp | 269 auto Order = in selectOrSplit() local
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| D | TargetRegisterInfo.cpp | 250 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC() local
422 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
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| D | CriticalAntiDepBreaker.cpp | 402 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister() local
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| D | AtomicExpandPass.cpp | 327 bool AtomicExpand::bracketInstWithFences(Instruction *I, AtomicOrdering Order) { in bracketInstWithFences()
440 AtomicOrdering Order = LI->getOrdering(); in expandAtomicLoadToCmpXchg() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Support/ |
| D | DynamicLibrary.cpp | 74 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup()
89 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SDNodeDbgValue.h | 148 unsigned Order; variable
244 unsigned Order; variable
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| D | ScheduleDAGSDNodes.cpp | 738 DenseMap<SDValue, Register> &VRBaseMap, unsigned Order) { in ProcessSDDbgValues()
786 unsigned Order = N->getIROrder(); in ProcessSourceNode() local
979 unsigned Order = Orders[i].first; in EmitSchedule() local
1025 unsigned Order = InstrOrder.first; in EmitSchedule() local
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| D | SelectionDAGDumper.cpp | 820 if (unsigned Order = getIROrder()) in print_details() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 37 std::unique_ptr<MCPhysReg[]> Order; member
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| D | ScheduleDAG.h | 56 Order ///< Any other ordering dependency. enumerator
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| /freebsd-12-stable/contrib/llvm-project/clang/lib/CodeGen/ |
| D | CGOpenMPRuntime.h | 552 explicit OffloadEntryInfo(OffloadingEntryInfoKinds Kind, unsigned Order, in OffloadEntryInfo()
580 unsigned Order = ~0u; variable
613 explicit OffloadEntryInfoTargetRegion(unsigned Order, in OffloadEntryInfoTargetRegion()
674 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, in OffloadEntryInfoDeviceGlobalVar()
678 unsigned Order, llvm::Constant *Addr, CharUnits VarSize, in OffloadEntryInfoDeviceGlobalVar()
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| D | CGAtomic.cpp | 515 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp()
705 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp()
829 llvm::Value *Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints()
75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
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| /freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 519 unsigned Order = 0; // Cache the sort key. member
746 unsigned getRegSetIDAt(unsigned Order) const { in getRegSetIDAt()
750 const RegUnitSet &getRegSetAt(unsigned Order) const { in getRegSetAt()
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| D | RegisterInfoEmitter.cpp | 1042 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc() local
1228 ArrayRef<Record*> Order = RC.getOrder(); in runTargetDesc() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/IR/ |
| D | BasicBlock.cpp | 500 unsigned Order = 0; in renumberInstructions() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 911 ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 324 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
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