1 /*- 2 * Copyright (c) 2003-2012 Broadcom Corporation 3 * All Rights Reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: stable/10/sys/dev/iicbus/iicoc.h 233539 2012-03-27 10:44:32Z jchandra $ 29 */ 30 31 #ifndef __OPENCORE_I2C_H__ 32 #define __OPENCORE_I2C_H__ 33 34 /* I2C specific registers */ 35 #define OC_I2C_PRESCALE_LO_REG 0x00 36 #define OC_I2C_PRESCALE_HI_REG 0x01 37 #define OC_I2C_CTRL_REG 0x02 38 #define OC_I2C_TRANSMIT_REG 0x03 /* tx and rx - same reg */ 39 #define OC_I2C_RECV_REG 0x03 /* tx and rx - same reg */ 40 #define OC_I2C_DATA_REG 0x03 /* tx and rx - same reg */ 41 #define OC_I2C_CMD_REG 0x04 /* cmd and status - same reg */ 42 #define OC_I2C_STATUS_REG 0x04 /* cmd and status - same reg */ 43 44 #define XLP_I2C_CLKFREQ 133333333 /* XLP 133 MHz IO clock */ 45 #define XLP_I2C_FREQ 100000 /* default 100kHz */ 46 #define I2C_TIMEOUT 500000 47 48 /* 49 * These defines pertain to the OpenCores 50 * I2C Master Host Controller used in XLP 51 */ 52 53 #define OC_PRESCALER_LO 0 54 #define OC_PRESCALER_HI 1 55 56 #define OC_CONTROL 2 57 #define OC_CONTROL_EN 0x80 58 #define OC_CONTROL_IEN 0x40 59 60 #define OC_DATA 3 /* Data TX & RX Reg */ 61 62 #define OC_COMMAND 4 63 #define OC_COMMAND_START 0x90 64 #define OC_COMMAND_STOP 0x40 65 #define OC_COMMAND_READ 0x20 66 #define OC_COMMAND_WRITE 0x10 67 #define OC_COMMAND_RDACK 0x20 68 #define OC_COMMAND_RDNACK 0x28 69 #define OC_COMMAND_IACK 0x01 /* Not used */ 70 71 #define OC_STATUS 4 /* Same as 'command' */ 72 #define OC_STATUS_NACK 0x80 /* Did not get an ACK */ 73 #define OC_STATUS_BUSY 0x40 74 #define OC_STATUS_AL 0x20 /* Arbitration Lost */ 75 #define OC_STATUS_TIP 0x02 /* Transfer in Progress */ 76 #define OC_STATUS_IF 0x01 /* Intr. Pending Flag */ 77 78 #endif 79