1 /* $NetBSD: ncr53c9xreg.h,v 1.16 2009/09/07 13:31:44 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Peter Galbavy. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* $FreeBSD$ */ 33 34 #ifndef _NCR53C9XREG_H_ 35 #define _NCR53C9XREG_H_ 36 37 /* 38 * Register addresses, relative to some base address 39 */ 40 41 #define NCR_TCL 0x00 /* RW - Transfer Count Low */ 42 #define NCR_TCM 0x01 /* RW - Transfer Count Mid */ 43 #define NCR_TCH 0x0e /* RW - Transfer Count High */ 44 /* NOT on 53C90 */ 45 46 #define NCR_FIFO 0x02 /* RW - FIFO data */ 47 48 #define NCR_CMD 0x03 /* RW - Command (2 deep) */ 49 #define NCRCMD_DMA 0x80 /* DMA Bit */ 50 #define NCRCMD_NOP 0x00 /* No Operation */ 51 #define NCRCMD_FLUSH 0x01 /* Flush FIFO */ 52 #define NCRCMD_RSTCHIP 0x02 /* Reset Chip */ 53 #define NCRCMD_RSTSCSI 0x03 /* Reset SCSI Bus */ 54 #define NCRCMD_RESEL 0x40 /* Reselect Sequence */ 55 #define NCRCMD_SELNATN 0x41 /* Select without ATN */ 56 #define NCRCMD_SELATN 0x42 /* Select with ATN */ 57 #define NCRCMD_SELATNS 0x43 /* Select with ATN & Stop */ 58 #define NCRCMD_ENSEL 0x44 /* Enable (Re)Selection */ 59 #define NCRCMD_DISSEL 0x45 /* Disable (Re)Selection */ 60 #define NCRCMD_SELATN3 0x46 /* Select with ATN3 */ 61 #define NCRCMD_RESEL3 0x47 /* Reselect3 Sequence */ 62 #define NCRCMD_SNDMSG 0x20 /* Send Message */ 63 #define NCRCMD_SNDSTAT 0x21 /* Send Status */ 64 #define NCRCMD_SNDDATA 0x22 /* Send Data */ 65 #define NCRCMD_DISCSEQ 0x23 /* Disconnect Sequence */ 66 #define NCRCMD_TERMSEQ 0x24 /* Terminate Sequence */ 67 #define NCRCMD_TCCS 0x25 /* Target Command Comp Seq */ 68 #define NCRCMD_DISC 0x27 /* Disconnect */ 69 #define NCRCMD_RECMSG 0x28 /* Receive Message */ 70 #define NCRCMD_RECCMD 0x29 /* Receive Command */ 71 #define NCRCMD_RECDATA 0x2a /* Receive Data */ 72 #define NCRCMD_RECCSEQ 0x2b /* Receive Command Sequence*/ 73 #define NCRCMD_ABORT 0x04 /* Target Abort DMA */ 74 #define NCRCMD_TRANS 0x10 /* Transfer Information */ 75 #define NCRCMD_ICCS 0x11 /* Initiator Cmd Comp Seq */ 76 #define NCRCMD_MSGOK 0x12 /* Message Accepted */ 77 #define NCRCMD_TRPAD 0x18 /* Transfer Pad */ 78 #define NCRCMD_SETATN 0x1a /* Set ATN */ 79 #define NCRCMD_RSTATN 0x1b /* Reset ATN */ 80 81 #define NCR_STAT 0x04 /* RO - Status */ 82 #define NCRSTAT_INT 0x80 /* Interrupt */ 83 #define NCRSTAT_GE 0x40 /* Gross Error */ 84 #define NCRSTAT_PE 0x20 /* Parity Error */ 85 #define NCRSTAT_TC 0x10 /* Terminal Count */ 86 #define NCRSTAT_VGC 0x08 /* Valid Group Code */ 87 #define NCRSTAT_PHASE 0x07 /* Phase bits */ 88 89 #define NCR_SELID 0x04 /* WO - Select/Reselect Bus ID */ 90 #define NCR_BUSID_HMEXC32 0x40 /* HME xfer counter is 32bit */ 91 #define NCR_BUSID_HMEENCID 0x10 /* HME encode reselection ID */ 92 93 #define NCR_INTR 0x05 /* RO - Interrupt */ 94 #define NCRINTR_SBR 0x80 /* SCSI Bus Reset */ 95 #define NCRINTR_ILL 0x40 /* Illegal Command */ 96 #define NCRINTR_DIS 0x20 /* Disconnect */ 97 #define NCRINTR_BS 0x10 /* Bus Service */ 98 #define NCRINTR_FC 0x08 /* Function Complete */ 99 #define NCRINTR_RESEL 0x04 /* Reselected */ 100 #define NCRINTR_SELATN 0x02 /* Select with ATN */ 101 #define NCRINTR_SEL 0x01 /* Selected */ 102 103 #define NCR_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */ 104 105 #define NCR_STEP 0x06 /* RO - Sequence Step */ 106 #define NCRSTEP_MASK 0x07 /* the last 3 bits */ 107 #define NCRSTEP_DONE 0x04 /* command went out */ 108 109 #define NCR_SYNCTP 0x06 /* WO - Synch Transfer Period */ 110 /* Default 5 (53C9X) */ 111 112 #define NCR_FFLAG 0x07 /* RO - FIFO Flags */ 113 #define NCRFIFO_SS 0xe0 /* Sequence Step (Dup) */ 114 #define NCRFIFO_FF 0x1f /* Bytes in FIFO */ 115 116 #define NCR_SYNCOFF 0x07 /* WO - Synch Offset */ 117 /* 0 = ASYNC */ 118 /* 1 - 15 = SYNC bytes */ 119 120 #define NCR_CFG1 0x08 /* RW - Configuration #1 */ 121 #define NCRCFG1_SLOW 0x80 /* Slow Cable Mode */ 122 #define NCRCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */ 123 #define NCRCFG1_PTEST 0x20 /* Parity Test Mod */ 124 #define NCRCFG1_PARENB 0x10 /* Enable Parity Check */ 125 #define NCRCFG1_CTEST 0x08 /* Enable Chip Test */ 126 #define NCRCFG1_BUSID 0x07 /* Bus ID */ 127 128 #define NCR_CCF 0x09 /* WO - Clock Conversion Factor */ 129 /* 0 = 35.01 - 40MHz */ 130 /* NEVER SET TO 1 */ 131 /* 2 = 10MHz */ 132 /* 3 = 10.01 - 15MHz */ 133 /* 4 = 15.01 - 20MHz */ 134 /* 5 = 20.01 - 25MHz */ 135 /* 6 = 25.01 - 30MHz */ 136 /* 7 = 30.01 - 35MHz */ 137 138 #define NCR_TEST 0x0a /* WO - Test (Chip Test Only) */ 139 140 #define NCR_CFG2 0x0b /* RW - Configuration #2 */ 141 #define NCRCFG2_RSVD 0xa0 /* reserved */ 142 #define NCRCFG2_FE 0x40 /* Features Enable */ 143 #define NCRCFG2_DREQ 0x10 /* DREQ High Impedance */ 144 #define NCRCFG2_SCSI2 0x08 /* SCSI-2 Enable */ 145 #define NCRCFG2_BPA 0x04 /* Target Bad Parity Abort */ 146 #define NCRCFG2_RPE 0x02 /* Register Parity Error */ 147 #define NCRCFG2_DPE 0x01 /* DMA Parity Error */ 148 149 #define NCRCFG2_HMEFE 0x10 /* HME feature enable */ 150 #define NCRCFG2_HME32 0x80 /* HME 32 extended */ 151 152 /* Config #3 only on 53C9X */ 153 #define NCR_CFG3 0x0c /* RW - Configuration #3 */ 154 #define NCRCFG3_RSVD 0xe0 /* reserved */ 155 #define NCRCFG3_IDM 0x10 /* ID Message Res Check */ 156 #define NCRCFG3_QTE 0x08 /* Queue Tag Enable */ 157 #define NCRCFG3_CDB 0x04 /* CDB 10-bytes OK */ 158 #define NCRCFG3_FSCSI 0x02 /* Fast SCSI */ 159 #define NCRCFG3_FCLK 0x01 /* Fast Clock (>25MHz) */ 160 161 /* 162 * For some unknown reason, the ESP406/FAS408 looks like every 163 * other ncr53c9x, except for configuration #3 register. At any 164 * rate, if you're dealing with these chips, you need to use these 165 * defines instead. 166 */ 167 168 /* Config #3 different on ESP406/FAS408 */ 169 #define NCR_ESPCFG3 0x0c /* RW - Configuration #3 */ 170 #define NCRESPCFG3_IDM 0x80 /* ID Message Res Check */ 171 #define NCRESPCFG3_QTE 0x40 /* Queue Tag Enable */ 172 #define NCRESPCFG3_CDB 0x20 /* CDB 10-bytes OK */ 173 #define NCRESPCFG3_FSCSI 0x10 /* Fast SCSI */ 174 #define NCRESPCFG3_SRESB 0x08 /* Save Residual Byte */ 175 #define NCRESPCFG3_FCLK 0x04 /* Fast Clock (>25MHz) */ 176 #define NCRESPCFG3_ADMA 0x02 /* Alternate DMA Mode */ 177 #define NCRESPCFG3_T8M 0x01 /* Threshold 8 Mode */ 178 179 /* Config #3 also different on NCR53CF9x/FAS100A/FAS216/FAS236 */ 180 #define NCR_F9XCFG3 0x0c /* RW - Configuration #3 */ 181 #define NCRF9XCFG3_IDM 0x80 /* ID Message Res Check */ 182 #define NCRF9XCFG3_QTE 0x40 /* Queue Tag Enable */ 183 #define NCRF9XCFG3_CDB 0x20 /* CDB 10-bytes OK */ 184 #define NCRF9XCFG3_FSCSI 0x10 /* Fast SCSI */ 185 #define NCRF9XCFG3_FCLK 0x08 /* Fast Clock (>25MHz) */ 186 #define NCRF9XCFG3_SRESB 0x04 /* Save Residual Byte */ 187 #define NCRF9XCFG3_ADMA 0x02 /* Alternate DMA Mode */ 188 #define NCRF9XCFG3_T8M 0x01 /* Threshold 8 Mode */ 189 190 /* Config #3 on FAS366 */ 191 #define NCRFASCFG3_OBAUTO 0x80 /* auto push odd-byte to DMA */ 192 #define NCRFASCFG3_EWIDE 0x40 /* Enable Wide-SCSI */ 193 #define NCRFASCFG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID */ 194 #define NCRFASCFG3_IDRESCHK 0x10 /* ID message checking */ 195 #define NCRFASCFG3_QUENB 0x08 /* 3-byte msg support */ 196 #define NCRFASCFG3_CDB10 0x04 /* group 2 scsi-2 support */ 197 #define NCRFASCFG3_FASTSCSI 0x02 /* 10 MB/S fast scsi mode */ 198 #define NCRFASCFG3_FASTCLK 0x01 /* fast clock mode */ 199 200 /* Config #4 only on ESP406/FAS408 */ 201 #define NCR_CFG4 0x0d /* RW - Configuration #4 */ 202 #define NCRCFG4_CRS1 0x80 /* Select register set #1 */ 203 #define NCRCFG4_RSVD 0x7b /* reserved */ 204 #define NCRCFG4_ACTNEG 0x04 /* Active negation */ 205 206 /* 207 The following registers are only on the ESP406/FAS408. The 208 documentation refers to them as "Control Register Set #1". 209 These are the registers that are visible when bit 7 of 210 register 0x0d is set. This bit is common to both register sets. 211 */ 212 213 #define NCR_JMP 0x00 /* RO - Jumper Sense Register */ 214 #define NCRJMP_RSVD 0xc0 /* reserved */ 215 #define NCRJMP_ROMSZ 0x20 /* ROM Size 1=16K, 0=32K */ 216 #define NCRJMP_J4 0x10 /* Jumper #4 */ 217 #define NCRJMP_J3 0x08 /* Jumper #3 */ 218 #define NCRJMP_J2 0x04 /* Jumper #2 */ 219 #define NCRJMP_J1 0x02 /* Jumper #1 */ 220 #define NCRJMP_J0 0x01 /* Jumper #0 */ 221 222 #define NCR_PIOFIFO 0x04 /* WO - PIO FIFO, 4 bytes deep */ 223 224 #define NCR_PSTAT 0x08 /* RW - PIO Status Register */ 225 #define NCRPSTAT_PERR 0x80 /* PIO Error */ 226 #define NCRPSTAT_SIRQ 0x40 /* Active High of SCSI IRQ */ 227 #define NCRPSTAT_ATAI 0x20 /* ATA IRQ */ 228 #define NCRPSTAT_FEMPT 0x10 /* PIO FIFO Empty */ 229 #define NCRPSTAT_F13 0x08 /* PIO FIFO 1/3 */ 230 #define NCRPSTAT_F23 0x04 /* PIO FIFO 2/3 */ 231 #define NCRPSTAT_FFULL 0x02 /* PIO FIFO Full */ 232 #define NCRPSTAT_PIOM 0x01 /* PIO/DMA Mode */ 233 234 #define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */ 235 #define NCRPIOI_RSVD 0xe0 /* reserved */ 236 #define NCRPIOI_EMPTY 0x10 /* IRQ When Empty */ 237 #define NCRPIOI_13 0x08 /* IRQ When 1/3 */ 238 #define NCRPIOI_23 0x04 /* IRQ When 2/3 */ 239 #define NCRPIOI_FULL 0x02 /* IRQ When Full */ 240 #define NCRPIOI_FINV 0x01 /* Flag Invert */ 241 242 #define NCR_CFG5 0x0d /* RW - Configuration #5 */ 243 #define NCRCFG5_CRS1 0x80 /* Select Register Set #1 */ 244 #define NCRCFG5_SRAM 0x40 /* SRAM Memory Map */ 245 #define NCRCFG5_AADDR 0x20 /* Auto Address */ 246 #define NCRCFG5_PTRINC 0x10 /* Pointer Increment */ 247 #define NCRCFG5_LOWPWR 0x08 /* Low Power Mode */ 248 #define NCRCFG5_SINT 0x04 /* SCSI Interrupt Enable */ 249 #define NCRCFG5_INTP 0x02 /* INT Polarity */ 250 #define NCRCFG5_AINT 0x01 /* ATA Interrupt Enable */ 251 252 #define NCR_SIGNTR 0x0e /* RO - Signature */ 253 254 /* Am53c974 Config #3 */ 255 #define NCR_AMDCFG3 0x0c /* RW - Configuration #3 */ 256 #define NCRAMDCFG3_IDM 0x80 /* ID Message Res Check */ 257 #define NCRAMDCFG3_QTE 0x40 /* Queue Tag Enable */ 258 #define NCRAMDCFG3_CDB 0x20 /* CDB 10-bytes OK */ 259 #define NCRAMDCFG3_FSCSI 0x10 /* Fast SCSI */ 260 #define NCRAMDCFG3_FCLK 0x08 /* Fast Clock (40MHz) */ 261 #define NCRAMDCFG3_RSVD 0x07 /* Reserved */ 262 263 /* Am53c974 Config #4 */ 264 #define NCR_AMDCFG4 0x0d /* RW - Configuration #4 */ 265 #define NCRAMDCFG4_GE 0xc0 /* Glitch Eater */ 266 #define NCRAMDCFG4_GE12NS 0x00 /* Signal window 12ns */ 267 #define NCRAMDCFG4_GE25NS 0x80 /* Signal window 25ns */ 268 #define NCRAMDCFG4_GE35NS 0x40 /* Signal window 35ns */ 269 #define NCRAMDCFG4_GE0NS 0xc0 /* Signal window 0ns */ 270 #define NCRAMDCFG4_PWD 0x20 /* Reduced power feature */ 271 #define NCRAMDCFG4_RSVD 0x13 /* Reserved */ 272 #define NCRAMDCFG4_RAE 0x08 /* Active neg. REQ/ACK */ 273 #define NCRAMDCFG4_RADE 0x04 /* Active neg. REQ/ACK/DAT */ 274 275 /* 276 * FAS366 277 */ 278 #define NCR_RCL NCR_TCH /* Recommand counter low */ 279 #define NCR_RCH 0xf /* Recommand counter high */ 280 #define NCR_UID NCR_RCL /* fas366 part-uniq id */ 281 282 283 /* status register #2 definitions (read only) */ 284 #define NCR_STAT2 NCR_CCF 285 #define NCRFAS_STAT2_SEQCNT 0x01 /* Sequence counter bit 7-3 enabled */ 286 #define NCRFAS_STAT2_FLATCHED 0x02 /* FIFO flags register latched */ 287 #define NCRFAS_STAT2_CLATCHED 0x04 /* Xfer cntr & recommand ctr latched */ 288 #define NCRFAS_STAT2_CACTIVE 0x08 /* Command register is active */ 289 #define NCRFAS_STAT2_SCSI16 0x10 /* SCSI interface is wide */ 290 #define NCRFAS_STAT2_ISHUTTLE 0x20 /* FIFO Top register contains 1 byte */ 291 #define NCRFAS_STAT2_OSHUTTLE 0x40 /* next byte from FIFO is MSB */ 292 #define NCRFAS_STAT2_EMPTY 0x80 /* FIFO is empty */ 293 294 #endif /* _NCR53C9XREG_H_ */ 295