1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2009-2013, 2016 Chelsio, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33 #ifndef __IW_CXGB4_H__
34 #define __IW_CXGB4_H__
35
36 #include <linux/list.h>
37 #include <linux/spinlock.h>
38 #include <linux/idr.h>
39 #include <linux/completion.h>
40 #include <linux/sched.h>
41 #include <linux/pci.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/wait.h>
44 #include <linux/kref.h>
45 #include <linux/timer.h>
46 #include <linux/io.h>
47 #include <sys/vmem.h>
48
49 #include <asm/byteorder.h>
50
51 #include <netinet/in.h>
52 #include <netinet/toecore.h>
53
54 #include <rdma/ib_verbs.h>
55 #include <rdma/iw_cm.h>
56
57 #include "common/common.h"
58 #include "common/t4_msg.h"
59 #include "common/t4_regs.h"
60 #include "common/t4_tcb.h"
61 #include "t4_l2t.h"
62
63 #define DRV_NAME "iw_cxgbe"
64 #define MOD DRV_NAME ":"
65 #define KTR_IW_CXGBE KTR_SPARE3
66
67 extern int c4iw_debug;
68 extern int use_dsgl;
69 extern int inline_threshold;
70
71 #define PDBG(fmt, args...) \
72 do { \
73 if (c4iw_debug) \
74 printf(MOD fmt, ## args); \
75 } while (0)
76
77 #include "t4.h"
78
cplhdr(struct mbuf * m)79 static inline void *cplhdr(struct mbuf *m)
80 {
81 return mtod(m, void*);
82 }
83
84 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.pbl.start)
85 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start)
86
87 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
88 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
89 #define C4IW_MAX_PAGE_SIZE 0x8000000
90
91 struct c4iw_id_table {
92 u32 flags;
93 u32 start; /* logical minimal id */
94 u32 last; /* hint for find */
95 u32 max;
96 spinlock_t lock;
97 unsigned long *table;
98 };
99
100 struct c4iw_resource {
101 struct c4iw_id_table tpt_table;
102 struct c4iw_id_table qid_table;
103 struct c4iw_id_table pdid_table;
104 };
105
106 struct c4iw_qid_list {
107 struct list_head entry;
108 u32 qid;
109 };
110
111 struct c4iw_dev_ucontext {
112 struct list_head qpids;
113 struct list_head cqids;
114 struct mutex lock;
115 };
116
117 enum c4iw_rdev_flags {
118 T4_FATAL_ERROR = (1<<0),
119 T4_STATUS_PAGE_DISABLED = (1<<1),
120 };
121
122 struct c4iw_stat {
123 u64 total;
124 u64 cur;
125 u64 max;
126 u64 fail;
127 };
128
129 struct c4iw_stats {
130 struct mutex lock;
131 struct c4iw_stat qid;
132 struct c4iw_stat pd;
133 struct c4iw_stat stag;
134 struct c4iw_stat pbl;
135 struct c4iw_stat rqt;
136 };
137
138 struct c4iw_hw_queue {
139 int t4_eq_status_entries;
140 int t4_max_eq_size;
141 int t4_max_iq_size;
142 int t4_max_rq_size;
143 int t4_max_sq_size;
144 int t4_max_qp_depth;
145 int t4_max_cq_depth;
146 int t4_stat_len;
147 };
148
149 struct c4iw_rdev {
150 struct adapter *adap;
151 struct c4iw_resource resource;
152 unsigned long qpshift;
153 u32 qpmask;
154 unsigned long cqshift;
155 u32 cqmask;
156 struct c4iw_dev_ucontext uctx;
157 vmem_t *rqt_arena;
158 vmem_t *pbl_arena;
159 u32 flags;
160 struct c4iw_stats stats;
161 struct c4iw_hw_queue hw_queue;
162 struct t4_dev_status_page *status_page;
163 unsigned long bar2_pa;
164 void __iomem *bar2_kva;
165 unsigned int bar2_len;
166 struct workqueue_struct *free_workq;
167 };
168
c4iw_fatal_error(struct c4iw_rdev * rdev)169 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
170 {
171 return rdev->flags & T4_FATAL_ERROR;
172 }
173
c4iw_num_stags(struct c4iw_rdev * rdev)174 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
175 {
176 return (int)(rdev->adap->vres.stag.size >> 5);
177 }
178
t4_max_fr_depth(struct c4iw_rdev * rdev,bool use_dsgl)179 static inline int t4_max_fr_depth(struct c4iw_rdev *rdev, bool use_dsgl)
180 {
181 if (rdev->adap->params.ulptx_memwrite_dsgl && use_dsgl)
182 return rdev->adap->params.dev_512sgl_mr ? T4_MAX_FR_FW_DSGL_DEPTH : T4_MAX_FR_DSGL_DEPTH;
183 else
184 return T4_MAX_FR_IMMD_DEPTH;
185 }
186
187 #define C4IW_WR_TO (60*HZ)
188
189 struct c4iw_wr_wait {
190 int ret;
191 struct completion completion;
192 };
193
c4iw_init_wr_wait(struct c4iw_wr_wait * wr_waitp)194 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
195 {
196 wr_waitp->ret = 0;
197 init_completion(&wr_waitp->completion);
198 }
199
c4iw_wake_up(struct c4iw_wr_wait * wr_waitp,int ret)200 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
201 {
202 wr_waitp->ret = ret;
203 complete(&wr_waitp->completion);
204 }
205
206 static inline int
c4iw_wait_for_reply(struct c4iw_rdev * rdev,struct c4iw_wr_wait * wr_waitp,u32 hwtid,u32 qpid,struct socket * so,const char * func)207 c4iw_wait_for_reply(struct c4iw_rdev *rdev, struct c4iw_wr_wait *wr_waitp,
208 u32 hwtid, u32 qpid, struct socket *so, const char *func)
209 {
210 struct adapter *sc = rdev->adap;
211 unsigned to = C4IW_WR_TO;
212 int ret;
213 int timedout = 0;
214 struct timeval t1, t2;
215
216 if (c4iw_fatal_error(rdev)) {
217 wr_waitp->ret = -EIO;
218 goto out;
219 }
220
221 getmicrotime(&t1);
222 do {
223 /* If waiting for reply in rdma_init()/rdma_fini() threads, then
224 * check if there are any connection errors.
225 */
226 if (so && so->so_error) {
227 wr_waitp->ret = -ECONNRESET;
228 CTR5(KTR_IW_CXGBE, "%s - Connection ERROR %u for sock %p"
229 "tid %u qpid %u", func,
230 so->so_error, so, hwtid, qpid);
231 break;
232 }
233
234 ret = wait_for_completion_timeout(&wr_waitp->completion, to);
235 if (!ret) {
236 getmicrotime(&t2);
237 timevalsub(&t2, &t1);
238 printf("%s - Device %s not responding after %ld.%06ld "
239 "seconds - tid %u qpid %u\n", func,
240 device_get_nameunit(sc->dev), t2.tv_sec, t2.tv_usec,
241 hwtid, qpid);
242 if (c4iw_fatal_error(rdev)) {
243 wr_waitp->ret = -EIO;
244 break;
245 }
246 to = to << 2;
247 timedout = 1;
248 }
249 } while (!ret);
250
251 out:
252 if (timedout) {
253 getmicrotime(&t2);
254 timevalsub(&t2, &t1);
255 printf("%s - Device %s reply after %ld.%06ld seconds - "
256 "tid %u qpid %u\n", func, device_get_nameunit(sc->dev),
257 t2.tv_sec, t2.tv_usec, hwtid, qpid);
258 }
259 if (wr_waitp->ret)
260 CTR4(KTR_IW_CXGBE, "%p: FW reply %d tid %u qpid %u", sc,
261 wr_waitp->ret, hwtid, qpid);
262 return (wr_waitp->ret);
263 }
264
265 struct c4iw_dev {
266 struct ib_device ibdev;
267 struct pci_dev pdev;
268 struct c4iw_rdev rdev;
269 u32 device_cap_flags;
270 struct idr cqidr;
271 struct idr qpidr;
272 struct idr mmidr;
273 spinlock_t lock;
274 struct dentry *debugfs_root;
275 u32 avail_ird;
276 };
277
to_c4iw_dev(struct ib_device * ibdev)278 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
279 {
280 return container_of(ibdev, struct c4iw_dev, ibdev);
281 }
282
rdev_to_c4iw_dev(struct c4iw_rdev * rdev)283 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
284 {
285 return container_of(rdev, struct c4iw_dev, rdev);
286 }
287
get_chp(struct c4iw_dev * rhp,u32 cqid)288 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
289 {
290 return idr_find(&rhp->cqidr, cqid);
291 }
292
get_qhp(struct c4iw_dev * rhp,u32 qpid)293 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
294 {
295 return idr_find(&rhp->qpidr, qpid);
296 }
297
get_mhp(struct c4iw_dev * rhp,u32 mmid)298 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
299 {
300 return idr_find(&rhp->mmidr, mmid);
301 }
302
_insert_handle(struct c4iw_dev * rhp,struct idr * idr,void * handle,u32 id,int lock)303 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
304 void *handle, u32 id, int lock)
305 {
306 int ret;
307 int newid;
308
309 do {
310 if (!idr_pre_get(idr, lock ? GFP_KERNEL : GFP_ATOMIC))
311 return -ENOMEM;
312 if (lock)
313 spin_lock_irq(&rhp->lock);
314 ret = idr_get_new_above(idr, handle, id, &newid);
315 BUG_ON(!ret && newid != id);
316 if (lock)
317 spin_unlock_irq(&rhp->lock);
318 } while (ret == -EAGAIN);
319
320 return ret;
321 }
322
insert_handle(struct c4iw_dev * rhp,struct idr * idr,void * handle,u32 id)323 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
324 void *handle, u32 id)
325 {
326 return _insert_handle(rhp, idr, handle, id, 1);
327 }
328
insert_handle_nolock(struct c4iw_dev * rhp,struct idr * idr,void * handle,u32 id)329 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
330 void *handle, u32 id)
331 {
332 return _insert_handle(rhp, idr, handle, id, 0);
333 }
334
_remove_handle(struct c4iw_dev * rhp,struct idr * idr,u32 id,int lock)335 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
336 u32 id, int lock)
337 {
338 if (lock)
339 spin_lock_irq(&rhp->lock);
340 idr_remove(idr, id);
341 if (lock)
342 spin_unlock_irq(&rhp->lock);
343 }
344
remove_handle(struct c4iw_dev * rhp,struct idr * idr,u32 id)345 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
346 {
347 _remove_handle(rhp, idr, id, 1);
348 }
349
remove_handle_nolock(struct c4iw_dev * rhp,struct idr * idr,u32 id)350 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
351 struct idr *idr, u32 id)
352 {
353 _remove_handle(rhp, idr, id, 0);
354 }
355
356 extern int c4iw_max_read_depth;
357
cur_max_read_depth(struct c4iw_dev * dev)358 static inline int cur_max_read_depth(struct c4iw_dev *dev)
359 {
360 return min(dev->rdev.adap->params.max_ordird_qp, c4iw_max_read_depth);
361 }
362
363 struct c4iw_pd {
364 struct ib_pd ibpd;
365 u32 pdid;
366 struct c4iw_dev *rhp;
367 };
368
to_c4iw_pd(struct ib_pd * ibpd)369 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
370 {
371 return container_of(ibpd, struct c4iw_pd, ibpd);
372 }
373
374 struct tpt_attributes {
375 u64 len;
376 u64 va_fbo;
377 enum fw_ri_mem_perms perms;
378 u32 stag;
379 u32 pdid;
380 u32 qpid;
381 u32 pbl_addr;
382 u32 pbl_size;
383 u32 state:1;
384 u32 type:2;
385 u32 rsvd:1;
386 u32 remote_invaliate_disable:1;
387 u32 zbva:1;
388 u32 mw_bind_enable:1;
389 u32 page_size:5;
390 };
391
392 struct c4iw_mr {
393 struct ib_mr ibmr;
394 struct ib_umem *umem;
395 struct c4iw_dev *rhp;
396 u64 kva;
397 struct tpt_attributes attr;
398 u64 *mpl;
399 dma_addr_t mpl_addr;
400 u32 max_mpl_len;
401 u32 mpl_len;
402 };
403
to_c4iw_mr(struct ib_mr * ibmr)404 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
405 {
406 return container_of(ibmr, struct c4iw_mr, ibmr);
407 }
408
409 struct c4iw_mw {
410 struct ib_mw ibmw;
411 struct c4iw_dev *rhp;
412 u64 kva;
413 struct tpt_attributes attr;
414 };
415
to_c4iw_mw(struct ib_mw * ibmw)416 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
417 {
418 return container_of(ibmw, struct c4iw_mw, ibmw);
419 }
420
421 struct c4iw_cq {
422 struct ib_cq ibcq;
423 struct c4iw_dev *rhp;
424 struct t4_cq cq;
425 spinlock_t lock;
426 spinlock_t comp_handler_lock;
427 atomic_t refcnt;
428 wait_queue_head_t wait;
429 };
430
to_c4iw_cq(struct ib_cq * ibcq)431 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
432 {
433 return container_of(ibcq, struct c4iw_cq, ibcq);
434 }
435
436 struct c4iw_mpa_attributes {
437 u8 initiator;
438 u8 recv_marker_enabled;
439 u8 xmit_marker_enabled;
440 u8 crc_enabled;
441 u8 enhanced_rdma_conn;
442 u8 version;
443 u8 p2p_type;
444 };
445
446 struct c4iw_qp_attributes {
447 u32 scq;
448 u32 rcq;
449 u32 sq_num_entries;
450 u32 rq_num_entries;
451 u32 sq_max_sges;
452 u32 sq_max_sges_rdma_write;
453 u32 rq_max_sges;
454 u32 state;
455 u8 enable_rdma_read;
456 u8 enable_rdma_write;
457 u8 enable_bind;
458 u8 enable_mmid0_fastreg;
459 u32 max_ord;
460 u32 max_ird;
461 u32 pd;
462 u32 next_state;
463 char terminate_buffer[52];
464 u32 terminate_msg_len;
465 u8 is_terminate_local;
466 struct c4iw_mpa_attributes mpa_attr;
467 struct c4iw_ep *llp_stream_handle;
468 u8 layer_etype;
469 u8 ecode;
470 u16 sq_db_inc;
471 u16 rq_db_inc;
472 u8 send_term;
473 };
474
475 struct c4iw_qp {
476 struct ib_qp ibqp;
477 struct c4iw_dev *rhp;
478 struct c4iw_ep *ep;
479 struct c4iw_qp_attributes attr;
480 struct t4_wq wq;
481 spinlock_t lock;
482 struct mutex mutex;
483 struct kref kref;
484 wait_queue_head_t wait;
485 struct timer_list timer;
486 int sq_sig_all;
487 struct work_struct free_work;
488 struct c4iw_ucontext *ucontext;
489 };
490
to_c4iw_qp(struct ib_qp * ibqp)491 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
492 {
493 return container_of(ibqp, struct c4iw_qp, ibqp);
494 }
495
496 struct c4iw_ucontext {
497 struct ib_ucontext ibucontext;
498 struct c4iw_dev_ucontext uctx;
499 u32 key;
500 spinlock_t mmap_lock;
501 struct list_head mmaps;
502 struct kref kref;
503 };
504
to_c4iw_ucontext(struct ib_ucontext * c)505 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
506 {
507 return container_of(c, struct c4iw_ucontext, ibucontext);
508 }
509
510 void _c4iw_free_ucontext(struct kref *kref);
511
c4iw_put_ucontext(struct c4iw_ucontext * ucontext)512 static inline void c4iw_put_ucontext(struct c4iw_ucontext *ucontext)
513 {
514 kref_put(&ucontext->kref, _c4iw_free_ucontext);
515 }
c4iw_get_ucontext(struct c4iw_ucontext * ucontext)516 static inline void c4iw_get_ucontext(struct c4iw_ucontext *ucontext)
517 {
518 kref_get(&ucontext->kref);
519 }
520
521 struct c4iw_mm_entry {
522 struct list_head entry;
523 u64 addr;
524 u32 key;
525 unsigned len;
526 };
527
remove_mmap(struct c4iw_ucontext * ucontext,u32 key,unsigned len)528 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
529 u32 key, unsigned len)
530 {
531 struct list_head *pos, *nxt;
532 struct c4iw_mm_entry *mm;
533
534 spin_lock(&ucontext->mmap_lock);
535 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
536
537 mm = list_entry(pos, struct c4iw_mm_entry, entry);
538 if (mm->key == key && mm->len == len) {
539 list_del_init(&mm->entry);
540 spin_unlock(&ucontext->mmap_lock);
541 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d",
542 __func__, key, (unsigned long long) mm->addr,
543 mm->len);
544 return mm;
545 }
546 }
547 spin_unlock(&ucontext->mmap_lock);
548 return NULL;
549 }
550
insert_mmap(struct c4iw_ucontext * ucontext,struct c4iw_mm_entry * mm)551 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
552 struct c4iw_mm_entry *mm)
553 {
554 spin_lock(&ucontext->mmap_lock);
555 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", __func__, mm->key,
556 (unsigned long long) mm->addr, mm->len);
557 list_add_tail(&mm->entry, &ucontext->mmaps);
558 spin_unlock(&ucontext->mmap_lock);
559 }
560
561 enum c4iw_qp_attr_mask {
562 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
563 C4IW_QP_ATTR_SQ_DB = 1<<1,
564 C4IW_QP_ATTR_RQ_DB = 1<<2,
565 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
566 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
567 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
568 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
569 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
570 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
571 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
572 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
573 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
574 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
575 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
576 C4IW_QP_ATTR_MAX_ORD |
577 C4IW_QP_ATTR_MAX_IRD |
578 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
579 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
580 C4IW_QP_ATTR_MPA_ATTR |
581 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
582 };
583
584 int c4iw_modify_qp(struct c4iw_dev *rhp,
585 struct c4iw_qp *qhp,
586 enum c4iw_qp_attr_mask mask,
587 struct c4iw_qp_attributes *attrs,
588 int internal);
589
590 enum c4iw_qp_state {
591 C4IW_QP_STATE_IDLE,
592 C4IW_QP_STATE_RTS,
593 C4IW_QP_STATE_ERROR,
594 C4IW_QP_STATE_TERMINATE,
595 C4IW_QP_STATE_CLOSING,
596 C4IW_QP_STATE_TOT
597 };
598
599 /*
600 * IW_CXGBE event bits.
601 * These bits are used for handling all events for a particular 'ep' serially.
602 */
603 #define C4IW_EVENT_SOCKET 0x0001
604 #define C4IW_EVENT_TIMEOUT 0x0002
605 #define C4IW_EVENT_TERM 0x0004
606
c4iw_convert_state(enum ib_qp_state ib_state)607 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
608 {
609 switch (ib_state) {
610 case IB_QPS_RESET:
611 case IB_QPS_INIT:
612 return C4IW_QP_STATE_IDLE;
613 case IB_QPS_RTS:
614 return C4IW_QP_STATE_RTS;
615 case IB_QPS_SQD:
616 return C4IW_QP_STATE_CLOSING;
617 case IB_QPS_SQE:
618 return C4IW_QP_STATE_TERMINATE;
619 case IB_QPS_ERR:
620 return C4IW_QP_STATE_ERROR;
621 default:
622 return -1;
623 }
624 }
625
to_ib_qp_state(int c4iw_qp_state)626 static inline int to_ib_qp_state(int c4iw_qp_state)
627 {
628 switch (c4iw_qp_state) {
629 case C4IW_QP_STATE_IDLE:
630 return IB_QPS_INIT;
631 case C4IW_QP_STATE_RTS:
632 return IB_QPS_RTS;
633 case C4IW_QP_STATE_CLOSING:
634 return IB_QPS_SQD;
635 case C4IW_QP_STATE_TERMINATE:
636 return IB_QPS_SQE;
637 case C4IW_QP_STATE_ERROR:
638 return IB_QPS_ERR;
639 }
640 return IB_QPS_ERR;
641 }
642
643 #define C4IW_DRAIN_OPCODE FW_RI_SGE_EC_CR_RETURN
644
c4iw_ib_to_tpt_access(int a)645 static inline u32 c4iw_ib_to_tpt_access(int a)
646 {
647 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
648 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
649 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
650 FW_RI_MEM_ACCESS_LOCAL_READ;
651 }
652
c4iw_ib_to_tpt_bind_access(int acc)653 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
654 {
655 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
656 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
657 }
658
659 enum c4iw_mmid_state {
660 C4IW_STAG_STATE_VALID,
661 C4IW_STAG_STATE_INVALID
662 };
663
664 #define C4IW_NODE_DESC "iw_cxgbe Chelsio Communications"
665
666 #define MPA_KEY_REQ "MPA ID Req Frame"
667 #define MPA_KEY_REP "MPA ID Rep Frame"
668
669 #define MPA_MAX_PRIVATE_DATA 256
670 #define MPA_ENHANCED_RDMA_CONN 0x10
671 #define MPA_REJECT 0x20
672 #define MPA_CRC 0x40
673 #define MPA_MARKERS 0x80
674 #define MPA_FLAGS_MASK 0xE0
675
676 #define MPA_V2_PEER2PEER_MODEL 0x8000
677 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
678 #define MPA_V2_RDMA_WRITE_RTR 0x8000
679 #define MPA_V2_RDMA_READ_RTR 0x4000
680 #define MPA_V2_IRD_ORD_MASK 0x3FFF
681
682 #define c4iw_put_ep(ep) { \
683 CTR4(KTR_IW_CXGBE, "put_ep (%s:%u) ep %p, refcnt %d", \
684 __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
685 WARN_ON(atomic_read(&(ep)->kref.refcount) < 1); \
686 kref_put(&((ep)->kref), _c4iw_free_ep); \
687 }
688
689 #define c4iw_get_ep(ep) { \
690 CTR4(KTR_IW_CXGBE, "get_ep (%s:%u) ep %p, refcnt %d", \
691 __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
692 kref_get(&((ep)->kref)); \
693 }
694
695 void _c4iw_free_ep(struct kref *kref);
696
697 struct mpa_message {
698 u8 key[16];
699 u8 flags;
700 u8 revision;
701 __be16 private_data_size;
702 u8 private_data[0];
703 };
704
705 struct mpa_v2_conn_params {
706 __be16 ird;
707 __be16 ord;
708 };
709
710 struct terminate_message {
711 u8 layer_etype;
712 u8 ecode;
713 __be16 hdrct_rsvd;
714 u8 len_hdrs[0];
715 };
716
717 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
718
719 enum c4iw_layers_types {
720 LAYER_RDMAP = 0x00,
721 LAYER_DDP = 0x10,
722 LAYER_MPA = 0x20,
723 RDMAP_LOCAL_CATA = 0x00,
724 RDMAP_REMOTE_PROT = 0x01,
725 RDMAP_REMOTE_OP = 0x02,
726 DDP_LOCAL_CATA = 0x00,
727 DDP_TAGGED_ERR = 0x01,
728 DDP_UNTAGGED_ERR = 0x02,
729 DDP_LLP = 0x03
730 };
731
732 enum c4iw_rdma_ecodes {
733 RDMAP_INV_STAG = 0x00,
734 RDMAP_BASE_BOUNDS = 0x01,
735 RDMAP_ACC_VIOL = 0x02,
736 RDMAP_STAG_NOT_ASSOC = 0x03,
737 RDMAP_TO_WRAP = 0x04,
738 RDMAP_INV_VERS = 0x05,
739 RDMAP_INV_OPCODE = 0x06,
740 RDMAP_STREAM_CATA = 0x07,
741 RDMAP_GLOBAL_CATA = 0x08,
742 RDMAP_CANT_INV_STAG = 0x09,
743 RDMAP_UNSPECIFIED = 0xff
744 };
745
746 enum c4iw_ddp_ecodes {
747 DDPT_INV_STAG = 0x00,
748 DDPT_BASE_BOUNDS = 0x01,
749 DDPT_STAG_NOT_ASSOC = 0x02,
750 DDPT_TO_WRAP = 0x03,
751 DDPT_INV_VERS = 0x04,
752 DDPU_INV_QN = 0x01,
753 DDPU_INV_MSN_NOBUF = 0x02,
754 DDPU_INV_MSN_RANGE = 0x03,
755 DDPU_INV_MO = 0x04,
756 DDPU_MSG_TOOBIG = 0x05,
757 DDPU_INV_VERS = 0x06
758 };
759
760 enum c4iw_mpa_ecodes {
761 MPA_CRC_ERR = 0x02,
762 MPA_MARKER_ERR = 0x03,
763 MPA_LOCAL_CATA = 0x05,
764 MPA_INSUFF_IRD = 0x06,
765 MPA_NOMATCH_RTR = 0x07,
766 };
767
768 enum c4iw_ep_state {
769 IDLE = 0,
770 LISTEN,
771 CONNECTING,
772 MPA_REQ_WAIT,
773 MPA_REQ_SENT,
774 MPA_REQ_RCVD,
775 MPA_REP_SENT,
776 FPDU_MODE,
777 ABORTING,
778 CLOSING,
779 MORIBUND,
780 DEAD,
781 };
782
783 enum c4iw_ep_flags {
784 PEER_ABORT_IN_PROGRESS = 0,
785 ABORT_REQ_IN_PROGRESS = 1,
786 RELEASE_RESOURCES = 2,
787 CLOSE_SENT = 3,
788 TIMEOUT = 4,
789 QP_REFERENCED = 5,
790 STOP_MPA_TIMER = 7,
791 };
792
793 enum c4iw_ep_history {
794 ACT_OPEN_REQ = 0,
795 ACT_OFLD_CONN = 1,
796 ACT_OPEN_RPL = 2,
797 ACT_ESTAB = 3,
798 PASS_ACCEPT_REQ = 4,
799 PASS_ESTAB = 5,
800 ABORT_UPCALL = 6,
801 ESTAB_UPCALL = 7,
802 CLOSE_UPCALL = 8,
803 ULP_ACCEPT = 9,
804 ULP_REJECT = 10,
805 TIMEDOUT = 11,
806 PEER_ABORT = 12,
807 PEER_CLOSE = 13,
808 CONNREQ_UPCALL = 14,
809 ABORT_CONN = 15,
810 DISCONN_UPCALL = 16,
811 EP_DISC_CLOSE = 17,
812 EP_DISC_ABORT = 18,
813 CONN_RPL_UPCALL = 19,
814 ACT_RETRY_NOMEM = 20,
815 ACT_RETRY_INUSE = 21,
816 CLOSE_CON_RPL = 22,
817 EP_DISC_FAIL = 24,
818 QP_REFED = 25,
819 QP_DEREFED = 26,
820 CM_ID_REFED = 27,
821 CM_ID_DEREFED = 28
822 };
823
824 struct c4iw_ep_common {
825 TAILQ_ENTRY(c4iw_ep_common) entry; /* Work queue attachment */
826 struct iw_cm_id *cm_id;
827 struct c4iw_qp *qp;
828 struct c4iw_dev *dev;
829 enum c4iw_ep_state state;
830 struct kref kref;
831 struct mutex mutex;
832 struct sockaddr_storage local_addr;
833 struct sockaddr_storage remote_addr;
834 struct c4iw_wr_wait wr_wait;
835 unsigned long flags;
836 unsigned long history;
837 int rpl_err;
838 int rpl_done;
839 struct thread *thread;
840 struct socket *so;
841 int ep_events;
842 };
843
844 struct c4iw_listen_ep {
845 struct c4iw_ep_common com;
846 unsigned int stid;
847 int backlog;
848 struct list_head listen_ep_list; /* list of all listener ep's bound
849 to one port address */
850 };
851
852 struct c4iw_ep {
853 struct c4iw_ep_common com;
854 struct c4iw_listen_ep *parent_ep;
855 struct timer_list timer;
856 unsigned int atid;
857 u32 hwtid;
858 u32 snd_seq;
859 u32 rcv_seq;
860 struct l2t_entry *l2t;
861 struct dst_entry *dst;
862 struct c4iw_mpa_attributes mpa_attr;
863 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
864 unsigned int mpa_pkt_len;
865 u32 ird;
866 u32 ord;
867 u32 tx_chan;
868 u32 mtu;
869 u16 mss;
870 u16 plen;
871 u16 rss_qid;
872 u16 txq_idx;
873 u16 ctrlq_idx;
874 u8 tos;
875 u8 retry_with_mpa_v1;
876 u8 tried_with_mpa_v1;
877 };
878
to_ep(struct iw_cm_id * cm_id)879 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
880 {
881 return cm_id->provider_data;
882 }
883
to_listen_ep(struct iw_cm_id * cm_id)884 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
885 {
886 return cm_id->provider_data;
887 }
888
compute_wscale(int win)889 static inline int compute_wscale(int win)
890 {
891 int wscale = 0;
892
893 while (wscale < 14 && (65535<<wscale) < win)
894 wscale++;
895 return wscale;
896 }
897
898 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
899 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
900 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
901 u32 reserved, u32 flags);
902 void c4iw_id_table_free(struct c4iw_id_table *alloc);
903
904 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct mbuf *m);
905
906 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
907 struct l2t_entry *l2t);
908 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
909 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
910 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
911 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
912 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
913 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
914 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
915 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
916 void c4iw_destroy_resource(struct c4iw_resource *rscp);
917 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
918 int c4iw_register_device(struct c4iw_dev *dev);
919 void c4iw_unregister_device(struct c4iw_dev *dev);
920 int __init c4iw_cm_init(void);
921 void __exit c4iw_cm_term(void);
922 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
923 struct c4iw_dev_ucontext *uctx);
924 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
925 struct c4iw_dev_ucontext *uctx);
926 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
927 int c4iw_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
928 const struct ib_send_wr **bad_wr);
929 int c4iw_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
930 const struct ib_recv_wr **bad_wr);
931 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
932 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
933 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
934 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
935 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
936 void c4iw_qp_add_ref(struct ib_qp *qp);
937 void c4iw_qp_rem_ref(struct ib_qp *qp);
938 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
939 u32 max_num_sg);
940 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
941 int sg_nents, unsigned int *sg_offset);
942 int c4iw_dealloc_mw(struct ib_mw *mw);
943 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
944 struct ib_udata *udata);
945 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, u64
946 virt, int acc, struct ib_udata *udata);
947 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
948 int c4iw_dereg_mr(struct ib_mr *ib_mr);
949 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey);
950 int c4iw_destroy_cq(struct ib_cq *ib_cq);
951 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
952 const struct ib_cq_init_attr *attr,
953 struct ib_ucontext *ib_context,
954 struct ib_udata *udata);
955 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
956 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
957 int c4iw_destroy_qp(struct ib_qp *ib_qp);
958 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
959 struct ib_qp_init_attr *attrs,
960 struct ib_udata *udata);
961 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
962 int attr_mask, struct ib_udata *udata);
963 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
964 int attr_mask, struct ib_qp_init_attr *init_attr);
965 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
966 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
967 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
968 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
969 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
970 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct mbuf *m);
971 void c4iw_flush_hw_cq(struct c4iw_cq *cq);
972 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
973 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
974 int __c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
975 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
976 int c4iw_flush_sq(struct c4iw_qp *qhp);
977 int c4iw_ev_handler(struct sge_iq *, const struct rsp_ctrl *);
978 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
979 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
980 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
981 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
982 struct c4iw_dev_ucontext *uctx);
983 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
984 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
985 struct c4iw_dev_ucontext *uctx);
986 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
987 void t4_dump_stag(struct adapter *sc, const u32 stag);
988 void t4_dump_all_stag(struct adapter *sc);
989 #endif
990