1 /* $NetBSD: mii.h,v 1.28 2025/02/28 09:07:12 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Modification to match BSD/OS 3.0 MII interface by Jason R. Thorpe, 7 * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef _DEV_MII_MII_H_ 31 #define _DEV_MII_MII_H_ 32 33 /* 34 * Registers common to all PHYs. 35 */ 36 37 #define MII_NPHY 32 /* max # of PHYs per MII */ 38 #define MII_ADDRBITS 5 /* Register address bits (0x00..0x1f) */ 39 #define MII_ADDRMASK 0x1f /* Address mask */ 40 41 /* 42 * MII commands, used if a device must drive the MII lines 43 * manually. 44 */ 45 #define MII_COMMAND_START 0x01 46 #define MII_COMMAND_READ 0x02 47 #define MII_COMMAND_WRITE 0x01 48 #define MII_COMMAND_ACK 0x02 49 50 #define MII_BMCR 0x00 /* Basic mode control register (rw) */ 51 #define BMCR_RESET 0x8000 /* reset */ 52 #define BMCR_LOOP 0x4000 /* loopback */ 53 #define BMCR_SPEED0 0x2000 /* speed selection (LSB) */ 54 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */ 55 #define BMCR_PDOWN 0x0800 /* power down */ 56 #define BMCR_ISO 0x0400 /* isolate */ 57 #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */ 58 #define BMCR_FDX 0x0100 /* Set duplex mode */ 59 #define BMCR_CTEST 0x0080 /* collision test */ 60 #define BMCR_SPEED1 0x0040 /* speed selection (MSB) */ 61 #define BMCR_UNIDIR 0x0020 /* Unidirectional enable */ 62 63 #define BMCR_S10 0x0000 /* 10 Mb/s */ 64 #define BMCR_S100 BMCR_SPEED0 /* 100 Mb/s */ 65 #define BMCR_S1000 BMCR_SPEED1 /* 1000 Mb/s */ 66 67 #define BMCR_SPEED(x) ((x) & (BMCR_SPEED0 | BMCR_SPEED1)) 68 69 #define MII_BMSR 0x01 /* Basic mode status register (ro) */ 70 #define BMSR_100T4 0x8000 /* 100 base T4 capable */ 71 #define BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */ 72 #define BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */ 73 #define BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */ 74 #define BMSR_10THDX 0x0800 /* 10 base T half duplex capable */ 75 #define BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */ 76 #define BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */ 77 #define BMSR_EXTSTAT 0x0100 /* Extended status in register 15 */ 78 #define BMSR_UNIDIR 0x0080 /* Unidirectional ability */ 79 #define BMSR_MFPS 0x0040 /* MII Frame Preamble Suppression */ 80 #define BMSR_ACOMP 0x0020 /* Autonegotiation complete */ 81 #define BMSR_RFAULT 0x0010 /* Link partner fault */ 82 #define BMSR_ANEG 0x0008 /* Autonegotiation capable */ 83 #define BMSR_LINK 0x0004 /* Link status */ 84 #define BMSR_JABBER 0x0002 /* Jabber detected */ 85 #define BMSR_EXTCAP 0x0001 /* Extended capability */ 86 87 /* 88 * Note that the EXTSTAT bit indicates that there is extended status 89 * info available in register 15, but 802.3 section 22.2.4.3 also 90 * states that all 1000 Mb/s capable PHYs will set this bit to 1. 91 */ 92 93 #define BMSR_MEDIAMASK (BMSR_100T4 | BMSR_100TXFDX | BMSR_100TXHDX | \ 94 BMSR_10TFDX | BMSR_10THDX | BMSR_100T2FDX | BMSR_100T2HDX) 95 96 /* 97 * Convert BMSR media capabilities to ANAR bits for autonegotiation. 98 * Note the shift chopps off the BMSR_ANEG bit. 99 */ 100 #define BMSR_MEDIA_TO_ANAR(x) (((x) & BMSR_MEDIAMASK) >> 6) 101 102 #define MII_PHYIDR1 0x02 /* ID register 1 (ro) */ 103 104 #define MII_PHYIDR2 0x03 /* ID register 2 (ro) */ 105 #define IDR2_OUILSB 0xfc00 /* OUI LSB */ 106 #define IDR2_MODEL 0x03f0 /* vendor model */ 107 #define IDR2_REV 0x000f /* vendor revision */ 108 109 #define MII_ANAR 0x04 /* Autonegotiation advertisement (rw) */ 110 /* section 28.2.4.1 and 37.2.6.1 */ 111 #define ANAR_NP 0x8000 /* Next page (ro) */ 112 #define ANAR_ACK 0x4000 /* link partner abilities acknowledged (ro) */ 113 #define ANAR_RF 0x2000 /* remote fault (ro) */ 114 #define ANAR_XNP 0x1000 /* Extended Next Page */ 115 /* Annex 28B.2 */ 116 #define ANAR_FC 0x0400 /* local device supports PAUSE */ 117 #define ANAR_T4 0x0200 /* local device supports 100bT4 */ 118 #define ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */ 119 #define ANAR_TX 0x0080 /* local device supports 100bTx */ 120 #define ANAR_10_FD 0x0040 /* local device supports 10bT FD */ 121 #define ANAR_10 0x0020 /* local device supports 10bT */ 122 #define ANAR_CSMA 0x0001 /* protocol selector CSMA/CD */ 123 #define ANAR_PAUSE_NONE (0 << 10) 124 #define ANAR_PAUSE_SYM (1 << 10) 125 #define ANAR_PAUSE_ASYM (2 << 10) 126 #define ANAR_PAUSE_TOWARDS (3 << 10) 127 128 /* Annex 28D */ 129 #define ANAR_X_FD 0x0020 /* local device supports 1000BASE-X FD */ 130 #define ANAR_X_HD 0x0040 /* local device supports 1000BASE-X HD */ 131 #define ANAR_X_PAUSE_NONE (0 << 7) 132 #define ANAR_X_PAUSE_SYM (1 << 7) 133 #define ANAR_X_PAUSE_ASYM (2 << 7) 134 #define ANAR_X_PAUSE_TOWARDS (3 << 7) 135 /* 37.2.1.5 Remote Fault */ 136 #define ANAR_X_RF1 0x1000 137 #define ANAR_X_RF2 0x2000 138 #define ANAR_X_RF_MASK (ANAR_X_RF1 | ANAR_X_RF2) 139 #define ANAR_X_RF_NONE (0 << 12) 140 #define ANAR_X_RF_OFFLINE (1 << 12) 141 #define ANAR_X_RF_LINKFAIL (2 << 12) 142 #define ANAR_X_RF_ANEGERR (3 << 12) 143 144 #define MII_ANLPAR 0x05 /* ANEG Link Partner Base Page abilities (rw)*/ 145 /* section 28.2.4.1 and 37.2.6.1 */ 146 #define ANLPAR_NP 0x8000 /* Next page (ro) */ 147 #define ANLPAR_ACK 0x4000 /* link partner accepted ACK (ro) */ 148 #define ANLPAR_RF 0x2000 /* remote fault (ro) */ 149 #define ANLPAR_XNP 0x1000 /* Extended Next Page */ 150 #define ANLPAR_FC 0x0400 /* link partner supports PAUSE */ 151 #define ANLPAR_T4 0x0200 /* link partner supports 100bT4 */ 152 #define ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */ 153 #define ANLPAR_TX 0x0080 /* link partner supports 100bTx */ 154 #define ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */ 155 #define ANLPAR_10 0x0020 /* link partner supports 10bT */ 156 #define ANLPAR_CSMA 0x0001 /* protocol selector CSMA/CD */ 157 #define ANLPAR_PAUSE_MASK (3 << 10) 158 #define ANLPAR_PAUSE_NONE (0 << 10) 159 #define ANLPAR_PAUSE_SYM (1 << 10) 160 #define ANLPAR_PAUSE_ASYM (2 << 10) 161 #define ANLPAR_PAUSE_TOWARDS (3 << 10) 162 163 #define ANLPAR_X_FD 0x0020 /* local device supports 1000BASE-X FD */ 164 #define ANLPAR_X_HD 0x0040 /* local device supports 1000BASE-X HD */ 165 #define ANLPAR_X_PAUSE_MASK (3 << 7) 166 #define ANLPAR_X_PAUSE_NONE (0 << 7) 167 #define ANLPAR_X_PAUSE_SYM (1 << 7) 168 #define ANLPAR_X_PAUSE_ASYM (2 << 7) 169 #define ANLPAR_X_PAUSE_TOWARDS (3 << 7) 170 /* 37.2.1.5 Remote Fault */ 171 #define ANLPAR_X_RF1 0x1000 172 #define ANLPAR_X_RF2 0x2000 173 #define ANLPAR_X_RF_MASK (ANLPAR_X_RF1 | ANLPAR_X_RF2) 174 #define ANLPAR_X_RF_NONE (0 << 12) 175 #define ANLPAR_X_RF_OFFLINE (1 << 12) 176 #define ANLPAR_X_RF_LINKFAIL (2 << 12) 177 #define ANLPAR_X_RF_ANEGERR (3 << 12) 178 179 #define MII_ANER 0x06 /* Autonegotiation expansion (ro) */ 180 /* section 28.2.4.1 and 37.2.6.1 */ 181 #define ANER_RNPLA 0x0040 /* Receive Next Page Location Able */ 182 #define ANER_RNPSL 0x0020 /* Received Next Page Storage Location */ 183 #define ANER_MLF 0x0010 /* multiple link detection fault */ 184 #define ANER_LPNP 0x0008 /* link partner next page-able */ 185 #define ANER_NP 0x0004 /* next page-able */ 186 #define ANER_PAGE_RX 0x0002 /* Page received */ 187 #define ANER_LPAN 0x0001 /* link partner autoneg-able */ 188 189 #define MII_ANNPT 0x07 /* Autonegotiation next page transmit (rw) */ 190 /* section 28.2.4.1 and 37.2.6.1 */ 191 #define ANNPT_NP 0x8000 /* Next Page */ 192 #define ANNPT_MP 0x2000 /* Message Page */ 193 #define ANNPT_ACK2 0x1000 /* Acknowledge 2 */ 194 #define ANNPT_TOGGLE 0x0800 /* Toggle */ 195 #define ANNPT_MSGUNF_MASK 0x07ff /* Message(Annex28C)/Unformatted Code Field */ 196 197 /* Next Page Message Code used in ANNPT and ANLPRNP */ 198 #define ANNP_MSG_NULL 1 /* Null Message */ 199 #define ANNP_MSG_1UP_TAF 2 /* 1Up w/ Tech. Ability Field follows */ 200 #define ANNP_MSG_2UP_TAF 3 /* 2Up w/ Tech. Ability Field follows */ 201 #define ANNP_MSG_1UP_BCRF 4 /* 1Up w/ Bin. coded Remote Flt follows */ 202 #define ANNP_MSG_OUIDTMSG 5 /* OUI tagged Message */ 203 #define ANNP_MSG_PHYIDTC 6 /* PHY Identifier Tag Code */ 204 #define ANNP_MSG_TMC_100T2 7 /* 100BASE-T2 Tech. Message Code */ 205 #define ANNP_MSG_TMC_1000T 8 /* 1000BASE-T Tech. Message Code */ 206 #define ANNP_MSG_TMC_10G1G 9 /* 10GBASE-T/1000BASE-T TMC: (XNP) */ 207 #define ANNP_MSG_TMC_EEE 10 /* EEE Technology Message Code */ 208 #define ANNP_MSG_OUIDTM_XNP 11 /* OUI tagged Message (XNP) */ 209 210 211 #define MII_ANLPRNP 0x08 /* Autonegotiation link partner rx next page */ 212 /* section 32.5.1 and 37.2.6.1 */ 213 #define ANLPRNP_NP 0x8000 /* Next Page */ 214 #define ANLPRNP_ACK 0x4000 /* Acknowledge */ 215 #define ANLPRNP_MP 0x2000 /* Message Page */ 216 #define ANLPRNP_ACK2 0x1000 /* Acknowledge 2 */ 217 #define ANLPRNP_TOGGLE 0x0800 /* Toggle */ 218 #define ANLPRNP_MSGUNF_MASK 0x07ff /* Message(Anx28C)/Unformatted Code Field */ 219 220 #define MII_GTCR 0x09 /* 221 * Master-Slave control register for 222 * 100BASE-T2 and 1000BASE-T. 223 */ 224 #define MII_100T2CR MII_GTCR /* alias */ 225 #define GTCR_TEST_MASK 0xe000 /* see 802.3ab ss. 40.6.1.1.2 */ 226 #define GTCR_MAN_MS 0x1000 /* enable manual master/slave control */ 227 #define GTCR_ADV_MS 0x0800 /* 1 = adv. master, 0 = adv. slave */ 228 #define GTCR_PORT_TYPE 0x0400 /* 1 = DCE, 0 = DTE (NIC) */ 229 #define GTCR_ADV_1000TFDX 0x0200 /* adv. 1000baseT FDX */ 230 #define GTCR_ADV_1000THDX 0x0100 /* adv. 1000baseT HDX */ 231 232 #define T2CR_TEST_NORMAL (0 << 13) /* Normal Operation */ 233 #define T2CR_TEST_RX (1 << 13) /* RX test */ 234 #define T2CR_TEST_TX_WAVEFORM (1 << 14) /* Mode 1. TX waveform test */ 235 #define T2CR_TEST_TX_JITTER (2 << 14) /* Mode 2. TX jitter test */ 236 #define T2CR_TEST_TX_IDLE (3 << 14) /* Mode 3. TX idle test */ 237 238 #define GTCR_TEST_NORMAL (0 << 13) /* Normal Operation */ 239 #define GTCR_TEST_TX_WAVEFORM (1 << 13) /* Mode 1. TX waveform test */ 240 #define GTCR_TEST_TX_JITTER_M (2 << 13) /* Mode 2. TX jitter test (Master) */ 241 #define GTCR_TEST_TX_JITTER_S (3 << 13) /* Mode 3. TX jitter test (Slave) */ 242 #define GTCR_TEST_TX_DISTORTION (4 << 13) /* Mode 4. TX distortion test */ 243 244 #define MII_GTSR 0x0a /* 245 * Master-Slave status register for 246 * 100BASE-T2 and 1000BASE-T. 247 */ 248 #define MII_100T2SR MII_GTSR /* alias */ 249 #define GTSR_MAN_MS_FLT 0x8000 /* master/slave config fault */ 250 #define GTSR_MS_RES 0x4000 /* result: 1 = master, 0 = slave */ 251 #define GTSR_LRS 0x2000 /* local rx status, 1 = ok */ 252 #define GTSR_RRS 0x1000 /* remote rx status, 1 = ok */ 253 #define GTSR_LP_1000TFDX 0x0800 /* link partner 1000baseT FDX capable */ 254 #define GTSR_LP_1000THDX 0x0400 /* link partner 1000baseT HDX capable */ 255 #define GTSR_IDLE_ERR 0x00ff /* IDLE error count */ 256 257 #define MII_PSECR 0x0b /* PSE control register */ 258 #define PSECR_DLLC 0x0020 /* Data Link Layer Classification capability */ 259 #define PSECR_EPLC 0x0010 /* Enable Physical Layer Classification */ 260 #define PSECR_PACTLMASK 0x000c /* pair control mask */ 261 #define PSECR_PINOUTB 0x0008 /* PSE pinout Alternative B */ 262 #define PSECR_PINOUTA 0x0004 /* PSE pinout Alternative A */ 263 #define PSECR_PSEENMASK 0x0003 /* PSE enable mask */ 264 #define PSECR_FOPOWTST 0x0002 /* Force Power Test Mode */ 265 #define PSECR_PSEEN 0x0001 /* PSE Enabled */ 266 #define PSECR_PSEDIS 0x0000 /* PSE Disabled */ 267 268 #define MII_PSESR 0x0c /* PSE status register */ 269 #define PSESR_PWRDENIED 0x1000 /* Power Denied */ 270 #define PSESR_VALSIG 0x0800 /* Valid PD signature detected */ 271 #define PSESR_INVALSIG 0x0400 /* Invalid PD signature detected */ 272 #define PSESR_SHORTCIRC 0x0200 /* Short circuit condition detected */ 273 #define PSESR_OVERLOAD 0x0100 /* Overload condition detected */ 274 #define PSESR_MPSABSENT 0x0080 /* MPS absent condition detected */ 275 #define PSESR_PDCLMASK 0x0070 /* PD Class mask */ 276 #define PSESR_STATMASK 0x000e /* PSE Status mask */ 277 #define PSESR_PAIRCTABL 0x0001 /* PAIR Control Ability */ 278 #define PSESR_PDCL_INVALID (5 << 4) /* Invalid Class */ 279 #define PSESR_PDCL_4 (4 << 4) /* Class 4 */ 280 #define PSESR_PDCL_3 (3 << 4) /* Class 3 */ 281 #define PSESR_PDCL_2 (2 << 4) /* Class 2 */ 282 #define PSESR_PDCL_1 (1 << 4) /* Class 1 */ 283 #define PSESR_PDCL_0 (0 << 4) /* Class 0 */ 284 #define PSESR_STAT_ISFLT (5 << 1) /* Implement specific fault */ 285 #define PSESR_STAT_TSTERR (4 << 1) /* Test Error */ 286 #define PSESR_STAT_TSTMODE (3 << 1) /* Test Mode */ 287 #define PSESR_STAT_DELVPWR (2 << 1) /* Delivering power */ 288 #define PSESR_STAT_SEARCH (1 << 1) /* Searching */ 289 #define PSESR_STAT_DIS (0 << 1) /* Disabled */ 290 291 #define MII_MMDACR 0x0d /* MMD access control register */ 292 #define MMDACR_FUNCMASK 0xc000 /* function */ 293 #define MMDACR_DADDRMASK 0x001f /* device address */ 294 #define MMDACR_FN_ADDRESS (0 << 14) /* address */ 295 #define MMDACR_FN_DATA (1 << 14) /* data, no post increment */ 296 #define MMDACR_FN_DATA_INC_RW (2 << 14) /* data, post increment on r/w */ 297 #define MMDACR_FN_DATA_INC_W (3 << 14) /* data, post increment on wr only */ 298 299 #define MII_MMDAADR 0x0e /* MMD access address data register */ 300 301 #define MII_EXTSR 0x0f /* Extended status register */ 302 #define EXTSR_1000XFDX 0x8000 /* 1000X full-duplex capable */ 303 #define EXTSR_1000XHDX 0x4000 /* 1000X half-duplex capable */ 304 #define EXTSR_1000TFDX 0x2000 /* 1000T full-duplex capable */ 305 #define EXTSR_1000THDX 0x1000 /* 1000T half-duplex capable */ 306 307 #define EXTSR_MEDIAMASK (EXTSR_1000XFDX | EXTSR_1000XHDX | \ 308 EXTSR_1000TFDX | EXTSR_1000THDX) 309 310 #endif /* _DEV_MII_MII_H_ */ 311