1 /*-
2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: stable/10/sys/dev/mlx5/device.h 339713 2018-10-25 14:12:48Z slavash $
26 */
27
28 #ifndef MLX5_DEVICE_H
29 #define MLX5_DEVICE_H
30
31 #include <linux/types.h>
32 #include <rdma/ib_verbs.h>
33 #include <dev/mlx5/mlx5_ifc.h>
34
35 #define FW_INIT_TIMEOUT_MILI 2000
36 #define FW_INIT_WAIT_MS 2
37
38 #if defined(__LITTLE_ENDIAN)
39 #define MLX5_SET_HOST_ENDIANNESS 0
40 #elif defined(__BIG_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0x80
42 #else
43 #error Host endianness not defined
44 #endif
45
46 /* helper macros */
47 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
48 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
49 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld)
50 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
51 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
52 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
53 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
54 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
55 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
56
57 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
58 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
59 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
60 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
61 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
62 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
63 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
64 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
65
66 /* insert a value to a struct */
67 #define MLX5_SET(typ, p, fld, v) do { \
68 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
69 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
73 << __mlx5_dw_bit_off(typ, fld))); \
74 } while (0)
75
76 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
78 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
82 << __mlx5_dw_bit_off(typ, fld))); \
83 } while (0)
84
85 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
86 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
87 __mlx5_mask(typ, fld))
88
89 #define MLX5_GET_PR(typ, p, fld) ({ \
90 u32 ___t = MLX5_GET(typ, p, fld); \
91 pr_debug(#fld " = 0x%x\n", ___t); \
92 ___t; \
93 })
94
95 #define MLX5_SET64(typ, p, fld, v) do { \
96 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
97 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
98 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
99 } while (0)
100
101 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
102
103 enum {
104 MLX5_MAX_COMMANDS = 32,
105 MLX5_CMD_DATA_BLOCK_SIZE = 512,
106 MLX5_CMD_MBOX_SIZE = 1024,
107 MLX5_PCI_CMD_XPORT = 7,
108 MLX5_MKEY_BSF_OCTO_SIZE = 4,
109 MLX5_MAX_PSVS = 4,
110 };
111
112 enum {
113 MLX5_EXTENDED_UD_AV = 0x80000000,
114 };
115
116 enum {
117 MLX5_CQ_FLAGS_OI = 2,
118 };
119
120 enum {
121 MLX5_STAT_RATE_OFFSET = 5,
122 };
123
124 enum {
125 MLX5_INLINE_SEG = 0x80000000,
126 };
127
128 enum {
129 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
130 };
131
132 enum {
133 MLX5_MIN_PKEY_TABLE_SIZE = 128,
134 MLX5_MAX_LOG_PKEY_TABLE = 5,
135 };
136
137 enum {
138 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
139 };
140
141 enum {
142 MLX5_PERM_LOCAL_READ = 1 << 2,
143 MLX5_PERM_LOCAL_WRITE = 1 << 3,
144 MLX5_PERM_REMOTE_READ = 1 << 4,
145 MLX5_PERM_REMOTE_WRITE = 1 << 5,
146 MLX5_PERM_ATOMIC = 1 << 6,
147 MLX5_PERM_UMR_EN = 1 << 7,
148 };
149
150 enum {
151 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
152 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
153 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
154 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
155 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
156 };
157
158 enum {
159 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
160 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
161 MLX5_MKEY_BSF_EN = 1 << 30,
162 MLX5_MKEY_LEN64 = 1 << 31,
163 };
164
165 enum {
166 MLX5_EN_RD = (u64)1,
167 MLX5_EN_WR = (u64)2
168 };
169
170 enum {
171 MLX5_BF_REGS_PER_PAGE = 4,
172 MLX5_MAX_UAR_PAGES = 1 << 8,
173 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
174 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
175 };
176
177 enum {
178 MLX5_MKEY_MASK_LEN = 1ull << 0,
179 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
180 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
181 MLX5_MKEY_MASK_PD = 1ull << 7,
182 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
183 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
184 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
185 MLX5_MKEY_MASK_KEY = 1ull << 13,
186 MLX5_MKEY_MASK_QPN = 1ull << 14,
187 MLX5_MKEY_MASK_LR = 1ull << 17,
188 MLX5_MKEY_MASK_LW = 1ull << 18,
189 MLX5_MKEY_MASK_RR = 1ull << 19,
190 MLX5_MKEY_MASK_RW = 1ull << 20,
191 MLX5_MKEY_MASK_A = 1ull << 21,
192 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
193 MLX5_MKEY_MASK_FREE = 1ull << 29,
194 };
195
196 enum {
197 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
198
199 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
200 MLX5_UMR_CHECK_FREE = (2 << 5),
201
202 MLX5_UMR_INLINE = (1 << 7),
203 };
204
205 #define MLX5_UMR_MTT_ALIGNMENT 0x40
206 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
207 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
208
209 enum {
210 MLX5_EVENT_QUEUE_TYPE_QP = 0,
211 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
212 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
213 };
214
215 enum {
216 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
217 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
218 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
219 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
220 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
221 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
222 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
223 };
224
225 enum {
226 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1,
227 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE,
228 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE,
229 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE,
230 MLX5_MAX_INLINE_RECEIVE_SIZE = 64
231 };
232
233 enum {
234 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
235 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
236 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
237 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
238 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21,
239 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
240 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
241 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
242 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33,
243 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34,
244 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
245 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
246 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
247 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48,
248 };
249
250 enum {
251 MLX5_ROCE_VERSION_1 = 0,
252 MLX5_ROCE_VERSION_1_5 = 1,
253 MLX5_ROCE_VERSION_2 = 2,
254 };
255
256 enum {
257 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
258 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5,
259 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
260 };
261
262 enum {
263 MLX5_ROCE_L3_TYPE_IPV4 = 0,
264 MLX5_ROCE_L3_TYPE_IPV6 = 1,
265 };
266
267 enum {
268 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
269 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
270 };
271
272 enum {
273 MLX5_OPCODE_NOP = 0x00,
274 MLX5_OPCODE_SEND_INVAL = 0x01,
275 MLX5_OPCODE_RDMA_WRITE = 0x08,
276 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
277 MLX5_OPCODE_SEND = 0x0a,
278 MLX5_OPCODE_SEND_IMM = 0x0b,
279 MLX5_OPCODE_LSO = 0x0e,
280 MLX5_OPCODE_RDMA_READ = 0x10,
281 MLX5_OPCODE_ATOMIC_CS = 0x11,
282 MLX5_OPCODE_ATOMIC_FA = 0x12,
283 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
284 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
285 MLX5_OPCODE_BIND_MW = 0x18,
286 MLX5_OPCODE_CONFIG_CMD = 0x1f,
287
288 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
289 MLX5_RECV_OPCODE_SEND = 0x01,
290 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
291 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
292
293 MLX5_CQE_OPCODE_ERROR = 0x1e,
294 MLX5_CQE_OPCODE_RESIZE = 0x16,
295
296 MLX5_OPCODE_SET_PSV = 0x20,
297 MLX5_OPCODE_GET_PSV = 0x21,
298 MLX5_OPCODE_CHECK_PSV = 0x22,
299 MLX5_OPCODE_RGET_PSV = 0x26,
300 MLX5_OPCODE_RCHECK_PSV = 0x27,
301
302 MLX5_OPCODE_UMR = 0x25,
303
304 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15),
305 };
306
307 enum {
308 MLX5_SET_PORT_RESET_QKEY = 0,
309 MLX5_SET_PORT_GUID0 = 16,
310 MLX5_SET_PORT_NODE_GUID = 17,
311 MLX5_SET_PORT_SYS_GUID = 18,
312 MLX5_SET_PORT_GID_TABLE = 19,
313 MLX5_SET_PORT_PKEY_TABLE = 20,
314 };
315
316 enum {
317 MLX5_MAX_PAGE_SHIFT = 31
318 };
319
320 enum {
321 MLX5_ADAPTER_PAGE_SHIFT = 12,
322 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
323 };
324
325 enum {
326 MLX5_CAP_OFF_CMDIF_CSUM = 46,
327 };
328
329 struct mlx5_inbox_hdr {
330 __be16 opcode;
331 u8 rsvd[4];
332 __be16 opmod;
333 };
334
335 struct mlx5_outbox_hdr {
336 u8 status;
337 u8 rsvd[3];
338 __be32 syndrome;
339 };
340
341 struct mlx5_cmd_set_dc_cnak_mbox_in {
342 struct mlx5_inbox_hdr hdr;
343 u8 enable;
344 u8 reserved[47];
345 __be64 pa;
346 };
347
348 struct mlx5_cmd_set_dc_cnak_mbox_out {
349 struct mlx5_outbox_hdr hdr;
350 u8 rsvd[8];
351 };
352
353 struct mlx5_cmd_layout {
354 u8 type;
355 u8 rsvd0[3];
356 __be32 inlen;
357 __be64 in_ptr;
358 __be32 in[4];
359 __be32 out[4];
360 __be64 out_ptr;
361 __be32 outlen;
362 u8 token;
363 u8 sig;
364 u8 rsvd1;
365 u8 status_own;
366 };
367
368
369 struct mlx5_health_buffer {
370 __be32 assert_var[5];
371 __be32 rsvd0[3];
372 __be32 assert_exit_ptr;
373 __be32 assert_callra;
374 __be32 rsvd1[2];
375 __be32 fw_ver;
376 __be32 hw_id;
377 __be32 rsvd2;
378 u8 irisc_index;
379 u8 synd;
380 __be16 ext_sync;
381 };
382
383 struct mlx5_init_seg {
384 __be32 fw_rev;
385 __be32 cmdif_rev_fw_sub;
386 __be32 rsvd0[2];
387 __be32 cmdq_addr_h;
388 __be32 cmdq_addr_l_sz;
389 __be32 cmd_dbell;
390 __be32 rsvd1[120];
391 __be32 initializing;
392 struct mlx5_health_buffer health;
393 __be32 rsvd2[880];
394 __be32 internal_timer_h;
395 __be32 internal_timer_l;
396 __be32 rsvd3[2];
397 __be32 health_counter;
398 __be32 rsvd4[1019];
399 __be64 ieee1588_clk;
400 __be32 ieee1588_clk_type;
401 __be32 clr_intx;
402 };
403
404 struct mlx5_eqe_comp {
405 __be32 reserved[6];
406 __be32 cqn;
407 };
408
409 struct mlx5_eqe_qp_srq {
410 __be32 reserved[6];
411 __be32 qp_srq_n;
412 };
413
414 struct mlx5_eqe_cq_err {
415 __be32 cqn;
416 u8 reserved1[7];
417 u8 syndrome;
418 };
419
420 struct mlx5_eqe_port_state {
421 u8 reserved0[8];
422 u8 port;
423 };
424
425 struct mlx5_eqe_gpio {
426 __be32 reserved0[2];
427 __be64 gpio_event;
428 };
429
430 struct mlx5_eqe_congestion {
431 u8 type;
432 u8 rsvd0;
433 u8 congestion_level;
434 };
435
436 struct mlx5_eqe_stall_vl {
437 u8 rsvd0[3];
438 u8 port_vl;
439 };
440
441 struct mlx5_eqe_cmd {
442 __be32 vector;
443 __be32 rsvd[6];
444 };
445
446 struct mlx5_eqe_page_req {
447 u8 rsvd0[2];
448 __be16 func_id;
449 __be32 num_pages;
450 __be32 rsvd1[5];
451 };
452
453 struct mlx5_eqe_vport_change {
454 u8 rsvd0[2];
455 __be16 vport_num;
456 __be32 rsvd1[6];
457 };
458
459
460 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
461 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
462
463 enum {
464 MLX5_MODULE_STATUS_PLUGGED = 0x1,
465 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
466 MLX5_MODULE_STATUS_ERROR = 0x3,
467 };
468
469 enum {
470 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0,
471 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1,
472 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2,
473 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3,
474 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4,
475 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER = 0x5,
476 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6,
477 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7,
478 MLX5_MODULE_EVENT_ERROR_PCIE_SYSTEM_POWER_SLOT_EXCEEDED = 0xc,
479 };
480
481 struct mlx5_eqe_port_module_event {
482 u8 rsvd0;
483 u8 module;
484 u8 rsvd1;
485 u8 module_status;
486 u8 rsvd2[2];
487 u8 error_type;
488 };
489
490 union ev_data {
491 __be32 raw[7];
492 struct mlx5_eqe_cmd cmd;
493 struct mlx5_eqe_comp comp;
494 struct mlx5_eqe_qp_srq qp_srq;
495 struct mlx5_eqe_cq_err cq_err;
496 struct mlx5_eqe_port_state port;
497 struct mlx5_eqe_gpio gpio;
498 struct mlx5_eqe_congestion cong;
499 struct mlx5_eqe_stall_vl stall_vl;
500 struct mlx5_eqe_page_req req_pages;
501 struct mlx5_eqe_port_module_event port_module_event;
502 struct mlx5_eqe_vport_change vport_change;
503 } __packed;
504
505 struct mlx5_eqe {
506 u8 rsvd0;
507 u8 type;
508 u8 rsvd1;
509 u8 sub_type;
510 __be32 rsvd2[7];
511 union ev_data data;
512 __be16 rsvd3;
513 u8 signature;
514 u8 owner;
515 } __packed;
516
517 struct mlx5_cmd_prot_block {
518 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
519 u8 rsvd0[48];
520 __be64 next;
521 __be32 block_num;
522 u8 rsvd1;
523 u8 token;
524 u8 ctrl_sig;
525 u8 sig;
526 };
527
528 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \
529 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE)
530 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block));
531 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE);
532
533 enum {
534 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
535 };
536
537 struct mlx5_err_cqe {
538 u8 rsvd0[32];
539 __be32 srqn;
540 u8 rsvd1[18];
541 u8 vendor_err_synd;
542 u8 syndrome;
543 __be32 s_wqe_opcode_qpn;
544 __be16 wqe_counter;
545 u8 signature;
546 u8 op_own;
547 };
548
549 struct mlx5_cqe64 {
550 u8 tunneled_etc;
551 u8 rsvd0[3];
552 u8 lro_tcppsh_abort_dupack;
553 u8 lro_min_ttl;
554 __be16 lro_tcp_win;
555 __be32 lro_ack_seq_num;
556 __be32 rss_hash_result;
557 u8 rss_hash_type;
558 u8 ml_path;
559 u8 rsvd20[2];
560 __be16 check_sum;
561 __be16 slid;
562 __be32 flags_rqpn;
563 u8 hds_ip_ext;
564 u8 l4_hdr_type_etc;
565 __be16 vlan_info;
566 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
567 __be32 imm_inval_pkey;
568 u8 rsvd40[4];
569 __be32 byte_cnt;
570 __be64 timestamp;
571 __be32 sop_drop_qpn;
572 __be16 wqe_counter;
573 u8 signature;
574 u8 op_own;
575 };
576
get_cqe_lro_timestamp_valid(struct mlx5_cqe64 * cqe)577 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe)
578 {
579 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1;
580 }
581
get_cqe_lro_tcppsh(struct mlx5_cqe64 * cqe)582 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
583 {
584 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
585 }
586
get_cqe_l4_hdr_type(struct mlx5_cqe64 * cqe)587 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
588 {
589 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
590 }
591
get_cqe_vlan(struct mlx5_cqe64 * cqe)592 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe)
593 {
594 return be16_to_cpu(cqe->vlan_info) & 0xfff;
595 }
596
get_cqe_smac(struct mlx5_cqe64 * cqe,u8 * smac)597 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac)
598 {
599 memcpy(smac, &cqe->rss_hash_type , 4);
600 memcpy(smac + 4, &cqe->slid , 2);
601 }
602
cqe_has_vlan(struct mlx5_cqe64 * cqe)603 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
604 {
605 return cqe->l4_hdr_type_etc & 0x1;
606 }
607
cqe_is_tunneled(struct mlx5_cqe64 * cqe)608 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
609 {
610 return cqe->tunneled_etc & 0x1;
611 }
612
613 enum {
614 CQE_L4_HDR_TYPE_NONE = 0x0,
615 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
616 CQE_L4_HDR_TYPE_UDP = 0x2,
617 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
618 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
619 };
620
621 enum {
622 /* source L3 hash types */
623 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0,
624 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0,
625 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0,
626
627 /* destination L3 hash types */
628 CQE_RSS_DST_HTYPE_IP = 0x3 << 2,
629 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2,
630 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2,
631
632 /* source L4 hash types */
633 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4,
634 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4,
635 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4,
636 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4,
637
638 /* destination L4 hash types */
639 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6,
640 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6,
641 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6,
642 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6,
643 };
644
645 enum {
646 CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
647 CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
648 CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
649 };
650
651 enum {
652 CQE_L2_OK = 1 << 0,
653 CQE_L3_OK = 1 << 1,
654 CQE_L4_OK = 1 << 2,
655 };
656
657 struct mlx5_sig_err_cqe {
658 u8 rsvd0[16];
659 __be32 expected_trans_sig;
660 __be32 actual_trans_sig;
661 __be32 expected_reftag;
662 __be32 actual_reftag;
663 __be16 syndrome;
664 u8 rsvd22[2];
665 __be32 mkey;
666 __be64 err_offset;
667 u8 rsvd30[8];
668 __be32 qpn;
669 u8 rsvd38[2];
670 u8 signature;
671 u8 op_own;
672 };
673
674 struct mlx5_wqe_srq_next_seg {
675 u8 rsvd0[2];
676 __be16 next_wqe_index;
677 u8 signature;
678 u8 rsvd1[11];
679 };
680
681 union mlx5_ext_cqe {
682 struct ib_grh grh;
683 u8 inl[64];
684 };
685
686 struct mlx5_cqe128 {
687 union mlx5_ext_cqe inl_grh;
688 struct mlx5_cqe64 cqe64;
689 };
690
691 struct mlx5_srq_ctx {
692 u8 state_log_sz;
693 u8 rsvd0[3];
694 __be32 flags_xrcd;
695 __be32 pgoff_cqn;
696 u8 rsvd1[4];
697 u8 log_pg_sz;
698 u8 rsvd2[7];
699 __be32 pd;
700 __be16 lwm;
701 __be16 wqe_cnt;
702 u8 rsvd3[8];
703 __be64 db_record;
704 };
705
706 struct mlx5_create_srq_mbox_in {
707 struct mlx5_inbox_hdr hdr;
708 __be32 input_srqn;
709 u8 rsvd0[4];
710 struct mlx5_srq_ctx ctx;
711 u8 rsvd1[208];
712 __be64 pas[0];
713 };
714
715 struct mlx5_create_srq_mbox_out {
716 struct mlx5_outbox_hdr hdr;
717 __be32 srqn;
718 u8 rsvd[4];
719 };
720
721 struct mlx5_destroy_srq_mbox_in {
722 struct mlx5_inbox_hdr hdr;
723 __be32 srqn;
724 u8 rsvd[4];
725 };
726
727 struct mlx5_destroy_srq_mbox_out {
728 struct mlx5_outbox_hdr hdr;
729 u8 rsvd[8];
730 };
731
732 struct mlx5_query_srq_mbox_in {
733 struct mlx5_inbox_hdr hdr;
734 __be32 srqn;
735 u8 rsvd0[4];
736 };
737
738 struct mlx5_query_srq_mbox_out {
739 struct mlx5_outbox_hdr hdr;
740 u8 rsvd0[8];
741 struct mlx5_srq_ctx ctx;
742 u8 rsvd1[32];
743 __be64 pas[0];
744 };
745
746 struct mlx5_arm_srq_mbox_in {
747 struct mlx5_inbox_hdr hdr;
748 __be32 srqn;
749 __be16 rsvd;
750 __be16 lwm;
751 };
752
753 struct mlx5_arm_srq_mbox_out {
754 struct mlx5_outbox_hdr hdr;
755 u8 rsvd[8];
756 };
757
758 struct mlx5_cq_context {
759 u8 status;
760 u8 cqe_sz_flags;
761 u8 st;
762 u8 rsvd3;
763 u8 rsvd4[6];
764 __be16 page_offset;
765 __be32 log_sz_usr_page;
766 __be16 cq_period;
767 __be16 cq_max_count;
768 __be16 rsvd20;
769 __be16 c_eqn;
770 u8 log_pg_sz;
771 u8 rsvd25[7];
772 __be32 last_notified_index;
773 __be32 solicit_producer_index;
774 __be32 consumer_counter;
775 __be32 producer_counter;
776 u8 rsvd48[8];
777 __be64 db_record_addr;
778 };
779
780 struct mlx5_create_cq_mbox_in {
781 struct mlx5_inbox_hdr hdr;
782 __be32 input_cqn;
783 u8 rsvdx[4];
784 struct mlx5_cq_context ctx;
785 u8 rsvd6[192];
786 __be64 pas[0];
787 };
788
789 struct mlx5_create_cq_mbox_out {
790 struct mlx5_outbox_hdr hdr;
791 __be32 cqn;
792 u8 rsvd0[4];
793 };
794
795 struct mlx5_destroy_cq_mbox_in {
796 struct mlx5_inbox_hdr hdr;
797 __be32 cqn;
798 u8 rsvd0[4];
799 };
800
801 struct mlx5_destroy_cq_mbox_out {
802 struct mlx5_outbox_hdr hdr;
803 u8 rsvd0[8];
804 };
805
806 struct mlx5_query_cq_mbox_in {
807 struct mlx5_inbox_hdr hdr;
808 __be32 cqn;
809 u8 rsvd0[4];
810 };
811
812 struct mlx5_query_cq_mbox_out {
813 struct mlx5_outbox_hdr hdr;
814 u8 rsvd0[8];
815 struct mlx5_cq_context ctx;
816 u8 rsvd6[16];
817 __be64 pas[0];
818 };
819
820 struct mlx5_modify_cq_mbox_in {
821 struct mlx5_inbox_hdr hdr;
822 __be32 cqn;
823 __be32 field_select;
824 struct mlx5_cq_context ctx;
825 u8 rsvd[192];
826 __be64 pas[0];
827 };
828
829 struct mlx5_modify_cq_mbox_out {
830 struct mlx5_outbox_hdr hdr;
831 u8 rsvd[8];
832 };
833
834 struct mlx5_eq_context {
835 u8 status;
836 u8 ec_oi;
837 u8 st;
838 u8 rsvd2[7];
839 __be16 page_pffset;
840 __be32 log_sz_usr_page;
841 u8 rsvd3[7];
842 u8 intr;
843 u8 log_page_size;
844 u8 rsvd4[15];
845 __be32 consumer_counter;
846 __be32 produser_counter;
847 u8 rsvd5[16];
848 };
849
850 struct mlx5_create_eq_mbox_in {
851 struct mlx5_inbox_hdr hdr;
852 u8 rsvd0[3];
853 u8 input_eqn;
854 u8 rsvd1[4];
855 struct mlx5_eq_context ctx;
856 u8 rsvd2[8];
857 __be64 events_mask;
858 u8 rsvd3[176];
859 __be64 pas[0];
860 };
861
862 struct mlx5_create_eq_mbox_out {
863 struct mlx5_outbox_hdr hdr;
864 u8 rsvd0[3];
865 u8 eq_number;
866 u8 rsvd1[4];
867 };
868
869 struct mlx5_map_eq_mbox_in {
870 struct mlx5_inbox_hdr hdr;
871 __be64 mask;
872 u8 mu;
873 u8 rsvd0[2];
874 u8 eqn;
875 u8 rsvd1[24];
876 };
877
878 struct mlx5_map_eq_mbox_out {
879 struct mlx5_outbox_hdr hdr;
880 u8 rsvd[8];
881 };
882
883 struct mlx5_query_eq_mbox_in {
884 struct mlx5_inbox_hdr hdr;
885 u8 rsvd0[3];
886 u8 eqn;
887 u8 rsvd1[4];
888 };
889
890 struct mlx5_query_eq_mbox_out {
891 struct mlx5_outbox_hdr hdr;
892 u8 rsvd[8];
893 struct mlx5_eq_context ctx;
894 };
895
896 enum {
897 MLX5_MKEY_STATUS_FREE = 1 << 6,
898 };
899
900 struct mlx5_mkey_seg {
901 /* This is a two bit field occupying bits 31-30.
902 * bit 31 is always 0,
903 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
904 */
905 u8 status;
906 u8 pcie_control;
907 u8 flags;
908 u8 version;
909 __be32 qpn_mkey7_0;
910 u8 rsvd1[4];
911 __be32 flags_pd;
912 __be64 start_addr;
913 __be64 len;
914 __be32 bsfs_octo_size;
915 u8 rsvd2[16];
916 __be32 xlt_oct_size;
917 u8 rsvd3[3];
918 u8 log2_page_size;
919 u8 rsvd4[4];
920 };
921
922 struct mlx5_query_special_ctxs_mbox_in {
923 struct mlx5_inbox_hdr hdr;
924 u8 rsvd[8];
925 };
926
927 struct mlx5_query_special_ctxs_mbox_out {
928 struct mlx5_outbox_hdr hdr;
929 __be32 dump_fill_mkey;
930 __be32 reserved_lkey;
931 };
932
933 struct mlx5_create_mkey_mbox_in {
934 struct mlx5_inbox_hdr hdr;
935 __be32 input_mkey_index;
936 __be32 flags;
937 struct mlx5_mkey_seg seg;
938 u8 rsvd1[16];
939 __be32 xlat_oct_act_size;
940 __be32 rsvd2;
941 u8 rsvd3[168];
942 __be64 pas[0];
943 };
944
945 struct mlx5_create_mkey_mbox_out {
946 struct mlx5_outbox_hdr hdr;
947 __be32 mkey;
948 u8 rsvd[4];
949 };
950
951 struct mlx5_query_mkey_mbox_in {
952 struct mlx5_inbox_hdr hdr;
953 __be32 mkey;
954 };
955
956 struct mlx5_query_mkey_mbox_out {
957 struct mlx5_outbox_hdr hdr;
958 __be64 pas[0];
959 };
960
961 struct mlx5_modify_mkey_mbox_in {
962 struct mlx5_inbox_hdr hdr;
963 __be32 mkey;
964 __be64 pas[0];
965 };
966
967 struct mlx5_modify_mkey_mbox_out {
968 struct mlx5_outbox_hdr hdr;
969 u8 rsvd[8];
970 };
971
972 struct mlx5_dump_mkey_mbox_in {
973 struct mlx5_inbox_hdr hdr;
974 };
975
976 struct mlx5_dump_mkey_mbox_out {
977 struct mlx5_outbox_hdr hdr;
978 __be32 mkey;
979 };
980
981 struct mlx5_mad_ifc_mbox_in {
982 struct mlx5_inbox_hdr hdr;
983 __be16 remote_lid;
984 u8 rsvd0;
985 u8 port;
986 u8 rsvd1[4];
987 u8 data[256];
988 };
989
990 struct mlx5_mad_ifc_mbox_out {
991 struct mlx5_outbox_hdr hdr;
992 u8 rsvd[8];
993 u8 data[256];
994 };
995
996 struct mlx5_access_reg_mbox_in {
997 struct mlx5_inbox_hdr hdr;
998 u8 rsvd0[2];
999 __be16 register_id;
1000 __be32 arg;
1001 __be32 data[0];
1002 };
1003
1004 struct mlx5_access_reg_mbox_out {
1005 struct mlx5_outbox_hdr hdr;
1006 u8 rsvd[8];
1007 __be32 data[0];
1008 };
1009
1010 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1011
1012 enum {
1013 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1014 };
1015
1016 struct mlx5_allocate_psv_in {
1017 struct mlx5_inbox_hdr hdr;
1018 __be32 npsv_pd;
1019 __be32 rsvd_psv0;
1020 };
1021
1022 struct mlx5_allocate_psv_out {
1023 struct mlx5_outbox_hdr hdr;
1024 u8 rsvd[8];
1025 __be32 psv_idx[4];
1026 };
1027
1028 struct mlx5_destroy_psv_in {
1029 struct mlx5_inbox_hdr hdr;
1030 __be32 psv_number;
1031 u8 rsvd[4];
1032 };
1033
1034 struct mlx5_destroy_psv_out {
1035 struct mlx5_outbox_hdr hdr;
1036 u8 rsvd[8];
1037 };
1038
mlx5_host_is_le(void)1039 static inline int mlx5_host_is_le(void)
1040 {
1041 #if defined(__LITTLE_ENDIAN)
1042 return 1;
1043 #elif defined(__BIG_ENDIAN)
1044 return 0;
1045 #else
1046 #error Host endianness not defined
1047 #endif
1048 }
1049
1050 #define MLX5_CMD_OP_MAX 0x939
1051
1052 enum {
1053 VPORT_STATE_DOWN = 0x0,
1054 VPORT_STATE_UP = 0x1,
1055 };
1056
1057 enum {
1058 MLX5_L3_PROT_TYPE_IPV4 = 0,
1059 MLX5_L3_PROT_TYPE_IPV6 = 1,
1060 };
1061
1062 enum {
1063 MLX5_L4_PROT_TYPE_TCP = 0,
1064 MLX5_L4_PROT_TYPE_UDP = 1,
1065 };
1066
1067 enum {
1068 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1069 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1070 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1071 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1072 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1073 };
1074
1075 enum {
1076 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1077 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1078 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1079
1080 };
1081
1082 enum {
1083 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1084 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2,
1085 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3,
1086 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1087 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5,
1088 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6,
1089 };
1090
1091 enum {
1092 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0,
1093 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1,
1094 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2
1095 };
1096
1097 enum {
1098 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0,
1099 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1,
1100 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2,
1101 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3
1102 };
1103
1104 enum {
1105 MLX5_UC_ADDR_CHANGE = (1 << 0),
1106 MLX5_MC_ADDR_CHANGE = (1 << 1),
1107 MLX5_VLAN_CHANGE = (1 << 2),
1108 MLX5_PROMISC_CHANGE = (1 << 3),
1109 MLX5_MTU_CHANGE = (1 << 4),
1110 };
1111
1112 enum mlx5_list_type {
1113 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0,
1114 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1,
1115 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2,
1116 };
1117
1118 enum {
1119 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
1120 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
1121 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
1122 };
1123
1124 /* MLX5 DEV CAPs */
1125
1126 /* TODO: EAT.ME */
1127 enum mlx5_cap_mode {
1128 HCA_CAP_OPMOD_GET_MAX = 0,
1129 HCA_CAP_OPMOD_GET_CUR = 1,
1130 };
1131
1132 enum mlx5_cap_type {
1133 MLX5_CAP_GENERAL = 0,
1134 MLX5_CAP_ETHERNET_OFFLOADS,
1135 MLX5_CAP_ODP,
1136 MLX5_CAP_ATOMIC,
1137 MLX5_CAP_ROCE,
1138 MLX5_CAP_IPOIB_OFFLOADS,
1139 MLX5_CAP_EOIB_OFFLOADS,
1140 MLX5_CAP_FLOW_TABLE,
1141 MLX5_CAP_ESWITCH_FLOW_TABLE,
1142 MLX5_CAP_ESWITCH,
1143 MLX5_CAP_SNAPSHOT,
1144 MLX5_CAP_VECTOR_CALC,
1145 MLX5_CAP_QOS,
1146 MLX5_CAP_DEBUG,
1147 /* NUM OF CAP Types */
1148 MLX5_CAP_NUM
1149 };
1150
1151 /* GET Dev Caps macros */
1152 #define MLX5_CAP_GEN(mdev, cap) \
1153 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1154
1155 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1156 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1157
1158 #define MLX5_CAP_ETH(mdev, cap) \
1159 MLX5_GET(per_protocol_networking_offload_caps,\
1160 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1161
1162 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1163 MLX5_GET(per_protocol_networking_offload_caps,\
1164 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1165
1166 #define MLX5_CAP_ROCE(mdev, cap) \
1167 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1168
1169 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1170 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1171
1172 #define MLX5_CAP_ATOMIC(mdev, cap) \
1173 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1174
1175 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1176 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1177
1178 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1179 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1180
1181 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1182 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1183
1184 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1185 MLX5_GET(flow_table_eswitch_cap, \
1186 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1187
1188 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1189 MLX5_GET(flow_table_eswitch_cap, \
1190 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1191
1192 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1193 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1194
1195 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1196 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1197
1198 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1199 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1200
1201 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1202 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1203
1204 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1205 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1206
1207 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1208 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1209
1210 #define MLX5_CAP_ESW(mdev, cap) \
1211 MLX5_GET(e_switch_cap, \
1212 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1213
1214 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1215 MLX5_GET(e_switch_cap, \
1216 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1217
1218 #define MLX5_CAP_ODP(mdev, cap)\
1219 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1220
1221 #define MLX5_CAP_ODP_MAX(mdev, cap)\
1222 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1223
1224 #define MLX5_CAP_SNAPSHOT(mdev, cap) \
1225 MLX5_GET(snapshot_cap, \
1226 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1227
1228 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \
1229 MLX5_GET(snapshot_cap, \
1230 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1231
1232 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \
1233 MLX5_GET(per_protocol_networking_offload_caps,\
1234 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1235
1236 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \
1237 MLX5_GET(per_protocol_networking_offload_caps,\
1238 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1239
1240 #define MLX5_CAP_DEBUG(mdev, cap) \
1241 MLX5_GET(debug_cap, \
1242 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1243
1244 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \
1245 MLX5_GET(debug_cap, \
1246 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1247
1248 #define MLX5_CAP_QOS(mdev, cap) \
1249 MLX5_GET(qos_cap,\
1250 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1251
1252 #define MLX5_CAP_QOS_MAX(mdev, cap) \
1253 MLX5_GET(qos_cap,\
1254 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1255
1256 enum {
1257 MLX5_CMD_STAT_OK = 0x0,
1258 MLX5_CMD_STAT_INT_ERR = 0x1,
1259 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1260 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1261 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1262 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1263 MLX5_CMD_STAT_RES_BUSY = 0x6,
1264 MLX5_CMD_STAT_LIM_ERR = 0x8,
1265 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1266 MLX5_CMD_STAT_IX_ERR = 0xa,
1267 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1268 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1269 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1270 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1271 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1272 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1273 };
1274
1275 enum {
1276 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1277 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1278 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1279 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1280 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1281 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6,
1282 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1283 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1284 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1285 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1286 };
1287
1288 enum {
1289 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1290 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1,
1291 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2,
1292 };
1293
1294 enum {
1295 MLX5_NUM_UUARS_PER_PAGE = MLX5_NON_FP_BF_REGS_PER_PAGE,
1296 MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_UUARS_PER_PAGE,
1297 };
1298
1299 enum {
1300 NUM_DRIVER_UARS = 4,
1301 NUM_LOW_LAT_UUARS = 4,
1302 };
1303
1304 enum {
1305 MLX5_CAP_PORT_TYPE_IB = 0x0,
1306 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1307 };
1308
1309 enum {
1310 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0,
1311 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1,
1312 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2
1313 };
1314
1315 enum mlx5_inline_modes {
1316 MLX5_INLINE_MODE_NONE,
1317 MLX5_INLINE_MODE_L2,
1318 MLX5_INLINE_MODE_IP,
1319 MLX5_INLINE_MODE_TCP_UDP,
1320 };
1321
1322 enum {
1323 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2,
1324 };
1325
mlx5_to_sw_pkey_sz(int pkey_sz)1326 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1327 {
1328 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1329 return 0;
1330 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1331 }
1332
1333 struct mlx5_ifc_mcia_reg_bits {
1334 u8 l[0x1];
1335 u8 reserved_0[0x7];
1336 u8 module[0x8];
1337 u8 reserved_1[0x8];
1338 u8 status[0x8];
1339
1340 u8 i2c_device_address[0x8];
1341 u8 page_number[0x8];
1342 u8 device_address[0x10];
1343
1344 u8 reserved_2[0x10];
1345 u8 size[0x10];
1346
1347 u8 reserved_3[0x20];
1348
1349 u8 dword_0[0x20];
1350 u8 dword_1[0x20];
1351 u8 dword_2[0x20];
1352 u8 dword_3[0x20];
1353 u8 dword_4[0x20];
1354 u8 dword_5[0x20];
1355 u8 dword_6[0x20];
1356 u8 dword_7[0x20];
1357 u8 dword_8[0x20];
1358 u8 dword_9[0x20];
1359 u8 dword_10[0x20];
1360 u8 dword_11[0x20];
1361 };
1362
1363 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c
1364
1365 struct mlx5_mini_cqe8 {
1366 union {
1367 __be32 rx_hash_result;
1368 __be16 checksum;
1369 __be16 rsvd;
1370 struct {
1371 __be16 wqe_counter;
1372 u8 s_wqe_opcode;
1373 u8 reserved;
1374 } s_wqe_info;
1375 };
1376 __be32 byte_cnt;
1377 };
1378
1379 enum {
1380 MLX5_NO_INLINE_DATA,
1381 MLX5_INLINE_DATA32_SEG,
1382 MLX5_INLINE_DATA64_SEG,
1383 MLX5_COMPRESSED,
1384 };
1385
1386 enum mlx5_exp_cqe_zip_recv_type {
1387 MLX5_CQE_FORMAT_HASH,
1388 MLX5_CQE_FORMAT_CSUM,
1389 };
1390
1391 #define MLX5E_CQE_FORMAT_MASK 0xc
mlx5_get_cqe_format(const struct mlx5_cqe64 * cqe)1392 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe)
1393 {
1394 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2;
1395 }
1396
1397 /* 8 regular priorities + 1 for multicast */
1398 #define MLX5_NUM_BYPASS_FTS 9
1399
1400 #endif /* MLX5_DEVICE_H */
1401