1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37 #ifndef MLX4_H
38 #define MLX4_H
39
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
46 #include <linux/device.h>
47 #include <linux/rwsem.h>
48 #include <linux/mlx4/device.h>
49 #include <linux/mlx4/driver.h>
50 #include <linux/mlx4/doorbell.h>
51 #include <linux/mlx4/cmd.h>
52
53 #define DRV_NAME "mlx4_core"
54 #define PFX DRV_NAME ": "
55 #define DRV_VERSION "2.1.6"
56 #define DRV_RELDATE __DATE__
57
58 #define DRV_STACK_NAME "Linux-MLNX_OFED"
59 #define DRV_STACK_VERSION "2.1"
60 #define DRV_NAME_FOR_FW DRV_STACK_NAME","DRV_STACK_VERSION
61
62 #define MLX4_FS_UDP_UC_EN (1 << 1)
63 #define MLX4_FS_TCP_UC_EN (1 << 2)
64 #define MLX4_FS_NUM_OF_L2_ADDR 8
65 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
66 #define MLX4_FS_NUM_MCG (1 << 17)
67
68 struct mlx4_set_port_prio2tc_context {
69 u8 prio2tc[4];
70 };
71
72 struct mlx4_port_scheduler_tc_cfg_be {
73 __be16 pg;
74 __be16 bw_precentage;
75 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
76 __be16 max_bw_value;
77 };
78
79 struct mlx4_set_port_scheduler_context {
80 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
81 };
82
83 enum {
84 MLX4_HCR_BASE = 0x80680,
85 MLX4_HCR_SIZE = 0x0001c,
86 MLX4_CLR_INT_SIZE = 0x00008,
87 MLX4_SLAVE_COMM_BASE = 0x0,
88 MLX4_COMM_PAGESIZE = 0x1000,
89 MLX4_CLOCK_SIZE = 0x00008
90 };
91
92 enum {
93 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
94 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
95 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
96 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE)/16 - 2),
97 };
98
99 enum {
100 MLX4_NUM_PDS = 1 << 15
101 };
102
103 enum {
104 MLX4_CMPT_TYPE_QP = 0,
105 MLX4_CMPT_TYPE_SRQ = 1,
106 MLX4_CMPT_TYPE_CQ = 2,
107 MLX4_CMPT_TYPE_EQ = 3,
108 MLX4_CMPT_NUM_TYPE
109 };
110
111 enum {
112 MLX4_CMPT_SHIFT = 24,
113 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
114 };
115
116 enum mlx4_mpt_state {
117 MLX4_MPT_DISABLED = 0,
118 MLX4_MPT_EN_HW,
119 MLX4_MPT_EN_SW
120 };
121
122 #define MLX4_COMM_TIME 10000
123 enum {
124 MLX4_COMM_CMD_RESET,
125 MLX4_COMM_CMD_VHCR0,
126 MLX4_COMM_CMD_VHCR1,
127 MLX4_COMM_CMD_VHCR2,
128 MLX4_COMM_CMD_VHCR_EN,
129 MLX4_COMM_CMD_VHCR_POST,
130 MLX4_COMM_CMD_FLR = 254
131 };
132
133 /*The flag indicates that the slave should delay the RESET cmd*/
134 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
135 /*indicates how many retries will be done if we are in the middle of FLR*/
136 #define NUM_OF_RESET_RETRIES 10
137 #define SLEEP_TIME_IN_RESET (2 * 1000)
138 enum mlx4_resource {
139 RES_QP,
140 RES_CQ,
141 RES_SRQ,
142 RES_XRCD,
143 RES_MPT,
144 RES_MTT,
145 RES_MAC,
146 RES_VLAN,
147 RES_NPORT_ID,
148 RES_COUNTER,
149 RES_FS_RULE,
150 RES_EQ,
151 MLX4_NUM_OF_RESOURCE_TYPE
152 };
153
154 enum mlx4_alloc_mode {
155 RES_OP_RESERVE,
156 RES_OP_RESERVE_AND_MAP,
157 RES_OP_MAP_ICM,
158 };
159
160 enum mlx4_res_tracker_free_type {
161 RES_TR_FREE_ALL,
162 RES_TR_FREE_SLAVES_ONLY,
163 RES_TR_FREE_STRUCTS_ONLY,
164 };
165
166 /*
167 *Virtual HCR structures.
168 * mlx4_vhcr is the sw representation, in machine endianess
169 *
170 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
171 * to FW to go through communication channel.
172 * It is big endian, and has the same structure as the physical HCR
173 * used by command interface
174 */
175 struct mlx4_vhcr {
176 u64 in_param;
177 u64 out_param;
178 u32 in_modifier;
179 u32 errno;
180 u16 op;
181 u16 token;
182 u8 op_modifier;
183 u8 e_bit;
184 };
185
186 struct mlx4_vhcr_cmd {
187 __be64 in_param;
188 __be32 in_modifier;
189 u32 reserved1;
190 __be64 out_param;
191 __be16 token;
192 u16 reserved;
193 u8 status;
194 u8 flags;
195 __be16 opcode;
196 } __packed;
197
198 struct mlx4_cmd_info {
199 u16 opcode;
200 bool has_inbox;
201 bool has_outbox;
202 bool out_is_imm;
203 bool encode_slave_id;
204 bool skip_err_print;
205 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
206 struct mlx4_cmd_mailbox *inbox);
207 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
208 struct mlx4_cmd_mailbox *inbox,
209 struct mlx4_cmd_mailbox *outbox,
210 struct mlx4_cmd_info *cmd);
211 };
212
213 enum {
214 MLX4_DEBUG_MASK_CMD_TIME = 0x100,
215 };
216
217 #ifdef CONFIG_MLX4_DEBUG
218 extern int mlx4_debug_level;
219 #else /* CONFIG_MLX4_DEBUG */
220 #define mlx4_debug_level (0)
221 #endif /* CONFIG_MLX4_DEBUG */
222
223 #define mlx4_dbg(mdev, format, arg...) \
224 do { \
225 if (mlx4_debug_level) \
226 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
227 } while (0)
228
229 #define mlx4_err(mdev, format, arg...) \
230 dev_err(&mdev->pdev->dev, format, ##arg)
231 #define mlx4_info(mdev, format, arg...) \
232 dev_info(&mdev->pdev->dev, format, ##arg)
233 #define mlx4_warn(mdev, format, arg...) \
234 dev_warn(&mdev->pdev->dev, format, ##arg)
235
236 extern int mlx4_log_num_mgm_entry_size;
237 extern int log_mtts_per_seg;
238 extern int mlx4_blck_lb;
239 extern int mlx4_set_4k_mtu;
240
241 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
242 #define ALL_SLAVES 0xff
243
244 struct mlx4_bitmap {
245 u32 last;
246 u32 top;
247 u32 max;
248 u32 reserved_top;
249 u32 mask;
250 u32 avail;
251 spinlock_t lock;
252 unsigned long *table;
253 };
254
255 struct mlx4_buddy {
256 unsigned long **bits;
257 unsigned int *num_free;
258 u32 max_order;
259 spinlock_t lock;
260 };
261
262 struct mlx4_icm;
263
264 struct mlx4_icm_table {
265 u64 virt;
266 int num_icm;
267 u32 num_obj;
268 int obj_size;
269 int lowmem;
270 int coherent;
271 struct mutex mutex;
272 struct mlx4_icm **icm;
273 };
274
275 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
276 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
277 #define MLX4_MPT_FLAG_MIO (1 << 17)
278 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
279 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
280 #define MLX4_MPT_FLAG_REGION (1 << 8)
281
282 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
283 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
284 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
285
286 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
287
288 #define MLX4_MPT_STATUS_SW 0xF0
289 #define MLX4_MPT_STATUS_HW 0x00
290
291 /*
292 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
293 */
294 struct mlx4_mpt_entry {
295 __be32 flags;
296 __be32 qpn;
297 __be32 key;
298 __be32 pd_flags;
299 __be64 start;
300 __be64 length;
301 __be32 lkey;
302 __be32 win_cnt;
303 u8 reserved1[3];
304 u8 mtt_rep;
305 __be64 mtt_addr;
306 __be32 mtt_sz;
307 __be32 entity_size;
308 __be32 first_byte_offset;
309 } __packed;
310
311 /*
312 * Must be packed because start is 64 bits but only aligned to 32 bits.
313 */
314 struct mlx4_eq_context {
315 __be32 flags;
316 u16 reserved1[3];
317 __be16 page_offset;
318 u8 log_eq_size;
319 u8 reserved2[4];
320 u8 eq_period;
321 u8 reserved3;
322 u8 eq_max_count;
323 u8 reserved4[3];
324 u8 intr;
325 u8 log_page_size;
326 u8 reserved5[2];
327 u8 mtt_base_addr_h;
328 __be32 mtt_base_addr_l;
329 u32 reserved6[2];
330 __be32 consumer_index;
331 __be32 producer_index;
332 u32 reserved7[4];
333 };
334
335 struct mlx4_cq_context {
336 __be32 flags;
337 u16 reserved1[3];
338 __be16 page_offset;
339 __be32 logsize_usrpage;
340 __be16 cq_period;
341 __be16 cq_max_count;
342 u8 reserved2[3];
343 u8 comp_eqn;
344 u8 log_page_size;
345 u8 reserved3[2];
346 u8 mtt_base_addr_h;
347 __be32 mtt_base_addr_l;
348 __be32 last_notified_index;
349 __be32 solicit_producer_index;
350 __be32 consumer_index;
351 __be32 producer_index;
352 u32 reserved4[2];
353 __be64 db_rec_addr;
354 };
355
356 struct mlx4_srq_context {
357 __be32 state_logsize_srqn;
358 u8 logstride;
359 u8 reserved1;
360 __be16 xrcd;
361 __be32 pg_offset_cqn;
362 u32 reserved2;
363 u8 log_page_size;
364 u8 reserved3[2];
365 u8 mtt_base_addr_h;
366 __be32 mtt_base_addr_l;
367 __be32 pd;
368 __be16 limit_watermark;
369 __be16 wqe_cnt;
370 u16 reserved4;
371 __be16 wqe_counter;
372 u32 reserved5;
373 __be64 db_rec_addr;
374 };
375
376 struct mlx4_eq {
377 struct mlx4_dev *dev;
378 void __iomem *doorbell;
379 int eqn;
380 u32 cons_index;
381 u16 irq;
382 u16 have_irq;
383 int nent;
384 struct mlx4_buf_list *page_list;
385 struct mlx4_mtt mtt;
386 };
387
388 struct mlx4_slave_eqe {
389 u8 type;
390 u8 port;
391 u32 param;
392 };
393
394 struct mlx4_slave_event_eq_info {
395 int eqn;
396 u16 token;
397 };
398
399 struct mlx4_profile {
400 int num_qp;
401 int rdmarc_per_qp;
402 int num_srq;
403 int num_cq;
404 int num_mcg;
405 int num_mpt;
406 unsigned num_mtt_segs;
407 };
408
409 struct mlx4_fw {
410 u64 clr_int_base;
411 u64 catas_offset;
412 u64 comm_base;
413 u64 clock_offset;
414 struct mlx4_icm *fw_icm;
415 struct mlx4_icm *aux_icm;
416 u32 catas_size;
417 u16 fw_pages;
418 u8 clr_int_bar;
419 u8 catas_bar;
420 u8 comm_bar;
421 u8 clock_bar;
422 };
423
424 struct mlx4_comm {
425 u32 slave_write;
426 u32 slave_read;
427 };
428
429 enum {
430 MLX4_MCAST_CONFIG = 0,
431 MLX4_MCAST_DISABLE = 1,
432 MLX4_MCAST_ENABLE = 2,
433 };
434
435 #define VLAN_FLTR_SIZE 128
436
437 struct mlx4_vlan_fltr {
438 __be32 entry[VLAN_FLTR_SIZE];
439 };
440
441 struct mlx4_mcast_entry {
442 struct list_head list;
443 u64 addr;
444 };
445
446 struct mlx4_promisc_qp {
447 struct list_head list;
448 u32 qpn;
449 };
450
451 struct mlx4_steer_index {
452 struct list_head list;
453 unsigned int index;
454 struct list_head duplicates;
455 };
456
457 #define MLX4_EVENT_TYPES_NUM 64
458
459 struct mlx4_slave_state {
460 u8 comm_toggle;
461 u8 last_cmd;
462 u8 init_port_mask;
463 bool active;
464 bool old_vlan_api;
465 u8 function;
466 dma_addr_t vhcr_dma;
467 u16 mtu[MLX4_MAX_PORTS + 1];
468 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
469 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
470 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
471 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
472 /* event type to eq number lookup */
473 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
474 u16 eq_pi;
475 u16 eq_ci;
476 spinlock_t lock;
477 /*initialized via the kzalloc*/
478 u8 is_slave_going_down;
479 u32 cookie;
480 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
481 };
482
483 #define MLX4_VGT 4095
484 #define NO_INDX (-1)
485
486
487 struct mlx4_vport_state {
488 u64 mac;
489 u16 default_vlan;
490 u8 default_qos;
491 u32 tx_rate;
492 bool spoofchk;
493 u32 link_state;
494 };
495
496 struct mlx4_vf_admin_state {
497 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
498 };
499
500 struct mlx4_vport_oper_state {
501 struct mlx4_vport_state state;
502 int mac_idx;
503 int vlan_idx;
504 };
505 struct mlx4_vf_oper_state {
506 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
507 };
508
509 struct slave_list {
510 struct mutex mutex;
511 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
512 };
513
514 struct resource_allocator {
515 spinlock_t alloc_lock;
516 union {
517 int res_reserved;
518 int res_port_rsvd[MLX4_MAX_PORTS];
519 };
520 union {
521 int res_free;
522 int res_port_free[MLX4_MAX_PORTS];
523 };
524 int *quota;
525 int *allocated;
526 int *guaranteed;
527 };
528
529 struct mlx4_resource_tracker {
530 spinlock_t lock;
531 /* tree for each resources */
532 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
533 /* num_of_slave's lists, one per slave */
534 struct slave_list *slave_list;
535 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
536 };
537
538 #define SLAVE_EVENT_EQ_SIZE 128
539 struct mlx4_slave_event_eq {
540 u32 eqn;
541 u32 cons;
542 u32 prod;
543 spinlock_t event_lock;
544 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
545 };
546
547 struct mlx4_master_qp0_state {
548 int proxy_qp0_active;
549 int qp0_active;
550 int port_active;
551 };
552
553 struct mlx4_mfunc_master_ctx {
554 struct mlx4_slave_state *slave_state;
555 struct mlx4_vf_admin_state *vf_admin;
556 struct mlx4_vf_oper_state *vf_oper;
557 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
558 int init_port_ref[MLX4_MAX_PORTS + 1];
559 u16 max_mtu[MLX4_MAX_PORTS + 1];
560 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
561 struct mlx4_resource_tracker res_tracker;
562 struct workqueue_struct *comm_wq;
563 struct work_struct comm_work;
564 struct work_struct arm_comm_work;
565 struct work_struct slave_event_work;
566 struct work_struct slave_flr_event_work;
567 spinlock_t slave_state_lock;
568 __be32 comm_arm_bit_vector[4];
569 struct mlx4_eqe cmd_eqe;
570 struct mlx4_slave_event_eq slave_eq;
571 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
572 };
573
574 struct mlx4_mfunc {
575 struct mlx4_comm __iomem *comm;
576 struct mlx4_vhcr_cmd *vhcr;
577 dma_addr_t vhcr_dma;
578
579 struct mlx4_mfunc_master_ctx master;
580 };
581
582 #define MGM_QPN_MASK 0x00FFFFFF
583 #define MGM_BLCK_LB_BIT 30
584
585 struct mlx4_mgm {
586 __be32 next_gid_index;
587 __be32 members_count;
588 u32 reserved[2];
589 u8 gid[16];
590 __be32 qp[MLX4_MAX_QP_PER_MGM];
591 };
592
593 struct mlx4_cmd {
594 struct pci_pool *pool;
595 void __iomem *hcr;
596 struct mutex hcr_mutex;
597 struct mutex slave_cmd_mutex;
598 struct semaphore poll_sem;
599 struct semaphore event_sem;
600 struct rw_semaphore switch_sem;
601 int max_cmds;
602 spinlock_t context_lock;
603 int free_head;
604 struct mlx4_cmd_context *context;
605 u16 token_mask;
606 u8 use_events;
607 u8 toggle;
608 u8 comm_toggle;
609 };
610
611 enum {
612 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
613 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
614 };
615 struct mlx4_vf_immed_vlan_work {
616 struct work_struct work;
617 struct mlx4_priv *priv;
618 int flags;
619 int slave;
620 int vlan_ix;
621 int orig_vlan_ix;
622 u8 port;
623 u8 qos;
624 u16 vlan_id;
625 u16 orig_vlan_id;
626 };
627
628
629 struct mlx4_uar_table {
630 struct mlx4_bitmap bitmap;
631 };
632
633 struct mlx4_mr_table {
634 struct mlx4_bitmap mpt_bitmap;
635 struct mlx4_buddy mtt_buddy;
636 u64 mtt_base;
637 u64 mpt_base;
638 struct mlx4_icm_table mtt_table;
639 struct mlx4_icm_table dmpt_table;
640 };
641
642 struct mlx4_cq_table {
643 struct mlx4_bitmap bitmap;
644 spinlock_t lock;
645 rwlock_t cq_table_lock;
646 struct radix_tree_root tree;
647 struct mlx4_icm_table table;
648 struct mlx4_icm_table cmpt_table;
649 };
650
651 struct mlx4_eq_table {
652 struct mlx4_bitmap bitmap;
653 char *irq_names;
654 void __iomem *clr_int;
655 void __iomem **uar_map;
656 u32 clr_mask;
657 struct mlx4_eq *eq;
658 struct mlx4_icm_table table;
659 struct mlx4_icm_table cmpt_table;
660 int have_irq;
661 u8 inta_pin;
662 };
663
664 struct mlx4_srq_table {
665 struct mlx4_bitmap bitmap;
666 spinlock_t lock;
667 struct radix_tree_root tree;
668 struct mlx4_icm_table table;
669 struct mlx4_icm_table cmpt_table;
670 };
671
672 struct mlx4_qp_table {
673 struct mlx4_bitmap bitmap;
674 u32 rdmarc_base;
675 int rdmarc_shift;
676 spinlock_t lock;
677 struct mlx4_icm_table qp_table;
678 struct mlx4_icm_table auxc_table;
679 struct mlx4_icm_table altc_table;
680 struct mlx4_icm_table rdmarc_table;
681 struct mlx4_icm_table cmpt_table;
682 };
683
684 struct mlx4_mcg_table {
685 struct mutex mutex;
686 struct mlx4_bitmap bitmap;
687 struct mlx4_icm_table table;
688 };
689
690 struct mlx4_catas_err {
691 u32 __iomem *map;
692 struct timer_list timer;
693 struct list_head list;
694 };
695
696 #define MLX4_MAX_MAC_NUM 128
697 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
698
699 struct mlx4_mac_table {
700 __be64 entries[MLX4_MAX_MAC_NUM];
701 int refs[MLX4_MAX_MAC_NUM];
702 struct mutex mutex;
703 int total;
704 int max;
705 };
706
707 #define MLX4_MAX_VLAN_NUM 128
708 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
709
710 struct mlx4_vlan_table {
711 __be32 entries[MLX4_MAX_VLAN_NUM];
712 int refs[MLX4_MAX_VLAN_NUM];
713 struct mutex mutex;
714 int total;
715 int max;
716 };
717
718 #define SET_PORT_GEN_ALL_VALID 0x7
719 #define SET_PORT_PROMISC_SHIFT 31
720 #define SET_PORT_MC_PROMISC_SHIFT 30
721
722 enum {
723 MCAST_DIRECT_ONLY = 0,
724 MCAST_DIRECT = 1,
725 MCAST_DEFAULT = 2
726 };
727
728
729 struct mlx4_set_port_general_context {
730 u8 reserved[3];
731 u8 flags;
732 u16 reserved2;
733 __be16 mtu;
734 u8 pptx;
735 u8 pfctx;
736 u16 reserved3;
737 u8 pprx;
738 u8 pfcrx;
739 u16 reserved4;
740 };
741
742 struct mlx4_set_port_rqp_calc_context {
743 __be32 base_qpn;
744 u8 rererved;
745 u8 n_mac;
746 u8 n_vlan;
747 u8 n_prio;
748 u8 reserved2[3];
749 u8 mac_miss;
750 u8 intra_no_vlan;
751 u8 no_vlan;
752 u8 intra_vlan_miss;
753 u8 vlan_miss;
754 u8 reserved3[3];
755 u8 no_vlan_prio;
756 __be32 promisc;
757 __be32 mcast;
758 };
759
760 struct mlx4_hca_info {
761 struct mlx4_dev *dev;
762 struct device_attribute firmware_attr;
763 struct device_attribute hca_attr;
764 struct device_attribute board_attr;
765 };
766
767 struct mlx4_port_info {
768 struct mlx4_dev *dev;
769 int port;
770 char dev_name[16];
771 struct device_attribute port_attr;
772 enum mlx4_port_type tmp_type;
773 char dev_mtu_name[16];
774 struct device_attribute port_mtu_attr;
775 struct mlx4_mac_table mac_table;
776 struct mlx4_vlan_table vlan_table;
777 int base_qpn;
778 };
779
780 struct mlx4_sense {
781 struct mlx4_dev *dev;
782 u8 do_sense_port[MLX4_MAX_PORTS + 1];
783 u8 sense_allowed[MLX4_MAX_PORTS + 1];
784 struct delayed_work sense_poll;
785 };
786
787 struct mlx4_msix_ctl {
788 u64 pool_bm;
789 struct mutex pool_lock;
790 };
791
792 struct mlx4_steer {
793 struct list_head promisc_qps[MLX4_NUM_STEERS];
794 struct list_head steer_entries[MLX4_NUM_STEERS];
795 };
796
797 enum {
798 MLX4_PCI_DEV_IS_VF = 1 << 0,
799 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
800 };
801
802 struct mlx4_roce_gid_entry {
803 u8 raw[16];
804 };
805
806 struct counter_index {
807 struct list_head list;
808 u32 index;
809 };
810
811 struct mlx4_counters {
812 struct mlx4_bitmap bitmap;
813 struct list_head global_port_list[MLX4_MAX_PORTS];
814 struct list_head vf_list[MLX4_MAX_NUM_VF][MLX4_MAX_PORTS];
815 struct mutex mutex;
816 };
817
818 enum {
819 MLX4_NO_RR = 0,
820 MLX4_USE_RR = 1,
821 };
822
823 struct mlx4_priv {
824 struct mlx4_dev dev;
825
826 struct list_head dev_list;
827 struct list_head ctx_list;
828 spinlock_t ctx_lock;
829
830 int pci_dev_data;
831
832 struct list_head pgdir_list;
833 struct mutex pgdir_mutex;
834
835 struct mlx4_fw fw;
836 struct mlx4_cmd cmd;
837 struct mlx4_mfunc mfunc;
838
839 struct mlx4_bitmap pd_bitmap;
840 struct mlx4_bitmap xrcd_bitmap;
841 struct mlx4_uar_table uar_table;
842 struct mlx4_mr_table mr_table;
843 struct mlx4_cq_table cq_table;
844 struct mlx4_eq_table eq_table;
845 struct mlx4_srq_table srq_table;
846 struct mlx4_qp_table qp_table;
847 struct mlx4_mcg_table mcg_table;
848 struct mlx4_counters counters_table;
849
850 struct mlx4_catas_err catas_err;
851
852 void __iomem *clr_base;
853
854 struct mlx4_uar driver_uar;
855 void __iomem *kar;
856 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
857 struct mlx4_hca_info hca_info;
858 struct mlx4_sense sense;
859 struct mutex port_mutex;
860 struct mlx4_msix_ctl msix_ctl;
861 struct mlx4_steer *steer;
862 struct list_head bf_list;
863 struct mutex bf_mutex;
864 struct io_mapping *bf_mapping;
865 void __iomem *clock_mapping;
866 int reserved_mtts;
867 int fs_hash_mode;
868 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
869 __be64 slave_node_guids[MLX4_MFUNC_MAX];
870 struct mlx4_roce_gid_entry roce_gids[MLX4_MAX_PORTS][128];
871 atomic_t opreq_count;
872 struct work_struct opreq_task;
873 };
874
mlx4_priv(struct mlx4_dev * dev)875 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
876 {
877 return container_of(dev, struct mlx4_priv, dev);
878 }
879
880 #define MLX4_SENSE_RANGE (HZ * 3)
881
882 extern struct workqueue_struct *mlx4_wq;
883
884 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
885 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
886 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
887 int align, u32 skip_mask);
888 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
889 int use_rr);
890 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
891 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
892 u32 reserved_bot, u32 resetrved_top);
893 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
894
895 int mlx4_reset(struct mlx4_dev *dev);
896
897 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
898 void mlx4_free_eq_table(struct mlx4_dev *dev);
899
900 int mlx4_init_pd_table(struct mlx4_dev *dev);
901 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
902 int mlx4_init_uar_table(struct mlx4_dev *dev);
903 int mlx4_init_mr_table(struct mlx4_dev *dev);
904 int mlx4_init_eq_table(struct mlx4_dev *dev);
905 int mlx4_init_cq_table(struct mlx4_dev *dev);
906 int mlx4_init_qp_table(struct mlx4_dev *dev);
907 int mlx4_init_srq_table(struct mlx4_dev *dev);
908 int mlx4_init_mcg_table(struct mlx4_dev *dev);
909
910 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
911 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
912 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
913 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
914 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
915 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
916 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
917 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
918 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
919 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
920 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
921 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
922 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
923 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
924 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
925 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
926 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
927 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
928 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
929 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
930 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
931
932 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
933 struct mlx4_vhcr *vhcr,
934 struct mlx4_cmd_mailbox *inbox,
935 struct mlx4_cmd_mailbox *outbox,
936 struct mlx4_cmd_info *cmd);
937 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
938 struct mlx4_vhcr *vhcr,
939 struct mlx4_cmd_mailbox *inbox,
940 struct mlx4_cmd_mailbox *outbox,
941 struct mlx4_cmd_info *cmd);
942 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
943 struct mlx4_vhcr *vhcr,
944 struct mlx4_cmd_mailbox *inbox,
945 struct mlx4_cmd_mailbox *outbox,
946 struct mlx4_cmd_info *cmd);
947 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
948 struct mlx4_vhcr *vhcr,
949 struct mlx4_cmd_mailbox *inbox,
950 struct mlx4_cmd_mailbox *outbox,
951 struct mlx4_cmd_info *cmd);
952 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
953 struct mlx4_vhcr *vhcr,
954 struct mlx4_cmd_mailbox *inbox,
955 struct mlx4_cmd_mailbox *outbox,
956 struct mlx4_cmd_info *cmd);
957 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
958 struct mlx4_vhcr *vhcr,
959 struct mlx4_cmd_mailbox *inbox,
960 struct mlx4_cmd_mailbox *outbox,
961 struct mlx4_cmd_info *cmd);
962 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
963 struct mlx4_vhcr *vhcr,
964 struct mlx4_cmd_mailbox *inbox,
965 struct mlx4_cmd_mailbox *outbox,
966 struct mlx4_cmd_info *cmd);
967 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
968 int *base, u8 flags);
969 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
970 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
971 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
972 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
973 int start_index, int npages, u64 *page_list);
974 int __mlx4_counter_alloc(struct mlx4_dev *dev, int slave, int port, u32 *idx);
975 void __mlx4_counter_free(struct mlx4_dev *dev, int slave, int port, u32 idx);
976
977 int __mlx4_slave_counters_free(struct mlx4_dev *dev, int slave);
978 int __mlx4_clear_if_stat(struct mlx4_dev *dev,
979 u8 counter_index);
980 u8 mlx4_get_default_counter_index(struct mlx4_dev *dev, int slave, int port);
981
982 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
983 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
984
985 void mlx4_start_catas_poll(struct mlx4_dev *dev);
986 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
987 void mlx4_catas_init(void);
988 int mlx4_restart_one(struct pci_dev *pdev);
989 int mlx4_register_device(struct mlx4_dev *dev);
990 void mlx4_unregister_device(struct mlx4_dev *dev);
991 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
992 unsigned long param);
993
994 struct mlx4_dev_cap;
995 struct mlx4_init_hca_param;
996
997 u64 mlx4_make_profile(struct mlx4_dev *dev,
998 struct mlx4_profile *request,
999 struct mlx4_dev_cap *dev_cap,
1000 struct mlx4_init_hca_param *init_hca);
1001 void mlx4_master_comm_channel(struct work_struct *work);
1002 void mlx4_master_arm_comm_channel(struct work_struct *work);
1003 void mlx4_gen_slave_eqe(struct work_struct *work);
1004 void mlx4_master_handle_slave_flr(struct work_struct *work);
1005
1006 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1007 struct mlx4_vhcr *vhcr,
1008 struct mlx4_cmd_mailbox *inbox,
1009 struct mlx4_cmd_mailbox *outbox,
1010 struct mlx4_cmd_info *cmd);
1011 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1012 struct mlx4_vhcr *vhcr,
1013 struct mlx4_cmd_mailbox *inbox,
1014 struct mlx4_cmd_mailbox *outbox,
1015 struct mlx4_cmd_info *cmd);
1016 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1017 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1018 struct mlx4_cmd_mailbox *outbox,
1019 struct mlx4_cmd_info *cmd);
1020 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1021 struct mlx4_vhcr *vhcr,
1022 struct mlx4_cmd_mailbox *inbox,
1023 struct mlx4_cmd_mailbox *outbox,
1024 struct mlx4_cmd_info *cmd);
1025 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1026 struct mlx4_vhcr *vhcr,
1027 struct mlx4_cmd_mailbox *inbox,
1028 struct mlx4_cmd_mailbox *outbox,
1029 struct mlx4_cmd_info *cmd);
1030 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1031 struct mlx4_vhcr *vhcr,
1032 struct mlx4_cmd_mailbox *inbox,
1033 struct mlx4_cmd_mailbox *outbox,
1034 struct mlx4_cmd_info *cmd);
1035 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1036 struct mlx4_vhcr *vhcr,
1037 struct mlx4_cmd_mailbox *inbox,
1038 struct mlx4_cmd_mailbox *outbox,
1039 struct mlx4_cmd_info *cmd);
1040 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1041 struct mlx4_vhcr *vhcr,
1042 struct mlx4_cmd_mailbox *inbox,
1043 struct mlx4_cmd_mailbox *outbox,
1044 struct mlx4_cmd_info *cmd);
1045 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1046 struct mlx4_vhcr *vhcr,
1047 struct mlx4_cmd_mailbox *inbox,
1048 struct mlx4_cmd_mailbox *outbox,
1049 struct mlx4_cmd_info *cmd);
1050 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1051 struct mlx4_vhcr *vhcr,
1052 struct mlx4_cmd_mailbox *inbox,
1053 struct mlx4_cmd_mailbox *outbox,
1054 struct mlx4_cmd_info *cmd);
1055 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1056 struct mlx4_vhcr *vhcr,
1057 struct mlx4_cmd_mailbox *inbox,
1058 struct mlx4_cmd_mailbox *outbox,
1059 struct mlx4_cmd_info *cmd);
1060 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1061 struct mlx4_vhcr *vhcr,
1062 struct mlx4_cmd_mailbox *inbox,
1063 struct mlx4_cmd_mailbox *outbox,
1064 struct mlx4_cmd_info *cmd);
1065 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1066 struct mlx4_vhcr *vhcr,
1067 struct mlx4_cmd_mailbox *inbox,
1068 struct mlx4_cmd_mailbox *outbox,
1069 struct mlx4_cmd_info *cmd);
1070 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1071 struct mlx4_vhcr *vhcr,
1072 struct mlx4_cmd_mailbox *inbox,
1073 struct mlx4_cmd_mailbox *outbox,
1074 struct mlx4_cmd_info *cmd);
1075 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1076 struct mlx4_vhcr *vhcr,
1077 struct mlx4_cmd_mailbox *inbox,
1078 struct mlx4_cmd_mailbox *outbox,
1079 struct mlx4_cmd_info *cmd);
1080 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1081 struct mlx4_vhcr *vhcr,
1082 struct mlx4_cmd_mailbox *inbox,
1083 struct mlx4_cmd_mailbox *outbox,
1084 struct mlx4_cmd_info *cmd);
1085 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1086 struct mlx4_vhcr *vhcr,
1087 struct mlx4_cmd_mailbox *inbox,
1088 struct mlx4_cmd_mailbox *outbox,
1089 struct mlx4_cmd_info *cmd);
1090 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1091 struct mlx4_vhcr *vhcr,
1092 struct mlx4_cmd_mailbox *inbox,
1093 struct mlx4_cmd_mailbox *outbox,
1094 struct mlx4_cmd_info *cmd);
1095 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1096 struct mlx4_vhcr *vhcr,
1097 struct mlx4_cmd_mailbox *inbox,
1098 struct mlx4_cmd_mailbox *outbox,
1099 struct mlx4_cmd_info *cmd);
1100 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1101 struct mlx4_vhcr *vhcr,
1102 struct mlx4_cmd_mailbox *inbox,
1103 struct mlx4_cmd_mailbox *outbox,
1104 struct mlx4_cmd_info *cmd);
1105 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1106 struct mlx4_vhcr *vhcr,
1107 struct mlx4_cmd_mailbox *inbox,
1108 struct mlx4_cmd_mailbox *outbox,
1109 struct mlx4_cmd_info *cmd);
1110 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1111 struct mlx4_vhcr *vhcr,
1112 struct mlx4_cmd_mailbox *inbox,
1113 struct mlx4_cmd_mailbox *outbox,
1114 struct mlx4_cmd_info *cmd);
1115 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1116 struct mlx4_vhcr *vhcr,
1117 struct mlx4_cmd_mailbox *inbox,
1118 struct mlx4_cmd_mailbox *outbox,
1119 struct mlx4_cmd_info *cmd);
1120 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1121 struct mlx4_vhcr *vhcr,
1122 struct mlx4_cmd_mailbox *inbox,
1123 struct mlx4_cmd_mailbox *outbox,
1124 struct mlx4_cmd_info *cmd);
1125 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1126 struct mlx4_vhcr *vhcr,
1127 struct mlx4_cmd_mailbox *inbox,
1128 struct mlx4_cmd_mailbox *outbox,
1129 struct mlx4_cmd_info *cmd);
1130 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1131 struct mlx4_vhcr *vhcr,
1132 struct mlx4_cmd_mailbox *inbox,
1133 struct mlx4_cmd_mailbox *outbox,
1134 struct mlx4_cmd_info *cmd);
1135 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1136 struct mlx4_vhcr *vhcr,
1137 struct mlx4_cmd_mailbox *inbox,
1138 struct mlx4_cmd_mailbox *outbox,
1139 struct mlx4_cmd_info *cmd);
1140
1141 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1142
1143 int mlx4_cmd_init(struct mlx4_dev *dev);
1144 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1145 int mlx4_multi_func_init(struct mlx4_dev *dev);
1146 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1147 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1148 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1149 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1150
1151 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1152 unsigned long timeout);
1153
1154 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1155 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1156
1157 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1158
1159 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1160
1161 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1162
1163 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1164 enum mlx4_port_type *type);
1165 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1166 enum mlx4_port_type *stype,
1167 enum mlx4_port_type *defaults);
1168 void mlx4_start_sense(struct mlx4_dev *dev);
1169 void mlx4_stop_sense(struct mlx4_dev *dev);
1170 void mlx4_sense_init(struct mlx4_dev *dev);
1171 int mlx4_check_port_params(struct mlx4_dev *dev,
1172 enum mlx4_port_type *port_type);
1173 int mlx4_change_port_types(struct mlx4_dev *dev,
1174 enum mlx4_port_type *port_types);
1175
1176 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1177 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1178 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1179 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1180
1181 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1182 /* resource tracker functions*/
1183 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1184 enum mlx4_resource resource_type,
1185 u64 resource_id, int *slave);
1186 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1187 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1188
1189 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1190 enum mlx4_res_tracker_free_type type);
1191
1192 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1193 struct mlx4_vhcr *vhcr,
1194 struct mlx4_cmd_mailbox *inbox,
1195 struct mlx4_cmd_mailbox *outbox,
1196 struct mlx4_cmd_info *cmd);
1197 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1198 struct mlx4_vhcr *vhcr,
1199 struct mlx4_cmd_mailbox *inbox,
1200 struct mlx4_cmd_mailbox *outbox,
1201 struct mlx4_cmd_info *cmd);
1202 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1203 struct mlx4_vhcr *vhcr,
1204 struct mlx4_cmd_mailbox *inbox,
1205 struct mlx4_cmd_mailbox *outbox,
1206 struct mlx4_cmd_info *cmd);
1207 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1208 struct mlx4_vhcr *vhcr,
1209 struct mlx4_cmd_mailbox *inbox,
1210 struct mlx4_cmd_mailbox *outbox,
1211 struct mlx4_cmd_info *cmd);
1212 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1213 struct mlx4_vhcr *vhcr,
1214 struct mlx4_cmd_mailbox *inbox,
1215 struct mlx4_cmd_mailbox *outbox,
1216 struct mlx4_cmd_info *cmd);
1217 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1218 struct mlx4_vhcr *vhcr,
1219 struct mlx4_cmd_mailbox *inbox,
1220 struct mlx4_cmd_mailbox *outbox,
1221 struct mlx4_cmd_info *cmd);
1222 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1223
1224 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1225 int *gid_tbl_len, int *pkey_tbl_len);
1226
1227 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1228 struct mlx4_vhcr *vhcr,
1229 struct mlx4_cmd_mailbox *inbox,
1230 struct mlx4_cmd_mailbox *outbox,
1231 struct mlx4_cmd_info *cmd);
1232
1233 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1234 struct mlx4_vhcr *vhcr,
1235 struct mlx4_cmd_mailbox *inbox,
1236 struct mlx4_cmd_mailbox *outbox,
1237 struct mlx4_cmd_info *cmd);
1238 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1239 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1240 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1241 int block_mcast_loopback, enum mlx4_protocol prot,
1242 enum mlx4_steer_type steer);
1243 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1244 u8 gid[16], u8 port,
1245 int block_mcast_loopback,
1246 enum mlx4_protocol prot, u64 *reg_id);
1247 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1248 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1249 struct mlx4_vhcr *vhcr,
1250 struct mlx4_cmd_mailbox *inbox,
1251 struct mlx4_cmd_mailbox *outbox,
1252 struct mlx4_cmd_info *cmd);
1253 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1254 struct mlx4_vhcr *vhcr,
1255 struct mlx4_cmd_mailbox *inbox,
1256 struct mlx4_cmd_mailbox *outbox,
1257 struct mlx4_cmd_info *cmd);
1258 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1259 int port, void *buf);
1260 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1261 struct mlx4_vhcr *vhcr,
1262 struct mlx4_cmd_mailbox *inbox,
1263 struct mlx4_cmd_mailbox *outbox,
1264 struct mlx4_cmd_info *cmd);
1265 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1266 struct mlx4_vhcr *vhcr,
1267 struct mlx4_cmd_mailbox *inbox,
1268 struct mlx4_cmd_mailbox *outbox,
1269 struct mlx4_cmd_info *cmd);
1270 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1271 struct mlx4_vhcr *vhcr,
1272 struct mlx4_cmd_mailbox *inbox,
1273 struct mlx4_cmd_mailbox *outbox,
1274 struct mlx4_cmd_info *cmd);
1275 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1276 struct mlx4_vhcr *vhcr,
1277 struct mlx4_cmd_mailbox *inbox,
1278 struct mlx4_cmd_mailbox *outbox,
1279 struct mlx4_cmd_info *cmd);
1280 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1281 struct mlx4_vhcr *vhcr,
1282 struct mlx4_cmd_mailbox *inbox,
1283 struct mlx4_cmd_mailbox *outbox,
1284 struct mlx4_cmd_info *cmd);
1285 int mlx4_MOD_STAT_CFG_wrapper(struct mlx4_dev *dev, int slave,
1286 struct mlx4_vhcr *vhcr,
1287 struct mlx4_cmd_mailbox *inbox,
1288 struct mlx4_cmd_mailbox *outbox,
1289 struct mlx4_cmd_info *cmd);
1290
1291 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1292 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1293
set_param_l(u64 * arg,u32 val)1294 static inline void set_param_l(u64 *arg, u32 val)
1295 {
1296 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1297 }
1298
set_param_h(u64 * arg,u32 val)1299 static inline void set_param_h(u64 *arg, u32 val)
1300 {
1301 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1302 }
1303
get_param_l(u64 * arg)1304 static inline u32 get_param_l(u64 *arg)
1305 {
1306 return (u32) (*arg & 0xffffffff);
1307 }
1308
get_param_h(u64 * arg)1309 static inline u32 get_param_h(u64 *arg)
1310 {
1311 return (u32)(*arg >> 32);
1312 }
1313
mlx4_tlock(struct mlx4_dev * dev)1314 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1315 {
1316 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1317 }
1318
1319 #define NOT_MASKED_PD_BITS 17
1320
1321 void sys_tune_init(void);
1322 void sys_tune_fini(void);
1323
1324 void mlx4_init_quotas(struct mlx4_dev *dev);
1325
1326 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave);
1327 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave);
1328 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1329
1330 #endif /* MLX4_H */
1331