1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the Mips specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H 15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H 16 17 #include "MCTargetDesc/MipsABIInfo.h" 18 #include "MipsFrameLowering.h" 19 #include "MipsISelLowering.h" 20 #include "MipsInstrInfo.h" 21 #include "llvm/IR/DataLayout.h" 22 #include "llvm/MC/MCInstrItineraries.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Target/TargetSelectionDAGInfo.h" 25 #include "llvm/Target/TargetSubtargetInfo.h" 26 #include <string> 27 28 #define GET_SUBTARGETINFO_HEADER 29 #include "MipsGenSubtargetInfo.inc" 30 31 namespace llvm { 32 class StringRef; 33 34 class MipsTargetMachine; 35 36 class MipsSubtarget : public MipsGenSubtargetInfo { 37 virtual void anchor(); 38 39 enum MipsArchEnum { 40 MipsDefault, 41 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max, 42 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6 43 }; 44 45 // Mips architecture version 46 MipsArchEnum MipsArchVersion; 47 48 // IsLittle - The target is Little Endian 49 bool IsLittle; 50 51 // IsSoftFloat - The target does not support any floating point instructions. 52 bool IsSoftFloat; 53 54 // IsSingleFloat - The target only supports single precision float 55 // point operations. This enable the target to use all 32 32-bit 56 // floating point registers instead of only using even ones. 57 bool IsSingleFloat; 58 59 // IsFPXX - MIPS O32 modeless ABI. 60 bool IsFPXX; 61 62 // NoABICalls - Disable SVR4-style position-independent code. 63 bool NoABICalls; 64 65 // IsFP64bit - The target processor has 64-bit floating point registers. 66 bool IsFP64bit; 67 68 /// Are odd single-precision registers permitted? 69 /// This corresponds to -modd-spreg and -mno-odd-spreg 70 bool UseOddSPReg; 71 72 // IsNan2008 - IEEE 754-2008 NaN encoding. 73 bool IsNaN2008bit; 74 75 // IsFP64bit - General-purpose registers are 64 bits wide 76 bool IsGP64bit; 77 78 // HasVFPU - Processor has a vector floating point unit. 79 bool HasVFPU; 80 81 // CPU supports cnMIPS (Cavium Networks Octeon CPU). 82 bool HasCnMips; 83 84 // isLinux - Target system is Linux. Is false we consider ELFOS for now. 85 bool IsLinux; 86 87 // UseSmallSection - Small section is used. 88 bool UseSmallSection; 89 90 /// Features related to the presence of specific instructions. 91 92 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32 93 bool HasMips3_32; 94 95 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2 96 bool HasMips3_32r2; 97 98 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32 99 bool HasMips4_32; 100 101 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2 102 bool HasMips4_32r2; 103 104 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2 105 bool HasMips5_32r2; 106 107 // InMips16 -- can process Mips16 instructions 108 bool InMips16Mode; 109 110 // Mips16 hard float 111 bool InMips16HardFloat; 112 113 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode 114 bool PreviousInMips16Mode; 115 116 // InMicroMips -- can process MicroMips instructions 117 bool InMicroMipsMode; 118 119 // HasDSP, HasDSPR2 -- supports DSP ASE. 120 bool HasDSP, HasDSPR2; 121 122 // Allow mixed Mips16 and Mips32 in one source file 123 bool AllowMixed16_32; 124 125 // Optimize for space by compiling all functions as Mips 16 unless 126 // it needs floating point. Functions needing floating point are 127 // compiled as Mips32 128 bool Os16; 129 130 // HasMSA -- supports MSA ASE. 131 bool HasMSA; 132 133 InstrItineraryData InstrItins; 134 135 // We can override the determination of whether we are in mips16 mode 136 // as from the command line 137 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode; 138 139 const MipsTargetMachine &TM; 140 141 Triple TargetTriple; 142 143 const TargetSelectionDAGInfo TSInfo; 144 std::unique_ptr<const MipsInstrInfo> InstrInfo; 145 std::unique_ptr<const MipsFrameLowering> FrameLowering; 146 std::unique_ptr<const MipsTargetLowering> TLInfo; 147 148 public: 149 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU. 150 bool enablePostRAScheduler() const override; 151 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override; 152 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override; 153 154 /// Only O32 and EABI supported right now. 155 bool isABI_EABI() const; 156 bool isABI_N64() const; 157 bool isABI_N32() const; 158 bool isABI_O32() const; 159 const MipsABIInfo &getABI() const; isABI_FPXX()160 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; } 161 162 /// This constructor initializes the data members to match that 163 /// of the specified triple. 164 MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, 165 bool little, const MipsTargetMachine &TM); 166 167 /// ParseSubtargetFeatures - Parses features string setting specified 168 /// subtarget options. Definition of function is auto generated by tblgen. 169 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 170 hasMips1()171 bool hasMips1() const { return MipsArchVersion >= Mips1; } hasMips2()172 bool hasMips2() const { return MipsArchVersion >= Mips2; } hasMips3()173 bool hasMips3() const { return MipsArchVersion >= Mips3; } hasMips4()174 bool hasMips4() const { return MipsArchVersion >= Mips4; } hasMips5()175 bool hasMips5() const { return MipsArchVersion >= Mips5; } hasMips4_32()176 bool hasMips4_32() const { return HasMips4_32; } hasMips4_32r2()177 bool hasMips4_32r2() const { return HasMips4_32r2; } hasMips32()178 bool hasMips32() const { 179 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) || 180 hasMips64(); 181 } hasMips32r2()182 bool hasMips32r2() const { 183 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) || 184 hasMips64r2(); 185 } hasMips32r3()186 bool hasMips32r3() const { 187 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) || 188 hasMips64r2(); 189 } hasMips32r5()190 bool hasMips32r5() const { 191 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) || 192 hasMips64r2(); 193 } hasMips32r6()194 bool hasMips32r6() const { 195 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) || 196 hasMips64r6(); 197 } hasMips64()198 bool hasMips64() const { return MipsArchVersion >= Mips64; } hasMips64r2()199 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; } hasMips64r3()200 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; } hasMips64r5()201 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; } hasMips64r6()202 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; } 203 hasCnMips()204 bool hasCnMips() const { return HasCnMips; } 205 isLittle()206 bool isLittle() const { return IsLittle; } isABICalls()207 bool isABICalls() const { return !NoABICalls; } isFPXX()208 bool isFPXX() const { return IsFPXX; } isFP64bit()209 bool isFP64bit() const { return IsFP64bit; } useOddSPReg()210 bool useOddSPReg() const { return UseOddSPReg; } noOddSPReg()211 bool noOddSPReg() const { return !UseOddSPReg; } isNaN2008()212 bool isNaN2008() const { return IsNaN2008bit; } isGP64bit()213 bool isGP64bit() const { return IsGP64bit; } isGP32bit()214 bool isGP32bit() const { return !IsGP64bit; } getGPRSizeInBytes()215 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; } isSingleFloat()216 bool isSingleFloat() const { return IsSingleFloat; } hasVFPU()217 bool hasVFPU() const { return HasVFPU; } inMips16Mode()218 bool inMips16Mode() const { return InMips16Mode; } inMips16ModeDefault()219 bool inMips16ModeDefault() const { 220 return InMips16Mode; 221 } 222 // Hard float for mips16 means essentially to compile as soft float 223 // but to use a runtime library for soft float that is written with 224 // native mips32 floating point instructions (those runtime routines 225 // run in mips32 hard float mode). inMips16HardFloat()226 bool inMips16HardFloat() const { 227 return inMips16Mode() && InMips16HardFloat; 228 } inMicroMipsMode()229 bool inMicroMipsMode() const { return InMicroMipsMode; } inMicroMips32r6Mode()230 bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); } hasDSP()231 bool hasDSP() const { return HasDSP; } hasDSPR2()232 bool hasDSPR2() const { return HasDSPR2; } hasMSA()233 bool hasMSA() const { return HasMSA; } useSmallSection()234 bool useSmallSection() const { return UseSmallSection; } 235 hasStandardEncoding()236 bool hasStandardEncoding() const { return !inMips16Mode(); } 237 useSoftFloat()238 bool useSoftFloat() const { return IsSoftFloat; } 239 enableLongBranchPass()240 bool enableLongBranchPass() const { 241 return hasStandardEncoding() || allowMixed16_32(); 242 } 243 244 /// Features related to the presence of specific instructions. hasExtractInsert()245 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); } hasMTHC1()246 bool hasMTHC1() const { return hasMips32r2(); } 247 allowMixed16_32()248 bool allowMixed16_32() const { return inMips16ModeDefault() | 249 AllowMixed16_32; } 250 os16()251 bool os16() const { return Os16; } 252 isTargetNaCl()253 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } 254 255 // for now constant islands are on for the whole compilation unit but we only 256 // really use them if in addition we are in mips16 mode 257 static bool useConstantIslands(); 258 stackAlignment()259 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; } 260 261 // Grab relocation model 262 Reloc::Model getRelocationModel() const; 263 264 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS, 265 const TargetMachine &TM); 266 267 /// Does the system support unaligned memory access. 268 /// 269 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not 270 /// specify which component of the system provides it. Hardware, software, and 271 /// hybrid implementations are all valid. systemSupportsUnalignedAccess()272 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); } 273 274 // Set helper classes 275 void setHelperClassesMips16(); 276 void setHelperClassesMipsSE(); 277 getSelectionDAGInfo()278 const TargetSelectionDAGInfo *getSelectionDAGInfo() const override { 279 return &TSInfo; 280 } getInstrInfo()281 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); } getFrameLowering()282 const TargetFrameLowering *getFrameLowering() const override { 283 return FrameLowering.get(); 284 } getRegisterInfo()285 const MipsRegisterInfo *getRegisterInfo() const override { 286 return &InstrInfo->getRegisterInfo(); 287 } getTargetLowering()288 const MipsTargetLowering *getTargetLowering() const override { 289 return TLInfo.get(); 290 } getInstrItineraryData()291 const InstrItineraryData *getInstrItineraryData() const override { 292 return &InstrItins; 293 } 294 }; 295 } // End llvm namespace 296 297 #endif 298