1 /******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35
36 #ifndef _IXGBE_H_
37 #define _IXGBE_H_
38
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #ifndef IXGBE_LEGACY_TX
43 #include <sys/buf_ring.h>
44 #endif
45 #include <sys/mbuf.h>
46 #include <sys/protosw.h>
47 #include <sys/socket.h>
48 #include <sys/malloc.h>
49 #include <sys/kernel.h>
50 #include <sys/module.h>
51 #include <sys/sockio.h>
52 #include <sys/eventhandler.h>
53
54 #include <net/if.h>
55 #include <net/if_var.h>
56 #include <net/if_arp.h>
57 #include <net/bpf.h>
58 #include <net/ethernet.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61
62 #include <net/if_types.h>
63 #include <net/if_vlan_var.h>
64 #include <net/iflib.h>
65
66 #include <netinet/in_systm.h>
67 #include <netinet/in.h>
68 #include <netinet/if_ether.h>
69 #include <netinet/ip.h>
70 #include <netinet/ip6.h>
71 #include <netinet/tcp.h>
72 #include <netinet/tcp_lro.h>
73 #include <netinet/udp.h>
74
75 #include <machine/in_cksum.h>
76
77 #include <sys/bus.h>
78 #include <machine/bus.h>
79 #include <sys/rman.h>
80 #include <machine/resource.h>
81 #include <vm/vm.h>
82 #include <vm/pmap.h>
83 #include <machine/clock.h>
84 #include <dev/pci/pcivar.h>
85 #include <dev/pci/pcireg.h>
86 #include <sys/proc.h>
87 #include <sys/sysctl.h>
88 #include <sys/endian.h>
89 #include <sys/taskqueue.h>
90 #include <sys/pcpu.h>
91 #include <sys/smp.h>
92 #include <machine/smp.h>
93 #include <sys/sbuf.h>
94
95 #ifdef PCI_IOV
96 #include <sys/nv.h>
97 #include <sys/iov_schema.h>
98 #include <dev/pci/pci_iov.h>
99 #endif
100
101 #include "ixgbe_api.h"
102 #include "ixgbe_common.h"
103 #include "ixgbe_phy.h"
104 #include "ixgbe_vf.h"
105
106 #ifdef PCI_IOV
107 #include "ixgbe_common.h"
108 #include "ixgbe_mbx.h"
109 #endif
110
111 /* Tunables */
112
113 /*
114 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
115 * number of transmit descriptors allocated by the driver. Increasing this
116 * value allows the driver to queue more transmits. Each descriptor is 16
117 * bytes. Performance tests have show the 2K value to be optimal for top
118 * performance.
119 */
120 #define DEFAULT_TXD 1024
121 #define PERFORM_TXD 2048
122 #define MAX_TXD 4096
123 #define MIN_TXD 64
124
125 /*
126 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
127 * number of receive descriptors allocated for each RX queue. Increasing this
128 * value allows the driver to buffer more incoming packets. Each descriptor
129 * is 16 bytes. A receive buffer is also allocated for each descriptor.
130 *
131 * Note: with 8 rings and a dual port card, it is possible to bump up
132 * against the system mbuf pool limit, you can tune nmbclusters
133 * to adjust for this.
134 */
135 #define DEFAULT_RXD 1024
136 #define PERFORM_RXD 2048
137 #define MAX_RXD 4096
138 #define MIN_RXD 64
139
140 /* Alignment for rings */
141 #define DBA_ALIGN 128
142
143 /*
144 * This is the max watchdog interval, ie. the time that can
145 * pass between any two TX clean operations, such only happening
146 * when the TX hardware is functioning.
147 */
148 #define IXGBE_WATCHDOG (10 * hz)
149
150 /*
151 * This parameters control when the driver calls the routine to reclaim
152 * transmit descriptors.
153 */
154 #define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
155 #define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
156
157 /* These defines are used in MTU calculations */
158 #define IXGBE_MAX_FRAME_SIZE 9728
159 #define IXGBE_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN)
160 #define IXGBE_MTU_HDR_VLAN (ETHER_HDR_LEN + ETHER_CRC_LEN + \
161 ETHER_VLAN_ENCAP_LEN)
162 #define IXGBE_MAX_MTU (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR)
163 #define IXGBE_MAX_MTU_VLAN (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR_VLAN)
164
165 /* Flow control constants */
166 #define IXGBE_FC_PAUSE 0xFFFF
167 #define IXGBE_FC_HI 0x20000
168 #define IXGBE_FC_LO 0x10000
169
170 /*
171 * Used for optimizing small rx mbufs. Effort is made to keep the copy
172 * small and aligned for the CPU L1 cache.
173 *
174 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting
175 * 32 byte alignment needed for the fast bcopy results in 8 bytes being
176 * wasted. Getting 64 byte alignment, which _should_ be ideal for
177 * modern Intel CPUs, results in 40 bytes wasted and a significant drop
178 * in observed efficiency of the optimization, 97.9% -> 81.8%.
179 */
180 #if __FreeBSD_version < 1002000
181 #define MPKTHSIZE (sizeof(struct m_hdr) + sizeof(struct pkthdr))
182 #endif
183 #define IXGBE_RX_COPY_HDR_PADDED ((((MPKTHSIZE - 1) / 32) + 1) * 32)
184 #define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED)
185 #define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - MPKTHSIZE)
186
187 /* Keep older OS drivers building... */
188 #if !defined(SYSCTL_ADD_UQUAD)
189 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
190 #endif
191
192 /* Defines for printing debug information */
193 #define DEBUG_INIT 0
194 #define DEBUG_IOCTL 0
195 #define DEBUG_HW 0
196
197 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
198 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
199 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
200 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
201 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
202 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
203 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
204 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
205 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
206
207 #define MAX_NUM_MULTICAST_ADDRESSES 128
208 #define IXGBE_82598_SCATTER 100
209 #define IXGBE_82599_SCATTER 32
210 #define MSIX_82598_BAR 3
211 #define MSIX_82599_BAR 4
212 #define IXGBE_TSO_SIZE 262140
213 #define IXGBE_RX_HDR 128
214 #define IXGBE_VFTA_SIZE 128
215 #define IXGBE_BR_SIZE 4096
216 #define IXGBE_QUEUE_MIN_FREE 32
217 #define IXGBE_MAX_TX_BUSY 10
218 #define IXGBE_QUEUE_HUNG 0x80000000
219
220 #define IXV_EITR_DEFAULT 128
221
222 /* Supported offload bits in mbuf flag */
223 #if __FreeBSD_version >= 1000000
224 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
225 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
226 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
227 #elif __FreeBSD_version >= 800000
228 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
229 #else
230 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP)
231 #endif
232
233 /* Backward compatibility items for very old versions */
234 #ifndef pci_find_cap
235 #define pci_find_cap pci_find_extcap
236 #endif
237
238 #ifndef DEVMETHOD_END
239 #define DEVMETHOD_END { NULL, NULL }
240 #endif
241
242 /*
243 * Interrupt Moderation parameters
244 */
245 #define IXGBE_LOW_LATENCY 128
246 #define IXGBE_AVE_LATENCY 400
247 #define IXGBE_BULK_LATENCY 1200
248
249 /* Using 1FF (the max value), the interval is ~1.05ms */
250 #define IXGBE_LINK_ITR_QUANTA 0x1FF
251 #define IXGBE_LINK_ITR ((IXGBE_LINK_ITR_QUANTA << 3) & \
252 IXGBE_EITR_ITR_INT_MASK)
253
254 /* MAC type macros */
255 #define IXGBE_IS_X550VF(_adapter) \
256 ((_adapter->hw.mac.type == ixgbe_mac_X550_vf) || \
257 (_adapter->hw.mac.type == ixgbe_mac_X550EM_x_vf))
258
259 #define IXGBE_IS_VF(_adapter) \
260 (IXGBE_IS_X550VF(_adapter) || \
261 (_adapter->hw.mac.type == ixgbe_mac_X540_vf) || \
262 (_adapter->hw.mac.type == ixgbe_mac_82599_vf))
263
264 #ifdef PCI_IOV
265 #define IXGBE_VF_INDEX(vmdq) ((vmdq) / 32)
266 #define IXGBE_VF_BIT(vmdq) (1 << ((vmdq) % 32))
267
268 #define IXGBE_VT_MSG_MASK 0xFFFF
269
270 #define IXGBE_VT_MSGINFO(msg) \
271 (((msg) & IXGBE_VT_MSGINFO_MASK) >> IXGBE_VT_MSGINFO_SHIFT)
272
273 #define IXGBE_VF_GET_QUEUES_RESP_LEN 5
274
275 #define IXGBE_API_VER_1_0 0
276 #define IXGBE_API_VER_2_0 1 /* Solaris API. Not supported. */
277 #define IXGBE_API_VER_1_1 2
278 #define IXGBE_API_VER_UNKNOWN UINT16_MAX
279
280 enum ixgbe_iov_mode {
281 IXGBE_64_VM,
282 IXGBE_32_VM,
283 IXGBE_NO_VM
284 };
285 #endif /* PCI_IOV */
286
287
288 /*
289 *****************************************************************************
290 * vendor_info_array
291 *
292 * This array contains the list of Subvendor/Subdevice IDs on which the driver
293 * should load.
294 *
295 *****************************************************************************
296 */
297 typedef struct _ixgbe_vendor_info_t {
298 unsigned int vendor_id;
299 unsigned int device_id;
300 unsigned int subvendor_id;
301 unsigned int subdevice_id;
302 unsigned int index;
303 } ixgbe_vendor_info_t;
304
305
306 struct ixgbe_tx_buf {
307 union ixgbe_adv_tx_desc *eop;
308 struct mbuf *m_head;
309 bus_dmamap_t map;
310 };
311
312 struct ixgbe_rx_buf {
313 struct mbuf *buf;
314 struct mbuf *fmp;
315 bus_dmamap_t pmap;
316 u_int flags;
317 #define IXGBE_RX_COPY 0x01
318 uint64_t addr;
319 };
320
321 /*
322 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free.
323 */
324 struct ixgbe_dma_alloc {
325 bus_addr_t dma_paddr;
326 caddr_t dma_vaddr;
327 bus_dma_tag_t dma_tag;
328 bus_dmamap_t dma_map;
329 bus_dma_segment_t dma_seg;
330 bus_size_t dma_size;
331 int dma_nseg;
332 };
333
334 struct ixgbe_mc_addr {
335 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
336 u32 vmdq;
337 };
338
339 /*
340 * The transmit ring, one per queue
341 */
342 struct tx_ring {
343 struct ix_queue *que;
344 struct adapter *adapter;
345 struct mtx tx_mtx;
346 u32 me;
347 u32 tail;
348 int busy;
349 union ixgbe_adv_tx_desc *tx_base;
350 struct ixgbe_tx_buf *tx_buffers;
351 uint64_t tx_paddr;
352 volatile u16 tx_avail;
353 u16 next_avail_desc;
354 u16 next_to_clean;
355 u16 num_desc;
356 u32 txd_cmd;
357 bus_dma_tag_t txtag;
358 char mtx_name[16];
359 #ifndef IXGBE_LEGACY_TX
360 struct buf_ring *br;
361 struct task txq_task;
362 #endif
363 #ifdef IXGBE_FDIR
364 u16 atr_sample;
365 u16 atr_count;
366 #endif
367 u32 bytes; /* used for AIM */
368 u32 packets;
369 /* Soft Stats */
370 unsigned long tso_tx;
371 unsigned long no_tx_map_avail;
372 unsigned long no_tx_dma_setup;
373 u64 no_desc_avail;
374 u64 total_packets;
375 };
376
377
378 /*
379 * The Receive ring, one per rx queue
380 */
381 struct rx_ring {
382 struct ix_queue *que;
383 struct adapter *adapter;
384 struct mtx rx_mtx;
385 struct lro_ctrl lro;
386 u32 me;
387 u32 tail;
388 union ixgbe_adv_rx_desc *rx_base;
389 uint64_t rx_paddr;
390 bool hw_rsc;
391 bool vtag_strip;
392 u16 mbuf_sz;
393 char mtx_name[16];
394 bus_dma_tag_t ptag;
395
396 u32 bytes; /* Used for AIM calc */
397 u32 packets;
398
399 /* Soft stats */
400 u64 rx_irq;
401 u64 rx_copies;
402 u64 rx_packets;
403 u64 rx_bytes;
404 u64 rx_discarded;
405 u64 rsc_num;
406 #ifdef IXGBE_FDIR
407 u64 flm;
408 #endif
409 };
410
411 /*
412 ** Driver queue struct: this is the interrupt container
413 ** for the associated tx and rx ring.
414 */
415 struct ix_queue {
416 struct adapter *adapter;
417 u32 msix; /* This queue's MSIX vector */
418 u32 eims; /* This queue's EIMS bit */
419 u32 eitr_setting;
420 u32 me;
421 struct resource *res;
422 void *tag;
423 int busy;
424 struct tx_ring txr;
425 struct rx_ring rxr;
426
427 struct if_irq que_irq;
428
429 u64 irqs;
430 };
431
432 #ifdef PCI_IOV
433 #define IXGBE_VF_CTS (1 << 0) /* VF is clear to send. */
434 #define IXGBE_VF_CAP_MAC (1 << 1) /* VF is permitted to change MAC. */
435 #define IXGBE_VF_CAP_VLAN (1 << 2) /* VF is permitted to join vlans. */
436 #define IXGBE_VF_ACTIVE (1 << 3) /* VF is active. */
437
438 #define IXGBE_MAX_VF_MC 30 /* Max number of multicast entries */
439
440 struct ixgbe_vf {
441 u_int pool;
442 u_int rar_index;
443 u_int max_frame_size;
444 uint32_t flags;
445 uint8_t ether_addr[ETHER_ADDR_LEN];
446 uint16_t mc_hash[IXGBE_MAX_VF_MC];
447 uint16_t num_mc_hashes;
448 uint16_t default_vlan;
449 uint16_t vlan_tag;
450 uint16_t api_ver;
451 };
452 #endif /* PCI_IOV */
453
454 /* Our adapter structure */
455 struct adapter {
456 if_ctx_t ctx;
457 if_softc_ctx_t shared;
458 #define num_queues shared->isc_nqsets
459 #define max_frame_size shared->isc_max_frame_size
460 #define intr_type shared->isc_intr
461 struct ifnet *ifp;
462 struct ixgbe_hw hw;
463 struct ixgbe_osdep osdep;
464
465 struct device *dev;
466
467 struct resource *pci_mem;
468
469 /*
470 * Interrupt resources: this set is
471 * either used for legacy, or for Link
472 * when doing MSIX
473 */
474 struct if_irq irq;
475 void *tag;
476 struct resource *res;
477
478 struct ifmedia *media;
479 int msix;
480 int if_flags;
481
482 u16 num_vlans;
483
484 /*
485 ** Shadow VFTA table, this is needed because
486 ** the real vlan filter table gets cleared during
487 ** a soft reset and the driver needs to be able
488 ** to repopulate it.
489 */
490 u32 shadow_vfta[IXGBE_VFTA_SIZE];
491
492 /* Info about the interface */
493 u32 optics;
494 u32 fc; /* local flow ctrl setting */
495 int advertise; /* link speeds */
496 bool link_active;
497 u16 num_segs;
498 u32 link_speed;
499 bool link_up;
500 u32 vector;
501 u16 dmac;
502 bool eee_enabled;
503 u32 phy_layer;
504
505 /* Power management-related */
506 bool wol_support;
507 u32 wufc;
508
509 /* Support for pluggable optics */
510 bool sfp_probe;
511
512 struct grouptask mod_task; /* SFP tasklet */
513 struct grouptask msf_task; /* Multispeed Fiber */
514
515 #ifdef PCI_IOV
516 struct grouptask mbx_task; /* VF -> PF mailbox interrupt */
517 #endif /* PCI_IOV */
518 #ifdef IXGBE_FDIR
519 int fdir_reinit;
520 struct grouptask fdir_task;
521 #endif
522
523 struct grouptask phy_task; /* PHY intr tasklet */
524
525 /*
526 ** Queues:
527 ** This is the irq holder, it has
528 ** and RX/TX pair or rings associated
529 ** with it.
530 */
531 struct ix_queue *queues;
532 u64 active_queues;
533
534 /*
535 * Transmit rings:
536 * Allocated at run time, an array of rings.
537 */
538 struct tx_ring *tx_rings;
539 u32 tx_process_limit;
540
541 /*
542 * Receive rings:
543 * Allocated at run time, an array of rings.
544 */
545 struct rx_ring *rx_rings;
546 u32 rx_process_limit;
547
548 /* Multicast array memory */
549 struct ixgbe_mc_addr *mta;
550 int num_vfs;
551 int pool;
552 #ifdef PCI_IOV
553 struct ixgbe_vf *vfs;
554 #endif
555 #ifdef DEV_NETMAP
556 void (*init_locked)(struct adapter *);
557 void (*stop_locked)(void *);
558 #endif
559
560 /* Misc stats maintained by the driver */
561 unsigned long rx_mbuf_sz;
562 unsigned long dropped_pkts;
563 unsigned long mbuf_defrag_failed;
564 unsigned long mbuf_header_failed;
565 unsigned long mbuf_packet_failed;
566 unsigned long watchdog_events;
567 unsigned long link_irq;
568 union {
569 struct ixgbe_hw_stats pf;
570 struct ixgbevf_hw_stats vf;
571 } stats;
572 #if __FreeBSD_version >= 1100036
573 /* counter(9) stats */
574 u64 ipackets;
575 u64 ierrors;
576 u64 opackets;
577 u64 oerrors;
578 u64 ibytes;
579 u64 obytes;
580 u64 imcasts;
581 u64 omcasts;
582 u64 iqdrops;
583 u64 noproto;
584 #endif
585 };
586
587
588 /* Precision Time Sync (IEEE 1588) defines */
589 #define ETHERTYPE_IEEE1588 0x88F7
590 #define PICOSECS_PER_TICK 20833
591 #define TSYNC_UDP_PORT 319 /* UDP port for the protocol */
592 #define IXGBE_ADVTXD_TSTAMP 0x00080000
593
594
595 #define IXGBE_CORE_LOCK_INIT(_sc, _name) \
596 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF)
597 #define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
598 #define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
599 #define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
600 #define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
601 #define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
602 #define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx)
603 #define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
604 #define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
605 #define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
606 #define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
607 #define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
608 #define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
609
610 /* For backward compatibility */
611 #if !defined(PCIER_LINK_STA)
612 #define PCIER_LINK_STA PCIR_EXPRESS_LINK_STA
613 #endif
614
615 /* Stats macros */
616 #if __FreeBSD_version >= 1100036
617 #define IXGBE_SET_IPACKETS(sc, count) (sc)->ipackets = (count)
618 #define IXGBE_SET_IERRORS(sc, count) (sc)->ierrors = (count)
619 #define IXGBE_SET_OPACKETS(sc, count) (sc)->opackets = (count)
620 #define IXGBE_SET_OERRORS(sc, count) (sc)->oerrors = (count)
621 #define IXGBE_SET_COLLISIONS(sc, count)
622 #define IXGBE_SET_IBYTES(sc, count) (sc)->ibytes = (count)
623 #define IXGBE_SET_OBYTES(sc, count) (sc)->obytes = (count)
624 #define IXGBE_SET_IMCASTS(sc, count) (sc)->imcasts = (count)
625 #define IXGBE_SET_OMCASTS(sc, count) (sc)->omcasts = (count)
626 #define IXGBE_SET_IQDROPS(sc, count) (sc)->iqdrops = (count)
627 #else
628 #define IXGBE_SET_IPACKETS(sc, count) (sc)->ifp->if_ipackets = (count)
629 #define IXGBE_SET_IERRORS(sc, count) (sc)->ifp->if_ierrors = (count)
630 #define IXGBE_SET_OPACKETS(sc, count) (sc)->ifp->if_opackets = (count)
631 #define IXGBE_SET_OERRORS(sc, count) (sc)->ifp->if_oerrors = (count)
632 #define IXGBE_SET_COLLISIONS(sc, count) (sc)->ifp->if_collisions = (count)
633 #define IXGBE_SET_IBYTES(sc, count) (sc)->ifp->if_ibytes = (count)
634 #define IXGBE_SET_OBYTES(sc, count) (sc)->ifp->if_obytes = (count)
635 #define IXGBE_SET_IMCASTS(sc, count) (sc)->ifp->if_imcasts = (count)
636 #define IXGBE_SET_OMCASTS(sc, count) (sc)->ifp->if_omcasts = (count)
637 #define IXGBE_SET_IQDROPS(sc, count) (sc)->ifp->if_iqdrops = (count)
638 #endif
639
640 /* External PHY register addresses */
641 #define IXGBE_PHY_CURRENT_TEMP 0xC820
642 #define IXGBE_PHY_OVERTEMP_STATUS 0xC830
643
644 /* Sysctl help messages; displayed with sysctl -d */
645 #define IXGBE_SYSCTL_DESC_ADV_SPEED \
646 "\nControl advertised link speed using these flags:\n" \
647 "\t0x1 - advertise 100M\n" \
648 "\t0x2 - advertise 1G\n" \
649 "\t0x4 - advertise 10G\n\n" \
650 "\t100M is only supported on certain 10GBaseT adapters.\n"
651
652 #define IXGBE_SYSCTL_DESC_SET_FC \
653 "\nSet flow control mode using these values:\n" \
654 "\t0 - off\n" \
655 "\t1 - rx pause\n" \
656 "\t2 - tx pause\n" \
657 "\t3 - tx and rx pause"
658
659 static inline bool
ixgbe_is_sfp(struct ixgbe_hw * hw)660 ixgbe_is_sfp(struct ixgbe_hw *hw)
661 {
662 switch (hw->phy.type) {
663 case ixgbe_phy_sfp_avago:
664 case ixgbe_phy_sfp_ftl:
665 case ixgbe_phy_sfp_intel:
666 case ixgbe_phy_sfp_unknown:
667 case ixgbe_phy_sfp_passive_tyco:
668 case ixgbe_phy_sfp_passive_unknown:
669 case ixgbe_phy_qsfp_passive_unknown:
670 case ixgbe_phy_qsfp_active_unknown:
671 case ixgbe_phy_qsfp_intel:
672 case ixgbe_phy_qsfp_unknown:
673 return TRUE;
674 default:
675 return FALSE;
676 }
677 }
678
679 /* Workaround to make 8.0 buildable */
680 #if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504
681 static __inline int
drbr_needs_enqueue(struct ifnet * ifp,struct buf_ring * br)682 drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br)
683 {
684 #ifdef ALTQ
685 if (ALTQ_IS_ENABLED(&ifp->if_snd))
686 return (1);
687 #endif
688 return (!buf_ring_empty(br));
689 }
690 #endif
691
692 /*
693 ** This checks for a zero mac addr, something that will be likely
694 ** unless the Admin on the Host has created one.
695 */
696 static inline bool
ixv_check_ether_addr(u8 * addr)697 ixv_check_ether_addr(u8 *addr)
698 {
699 bool status = TRUE;
700
701 if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 &&
702 addr[3] == 0 && addr[4]== 0 && addr[5] == 0))
703 status = FALSE;
704 return (status);
705 }
706
707 /* Shared Prototypes */
708
709 #ifdef IXGBE_LEGACY_TX
710 void ixgbe_start(struct ifnet *);
711 void ixgbe_start_locked(struct tx_ring *, struct ifnet *);
712 #else /* ! IXGBE_LEGACY_TX */
713 int ixgbe_mq_start(struct ifnet *, struct mbuf *);
714 int ixgbe_mq_start_locked(struct ifnet *, struct tx_ring *);
715 void ixgbe_qflush(struct ifnet *);
716 void ixgbe_deferred_mq_start(void *, int);
717 #endif /* IXGBE_LEGACY_TX */
718
719 int ixgbe_allocate_queues(struct adapter *);
720 int ixgbe_allocate_transmit_buffers(struct tx_ring *);
721 int ixgbe_setup_transmit_structures(struct adapter *);
722 void ixgbe_free_transmit_structures(struct adapter *);
723 int ixgbe_allocate_receive_buffers(struct rx_ring *);
724 int ixgbe_setup_receive_structures(struct adapter *);
725 void ixgbe_free_receive_structures(struct adapter *);
726 void ixgbe_txeof(struct tx_ring *);
727 bool ixgbe_rxeof(struct ix_queue *);
728
729 int ixgbe_dma_malloc(struct adapter *,
730 bus_size_t, struct ixgbe_dma_alloc *, int);
731 void ixgbe_dma_free(struct adapter *, struct ixgbe_dma_alloc *);
732
733 #ifdef PCI_IOV
734
735 static inline boolean_t
ixgbe_vf_mac_changed(struct ixgbe_vf * vf,const uint8_t * mac)736 ixgbe_vf_mac_changed(struct ixgbe_vf *vf, const uint8_t *mac)
737 {
738 return (bcmp(mac, vf->ether_addr, ETHER_ADDR_LEN) != 0);
739 }
740
741 static inline void
ixgbe_send_vf_msg(struct adapter * adapter,struct ixgbe_vf * vf,u32 msg)742 ixgbe_send_vf_msg(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg)
743 {
744
745 if (vf->flags & IXGBE_VF_CTS)
746 msg |= IXGBE_VT_MSGTYPE_CTS;
747
748 ixgbe_write_mbx(&adapter->hw, &msg, 1, vf->pool);
749 }
750
751 static inline void
ixgbe_send_vf_ack(struct adapter * adapter,struct ixgbe_vf * vf,u32 msg)752 ixgbe_send_vf_ack(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg)
753 {
754 msg &= IXGBE_VT_MSG_MASK;
755 ixgbe_send_vf_msg(adapter, vf, msg | IXGBE_VT_MSGTYPE_ACK);
756 }
757
758 static inline void
ixgbe_send_vf_nack(struct adapter * adapter,struct ixgbe_vf * vf,u32 msg)759 ixgbe_send_vf_nack(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg)
760 {
761 msg &= IXGBE_VT_MSG_MASK;
762 ixgbe_send_vf_msg(adapter, vf, msg | IXGBE_VT_MSGTYPE_NACK);
763 }
764
765 static inline void
ixgbe_process_vf_ack(struct adapter * adapter,struct ixgbe_vf * vf)766 ixgbe_process_vf_ack(struct adapter *adapter, struct ixgbe_vf *vf)
767 {
768 if (!(vf->flags & IXGBE_VF_CTS))
769 ixgbe_send_vf_nack(adapter, vf, 0);
770 }
771
772 static inline enum ixgbe_iov_mode
ixgbe_get_iov_mode(struct adapter * adapter)773 ixgbe_get_iov_mode(struct adapter *adapter)
774 {
775 if (adapter->num_vfs == 0)
776 return (IXGBE_NO_VM);
777 if (adapter->num_queues <= 2)
778 return (IXGBE_64_VM);
779 else if (adapter->num_queues <= 4)
780 return (IXGBE_32_VM);
781 else
782 return (IXGBE_NO_VM);
783 }
784
785 static inline u16
ixgbe_max_vfs(enum ixgbe_iov_mode mode)786 ixgbe_max_vfs(enum ixgbe_iov_mode mode)
787 {
788 /*
789 * We return odd numbers below because we
790 * reserve 1 VM's worth of queues for the PF.
791 */
792 switch (mode) {
793 case IXGBE_64_VM:
794 return (63);
795 case IXGBE_32_VM:
796 return (31);
797 case IXGBE_NO_VM:
798 default:
799 return (0);
800 }
801 }
802
803 static inline int
ixgbe_vf_queues(enum ixgbe_iov_mode mode)804 ixgbe_vf_queues(enum ixgbe_iov_mode mode)
805 {
806 switch (mode) {
807 case IXGBE_64_VM:
808 return (2);
809 case IXGBE_32_VM:
810 return (4);
811 case IXGBE_NO_VM:
812 default:
813 return (0);
814 }
815 }
816
817 static inline int
ixgbe_vf_que_index(enum ixgbe_iov_mode mode,u32 vfnum,int num)818 ixgbe_vf_que_index(enum ixgbe_iov_mode mode, u32 vfnum, int num)
819 {
820 return ((vfnum * ixgbe_vf_queues(mode)) + num);
821 }
822
823 static inline int
ixgbe_pf_que_index(enum ixgbe_iov_mode mode,int num)824 ixgbe_pf_que_index(enum ixgbe_iov_mode mode, int num)
825 {
826 return (ixgbe_vf_que_index(mode, ixgbe_max_vfs(mode), num));
827 }
828
829 static inline void
ixgbe_update_max_frame(struct adapter * adapter,int max_frame)830 ixgbe_update_max_frame(struct adapter * adapter, int max_frame)
831 {
832 if (adapter->max_frame_size < max_frame)
833 adapter->max_frame_size = max_frame;
834 }
835
836 static inline u32
ixgbe_get_mrqc(enum ixgbe_iov_mode mode)837 ixgbe_get_mrqc(enum ixgbe_iov_mode mode)
838 {
839 u32 mrqc = 0;
840 switch (mode) {
841 case IXGBE_64_VM:
842 mrqc = IXGBE_MRQC_VMDQRSS64EN;
843 break;
844 case IXGBE_32_VM:
845 mrqc = IXGBE_MRQC_VMDQRSS32EN;
846 break;
847 case IXGBE_NO_VM:
848 mrqc = 0;
849 break;
850 default:
851 panic("Unexpected SR-IOV mode %d", mode);
852 }
853 return(mrqc);
854 }
855
856
857 static inline u32
ixgbe_get_mtqc(enum ixgbe_iov_mode mode)858 ixgbe_get_mtqc(enum ixgbe_iov_mode mode)
859 {
860 uint32_t mtqc = 0;
861 switch (mode) {
862 case IXGBE_64_VM:
863 mtqc |= IXGBE_MTQC_64VF | IXGBE_MTQC_VT_ENA;
864 break;
865 case IXGBE_32_VM:
866 mtqc |= IXGBE_MTQC_32VF | IXGBE_MTQC_VT_ENA;
867 break;
868 case IXGBE_NO_VM:
869 mtqc = IXGBE_MTQC_64Q_1PB;
870 break;
871 default:
872 panic("Unexpected SR-IOV mode %d", mode);
873 }
874 return(mtqc);
875 }
876 #endif /* PCI_IOV */
877
878 #endif /* _IXGBE_H_ */
879