1 /* $NetBSD: isp_pci.c,v 1.122 2019/11/10 21:16:36 chs Exp $ */
2 /*
3 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration
4 * All rights reserved.
5 *
6 * Additional Copyright (C) 2000-2007 by Matthew Jacob
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 /*
32 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
33 */
34
35 /*
36 * 24XX 4Gb material support provided by MetrumRG Associates.
37 * Many thanks are due to them.
38 */
39
40 #include <sys/cdefs.h>
41 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.122 2019/11/10 21:16:36 chs Exp $");
42
43 #include <dev/ic/isp_netbsd.h>
44 #include <dev/pci/pcireg.h>
45 #include <dev/pci/pcivar.h>
46 #include <dev/pci/pcidevs.h>
47 #include <sys/reboot.h>
48
49 static uint32_t isp_pci_rd_reg(struct ispsoftc *, int);
50 static void isp_pci_wr_reg(struct ispsoftc *, int, uint32_t);
51 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT))
52 static uint32_t isp_pci_rd_reg_1080(struct ispsoftc *, int);
53 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, uint32_t);
54 #endif
55 #if !defined(ISP_DISABLE_2100_SUPPORT) && \
56 !defined(ISP_DISABLE_2200_SUPPORT) && \
57 !defined(ISP_DISABLE_1020_SUPPORT) && \
58 !defined(ISP_DISABLE_1080_SUPPORT) && \
59 !defined(ISP_DISABLE_12160_SUPPORT)
60 static int
61 isp_pci_rd_isr(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *);
62 #endif
63 #if !(defined(ISP_DISABLE_2300_SUPPORT) && defined(ISP_DISABLE_2322_SUPPORT))
64 static int
65 isp_pci_rd_isr_2300(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *);
66 #endif
67 #if !defined(ISP_DISABLE_2400_SUPPORT)
68 static uint32_t isp_pci_rd_reg_2400(struct ispsoftc *, int);
69 static void isp_pci_wr_reg_2400(struct ispsoftc *, int, uint32_t);
70 static int
71 isp_pci_rd_isr_2400(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *);
72 #endif
73 static int isp_pci_mbxdma(struct ispsoftc *);
74 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, void *);
75 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, uint32_t);
76 static void isp_pci_reset0(struct ispsoftc *);
77 static void isp_pci_reset1(struct ispsoftc *);
78 static void isp_pci_dumpregs(struct ispsoftc *, const char *);
79 static int isp_pci_intr(void *);
80
81 #if defined(ISP_DISABLE_1020_SUPPORT) || defined(ISP_DISABLE_FW)
82 #define ISP_1040_RISC_CODE NULL
83 #else
84 #define ISP_1040_RISC_CODE (const uint16_t *) isp_1040_risc_code
85 #include <dev/microcode/isp/asm_1040.h>
86 #endif
87
88 #if defined(ISP_DISABLE_1080_SUPPORT) || defined(ISP_DISABLE_FW)
89 #define ISP_1080_RISC_CODE NULL
90 #else
91 #define ISP_1080_RISC_CODE (const uint16_t *) isp_1080_risc_code
92 #include <dev/microcode/isp/asm_1080.h>
93 #endif
94
95 #if defined(ISP_DISABLE_12160_SUPPORT) || defined(ISP_DISABLE_FW)
96 #define ISP_12160_RISC_CODE NULL
97 #else
98 #define ISP_12160_RISC_CODE (const uint16_t *) isp_12160_risc_code
99 #include <dev/microcode/isp/asm_12160.h>
100 #endif
101
102 #if defined(ISP_DISABLE_2100_SUPPORT) || defined(ISP_DISABLE_FW)
103 #define ISP_2100_RISC_CODE NULL
104 #else
105 #define ISP_2100_RISC_CODE (const uint16_t *) isp_2100_risc_code
106 #include <dev/microcode/isp/asm_2100.h>
107 #endif
108
109 #if defined(ISP_DISABLE_2200_SUPPORT) || defined(ISP_DISABLE_FW)
110 #define ISP_2200_RISC_CODE NULL
111 #else
112 #define ISP_2200_RISC_CODE (const uint16_t *) isp_2200_risc_code
113 #include <dev/microcode/isp/asm_2200.h>
114 #endif
115
116 #if defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_FW)
117 #define ISP_2300_RISC_CODE NULL
118 #else
119 #define ISP_2300_RISC_CODE (const uint16_t *) isp_2300_risc_code
120 #include <dev/microcode/isp/asm_2300.h>
121 #endif
122 #if defined(ISP_DISABLE_2322_SUPPORT) || defined(ISP_DISABLE_FW)
123 #define ISP_2322_RISC_CODE NULL
124 #else
125 #define ISP_2322_RISC_CODE (const uint16_t *) isp_2322_risc_code
126 #include <dev/microcode/isp/asm_2322.h>
127 #endif
128
129 #if defined(ISP_DISABLE_2400_SUPPORT) || defined(ISP_DISABLE_FW)
130 #define ISP_2400_RISC_CODE NULL
131 #define ISP_2500_RISC_CODE NULL
132 #else
133 #define ISP_2500
134 #define ISP_2400
135 #define ISP_2400_RISC_CODE (const uint32_t *) isp_2400_risc_code
136 #define ISP_2500_RISC_CODE (const uint32_t *) isp_2500_risc_code
137 #include <dev/microcode/isp/asm_2400.h>
138 #include <dev/microcode/isp/asm_2500.h>
139 #endif
140
141 #ifndef ISP_DISABLE_1020_SUPPORT
142 static struct ispmdvec mdvec = {
143 isp_pci_rd_isr,
144 isp_pci_rd_reg,
145 isp_pci_wr_reg,
146 isp_pci_mbxdma,
147 isp_pci_dmasetup,
148 isp_pci_dmateardown,
149 isp_pci_reset0,
150 isp_pci_reset1,
151 isp_pci_dumpregs,
152 ISP_1040_RISC_CODE,
153 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64,
154 0
155 };
156 #endif
157
158 #ifndef ISP_DISABLE_1080_SUPPORT
159 static struct ispmdvec mdvec_1080 = {
160 isp_pci_rd_isr,
161 isp_pci_rd_reg_1080,
162 isp_pci_wr_reg_1080,
163 isp_pci_mbxdma,
164 isp_pci_dmasetup,
165 isp_pci_dmateardown,
166 isp_pci_reset0,
167 isp_pci_reset1,
168 isp_pci_dumpregs,
169 ISP_1080_RISC_CODE,
170 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64,
171 0
172 };
173 #endif
174
175 #ifndef ISP_DISABLE_12160_SUPPORT
176 static struct ispmdvec mdvec_12160 = {
177 isp_pci_rd_isr,
178 isp_pci_rd_reg_1080,
179 isp_pci_wr_reg_1080,
180 isp_pci_mbxdma,
181 isp_pci_dmasetup,
182 isp_pci_dmateardown,
183 isp_pci_reset0,
184 isp_pci_reset1,
185 isp_pci_dumpregs,
186 ISP_12160_RISC_CODE,
187 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64,
188 0
189 };
190 #endif
191
192 #ifndef ISP_DISABLE_2100_SUPPORT
193 static struct ispmdvec mdvec_2100 = {
194 isp_pci_rd_isr,
195 isp_pci_rd_reg,
196 isp_pci_wr_reg,
197 isp_pci_mbxdma,
198 isp_pci_dmasetup,
199 isp_pci_dmateardown,
200 isp_pci_reset0,
201 isp_pci_reset1,
202 isp_pci_dumpregs,
203 ISP_2100_RISC_CODE,
204 0,
205 0
206 };
207 #endif
208
209 #ifndef ISP_DISABLE_2200_SUPPORT
210 static struct ispmdvec mdvec_2200 = {
211 isp_pci_rd_isr,
212 isp_pci_rd_reg,
213 isp_pci_wr_reg,
214 isp_pci_mbxdma,
215 isp_pci_dmasetup,
216 isp_pci_dmateardown,
217 isp_pci_reset0,
218 isp_pci_reset1,
219 isp_pci_dumpregs,
220 ISP_2200_RISC_CODE,
221 0,
222 0
223 };
224 #endif
225
226 #ifndef ISP_DISABLE_2300_SUPPORT
227 static struct ispmdvec mdvec_2300 = {
228 isp_pci_rd_isr_2300,
229 isp_pci_rd_reg,
230 isp_pci_wr_reg,
231 isp_pci_mbxdma,
232 isp_pci_dmasetup,
233 isp_pci_dmateardown,
234 isp_pci_reset0,
235 isp_pci_reset1,
236 isp_pci_dumpregs,
237 ISP_2300_RISC_CODE,
238 0,
239 0
240 };
241 #endif
242
243 #ifndef ISP_DISABLE_2322_SUPPORT
244 static struct ispmdvec mdvec_2322 = {
245 isp_pci_rd_isr_2300,
246 isp_pci_rd_reg,
247 isp_pci_wr_reg,
248 isp_pci_mbxdma,
249 isp_pci_dmasetup,
250 isp_pci_dmateardown,
251 isp_pci_reset0,
252 isp_pci_reset1,
253 isp_pci_dumpregs,
254 ISP_2322_RISC_CODE,
255 0,
256 0
257 };
258 #endif
259
260 #ifndef ISP_DISABLE_2400_SUPPORT
261 static struct ispmdvec mdvec_2400 = {
262 isp_pci_rd_isr_2400,
263 isp_pci_rd_reg_2400,
264 isp_pci_wr_reg_2400,
265 isp_pci_mbxdma,
266 isp_pci_dmasetup,
267 isp_pci_dmateardown,
268 isp_pci_reset0,
269 isp_pci_reset1,
270 NULL,
271 ISP_2400_RISC_CODE,
272 0,
273 0
274 };
275 static struct ispmdvec mdvec_2500 = {
276 isp_pci_rd_isr_2400,
277 isp_pci_rd_reg_2400,
278 isp_pci_wr_reg_2400,
279 isp_pci_mbxdma,
280 isp_pci_dmasetup,
281 isp_pci_dmateardown,
282 isp_pci_reset0,
283 isp_pci_reset1,
284 NULL,
285 ISP_2500_RISC_CODE,
286 0,
287 0
288 };
289 #endif
290
291 #ifndef PCI_VENDOR_QLOGIC
292 #define PCI_VENDOR_QLOGIC 0x1077
293 #endif
294
295 #ifndef PCI_PRODUCT_QLOGIC_ISP1020
296 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
297 #endif
298
299 #ifndef PCI_PRODUCT_QLOGIC_ISP1080
300 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080
301 #endif
302
303 #ifndef PCI_PRODUCT_QLOGIC_ISP1240
304 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240
305 #endif
306
307 #ifndef PCI_PRODUCT_QLOGIC_ISP1280
308 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280
309 #endif
310
311 #ifndef PCI_PRODUCT_QLOGIC_ISP10160
312 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016
313 #endif
314
315 #ifndef PCI_PRODUCT_QLOGIC_ISP12160
316 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216
317 #endif
318
319 #ifndef PCI_PRODUCT_QLOGIC_ISP2100
320 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
321 #endif
322
323 #ifndef PCI_PRODUCT_QLOGIC_ISP2200
324 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200
325 #endif
326
327 #ifndef PCI_PRODUCT_QLOGIC_ISP2300
328 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300
329 #endif
330
331 #ifndef PCI_PRODUCT_QLOGIC_ISP2312
332 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312
333 #endif
334
335 #ifndef PCI_PRODUCT_QLOGIC_ISP2322
336 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322
337 #endif
338
339 #ifndef PCI_PRODUCT_QLOGIC_ISP2422
340 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422
341 #endif
342
343 #ifndef PCI_PRODUCT_QLOGIC_ISP2432
344 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432
345 #endif
346
347 #ifndef PCI_PRODUCT_QLOGIC_ISP2532
348 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532
349 #endif
350
351 #ifndef PCI_PRODUCT_QLOGIC_ISP6312
352 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312
353 #endif
354
355 #ifndef PCI_PRODUCT_QLOGIC_ISP6322
356 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322
357 #endif
358
359
360 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
361
362 #define PCI_QLOGIC_ISP1080 \
363 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC)
364
365 #define PCI_QLOGIC_ISP10160 \
366 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC)
367
368 #define PCI_QLOGIC_ISP12160 \
369 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC)
370
371 #define PCI_QLOGIC_ISP1240 \
372 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC)
373
374 #define PCI_QLOGIC_ISP1280 \
375 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC)
376
377 #define PCI_QLOGIC_ISP2100 \
378 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
379
380 #define PCI_QLOGIC_ISP2200 \
381 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC)
382
383 #define PCI_QLOGIC_ISP2300 \
384 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC)
385
386 #define PCI_QLOGIC_ISP2312 \
387 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC)
388
389 #define PCI_QLOGIC_ISP2322 \
390 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC)
391
392 #define PCI_QLOGIC_ISP2422 \
393 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC)
394
395 #define PCI_QLOGIC_ISP2432 \
396 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC)
397
398 #define PCI_QLOGIC_ISP2532 \
399 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC)
400
401 #define PCI_QLOGIC_ISP6312 \
402 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC)
403
404 #define PCI_QLOGIC_ISP6322 \
405 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC)
406
407 #define IO_MAP_REG 0x10
408 #define MEM_MAP_REG 0x14
409 #define PCIR_ROMADDR 0x30
410
411 #define PCI_DFLT_LTNCY 0x40
412 #define PCI_DFLT_LNSZ 0x10
413
414 static int isp_pci_probe(device_t, cfdata_t, void *);
415 static void isp_pci_attach(device_t, device_t, void *);
416
417 struct isp_pcisoftc {
418 struct ispsoftc pci_isp;
419 pci_chipset_tag_t pci_pc;
420 pcitag_t pci_tag;
421 bus_space_tag_t pci_st;
422 bus_space_handle_t pci_sh;
423 bus_dmamap_t *pci_xfer_dmap;
424 void * pci_ih;
425 int16_t pci_poff[_NREG_BLKS];
426 };
427
428 CFATTACH_DECL_NEW(isp_pci, sizeof (struct isp_pcisoftc),
429 isp_pci_probe, isp_pci_attach, NULL, NULL);
430
431 static int
isp_pci_probe(device_t parent,cfdata_t match,void * aux)432 isp_pci_probe(device_t parent, cfdata_t match, void *aux)
433 {
434 struct pci_attach_args *pa = aux;
435 switch (pa->pa_id) {
436 #ifndef ISP_DISABLE_1020_SUPPORT
437 case PCI_QLOGIC_ISP:
438 return (1);
439 #endif
440 #ifndef ISP_DISABLE_1080_SUPPORT
441 case PCI_QLOGIC_ISP1080:
442 case PCI_QLOGIC_ISP1240:
443 case PCI_QLOGIC_ISP1280:
444 return (1);
445 #endif
446 #ifndef ISP_DISABLE_12160_SUPPORT
447 case PCI_QLOGIC_ISP10160:
448 case PCI_QLOGIC_ISP12160:
449 return (1);
450 #endif
451 #ifndef ISP_DISABLE_2100_SUPPORT
452 case PCI_QLOGIC_ISP2100:
453 return (1);
454 #endif
455 #ifndef ISP_DISABLE_2200_SUPPORT
456 case PCI_QLOGIC_ISP2200:
457 return (1);
458 #endif
459 #ifndef ISP_DISABLE_2300_SUPPORT
460 case PCI_QLOGIC_ISP2300:
461 case PCI_QLOGIC_ISP2312:
462 case PCI_QLOGIC_ISP6312:
463 #endif
464 #ifndef ISP_DISABLE_2322_SUPPORT
465 case PCI_QLOGIC_ISP2322:
466 case PCI_QLOGIC_ISP6322:
467 return (1);
468 #endif
469 #ifndef ISP_DISABLE_2400_SUPPORT
470 case PCI_QLOGIC_ISP2422:
471 case PCI_QLOGIC_ISP2432:
472 case PCI_QLOGIC_ISP2532:
473 return (1);
474 #endif
475 default:
476 return (0);
477 }
478 }
479
480 static void
isp_pci_attach(device_t parent,device_t self,void * aux)481 isp_pci_attach(device_t parent, device_t self, void *aux)
482 {
483 uint32_t data, rev, linesz = PCI_DFLT_LNSZ;
484 struct pci_attach_args *pa = aux;
485 struct isp_pcisoftc *pcs = device_private(self);
486 struct ispsoftc *isp = &pcs->pci_isp;
487 bus_space_tag_t st, iot, memt;
488 bus_space_handle_t sh, ioh, memh;
489 pci_intr_handle_t ih;
490 pcireg_t mem_type;
491 const char *dstring;
492 const char *intrstr;
493 int ioh_valid, memh_valid;
494 size_t mamt;
495 char intrbuf[PCI_INTRSTR_LEN];
496
497 isp->isp_osinfo.dev = self;
498
499 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0,
500 &iot, &ioh, NULL, NULL) == 0);
501
502 mem_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, MEM_MAP_REG);
503 if (PCI_MAPREG_TYPE(mem_type) != PCI_MAPREG_TYPE_MEM) {
504 memh_valid = 0;
505 } else if (PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_32BIT &&
506 PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_64BIT) {
507 memh_valid = 0;
508 } else {
509 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, mem_type, 0,
510 &memt, &memh, NULL, NULL) == 0);
511 }
512 if (memh_valid) {
513 st = memt;
514 sh = memh;
515 } else if (ioh_valid) {
516 st = iot;
517 sh = ioh;
518 } else {
519 aprint_error(": unable to map device registers\n");
520 return;
521 }
522 dstring = "\n";
523
524 isp->isp_nchan = 1;
525 mamt = 0;
526
527 pcs->pci_st = st;
528 pcs->pci_sh = sh;
529 pcs->pci_pc = pa->pa_pc;
530 pcs->pci_tag = pa->pa_tag;
531 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF;
532 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF;
533 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF;
534 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF;
535 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF;
536 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff;
537
538
539 #ifndef ISP_DISABLE_1020_SUPPORT
540 if (pa->pa_id == PCI_QLOGIC_ISP) {
541 dstring = ": QLogic 1020 Fast Wide SCSI HBA\n";
542 isp->isp_mdvec = &mdvec;
543 isp->isp_type = ISP_HA_SCSI_UNKNOWN;
544 mamt = sizeof (sdparam);
545 }
546 #endif
547 #ifndef ISP_DISABLE_1080_SUPPORT
548 if (pa->pa_id == PCI_QLOGIC_ISP1080) {
549 dstring = ": QLogic 1080 Ultra-2 Wide SCSI HBA\n";
550 isp->isp_mdvec = &mdvec_1080;
551 isp->isp_type = ISP_HA_SCSI_1080;
552 mamt = sizeof (sdparam);
553 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
554 ISP1080_DMA_REGS_OFF;
555 }
556 if (pa->pa_id == PCI_QLOGIC_ISP1240) {
557 dstring = ": QLogic Dual Channel Ultra Wide SCSI HBA\n";
558 isp->isp_mdvec = &mdvec_1080;
559 isp->isp_type = ISP_HA_SCSI_1240;
560 isp->isp_nchan++;
561 mamt = sizeof (sdparam) * 2;
562 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
563 ISP1080_DMA_REGS_OFF;
564 }
565 if (pa->pa_id == PCI_QLOGIC_ISP1280) {
566 dstring = ": QLogic Dual Channel Ultra-2 Wide SCSI HBA\n";
567 isp->isp_mdvec = &mdvec_1080;
568 isp->isp_type = ISP_HA_SCSI_1280;
569 isp->isp_nchan++;
570 mamt = sizeof (sdparam) * 2;
571 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
572 ISP1080_DMA_REGS_OFF;
573 }
574 #endif
575 #ifndef ISP_DISABLE_12160_SUPPORT
576 if (pa->pa_id == PCI_QLOGIC_ISP10160) {
577 dstring = ": QLogic Ultra-3 Wide SCSI HBA\n";
578 isp->isp_mdvec = &mdvec_12160;
579 isp->isp_type = ISP_HA_SCSI_10160;
580 mamt = sizeof (sdparam);
581 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
582 ISP1080_DMA_REGS_OFF;
583 }
584 if (pa->pa_id == PCI_QLOGIC_ISP12160) {
585 dstring = ": QLogic Dual Channel Ultra-3 Wide SCSI HBA\n";
586 isp->isp_mdvec = &mdvec_12160;
587 isp->isp_type = ISP_HA_SCSI_12160;
588 isp->isp_nchan++;
589 mamt = sizeof (sdparam) * 2;
590 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
591 ISP1080_DMA_REGS_OFF;
592 }
593 #endif
594 #ifndef ISP_DISABLE_2100_SUPPORT
595 if (pa->pa_id == PCI_QLOGIC_ISP2100) {
596 dstring = ": QLogic FC-AL HBA\n";
597 isp->isp_mdvec = &mdvec_2100;
598 isp->isp_type = ISP_HA_FC_2100;
599 mamt = sizeof (fcparam);
600 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
601 PCI_MBOX_REGS2100_OFF;
602 if (rev < 3) {
603 /*
604 * XXX: Need to get the actual revision
605 * XXX: number of the 2100 FB. At any rate,
606 * XXX: lower cache line size for early revision
607 * XXX; boards.
608 */
609 linesz = 1;
610 }
611 }
612 #endif
613 #ifndef ISP_DISABLE_2200_SUPPORT
614 if (pa->pa_id == PCI_QLOGIC_ISP2200) {
615 dstring = ": QLogic FC-AL and Fabric HBA\n";
616 isp->isp_mdvec = &mdvec_2200;
617 isp->isp_type = ISP_HA_FC_2200;
618 mamt = sizeof (fcparam);
619 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
620 PCI_MBOX_REGS2100_OFF;
621 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
622 }
623 #endif
624 #ifndef ISP_DISABLE_2300_SUPPORT
625 if (pa->pa_id == PCI_QLOGIC_ISP2300 ||
626 pa->pa_id == PCI_QLOGIC_ISP2312 ||
627 pa->pa_id == PCI_QLOGIC_ISP6312) {
628 isp->isp_mdvec = &mdvec_2300;
629 if (pa->pa_id == PCI_QLOGIC_ISP2300 ||
630 pa->pa_id == PCI_QLOGIC_ISP6312) {
631 dstring = ": QLogic FC-AL and 2Gbps Fabric HBA\n";
632 isp->isp_type = ISP_HA_FC_2300;
633 } else {
634 dstring =
635 ": QLogic Dual Port FC-AL and 2Gbps Fabric HBA\n";
636 isp->isp_port = pa->pa_function;
637 }
638 isp->isp_type = ISP_HA_FC_2312;
639 mamt = sizeof (fcparam);
640 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
641 PCI_MBOX_REGS2300_OFF;
642 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
643 }
644 #endif
645 #ifndef ISP_DISABLE_2322_SUPPORT
646 if (pa->pa_id == PCI_QLOGIC_ISP2322 ||
647 pa->pa_id == PCI_QLOGIC_ISP6322) {
648 isp->isp_mdvec = &mdvec_2322;
649 dstring = ": QLogic FC-AL and 2Gbps Fabric PCI-E HBA\n";
650 isp->isp_type = ISP_HA_FC_2322;
651 isp->isp_port = pa->pa_function;
652 mamt = sizeof (fcparam);
653 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
654 PCI_MBOX_REGS2300_OFF;
655 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
656 }
657 #endif
658 #ifndef ISP_DISABLE_2400_SUPPORT
659 if (pa->pa_id == PCI_QLOGIC_ISP2422 ||
660 pa->pa_id == PCI_QLOGIC_ISP2432) {
661 isp->isp_mdvec = &mdvec_2400;
662 if (pa->pa_id == PCI_QLOGIC_ISP2422) {
663 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-X HBA\n";
664 } else {
665 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-E HBA\n";
666 }
667 isp->isp_type = ISP_HA_FC_2400;
668 isp->isp_port = pa->pa_function;
669 mamt = sizeof (fcparam);
670 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
671 PCI_MBOX_REGS2400_OFF;
672 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
673 }
674 if (pa->pa_id == PCI_QLOGIC_ISP2532) {
675 isp->isp_mdvec = &mdvec_2500;
676 dstring = ": QLogic FC-AL and 8Gbps Fabric PCI-E HBA\n";
677 isp->isp_type = ISP_HA_FC_2500;
678 isp->isp_port = pa->pa_function;
679 mamt = sizeof (fcparam);
680 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
681 PCI_MBOX_REGS2400_OFF;
682 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
683 }
684 #endif
685 if (mamt == 0) {
686 return;
687 }
688
689 isp->isp_param = malloc(mamt, M_DEVBUF, M_WAITOK | M_ZERO);
690 mamt = sizeof (struct scsipi_channel) * isp->isp_nchan;
691 isp->isp_osinfo.chan = malloc(mamt, M_DEVBUF, M_WAITOK | M_ZERO);
692 isp->isp_osinfo.adapter.adapt_nchannels = isp->isp_nchan;
693
694 /*
695 * Set up logging levels.
696 */
697 #ifdef ISP_LOGDEFAULT
698 isp->isp_dblev = ISP_LOGDEFAULT;
699 #else
700 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR;
701 if (bootverbose)
702 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO;
703 #ifdef SCSIDEBUG
704 isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGDEBUG1|ISP_LOGDEBUG2;
705 #endif
706 #endif
707 if (isp->isp_dblev & ISP_LOGCONFIG) {
708 aprint_normal("\n");
709 } else {
710 aprint_normal("%s", dstring);
711 }
712
713 isp->isp_dmatag = pa->pa_dmat;
714 isp->isp_revision = rev;
715
716 /*
717 * Make sure that command register set sanely.
718 */
719 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
720 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE;
721
722 /*
723 * Not so sure about these- but I think it's important that they get
724 * enabled......
725 */
726 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
727 if (IS_2300(isp)) { /* per QLogic errata */
728 data &= ~PCI_COMMAND_INVALIDATE_ENABLE;
729 }
730 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data);
731
732 /*
733 * Make sure that the latency timer, cache line size,
734 * and ROM is disabled.
735 */
736 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
737 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
738 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT);
739 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT);
740 data |= (linesz << PCI_CACHELINE_SHIFT);
741 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data);
742
743 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR);
744 data &= ~1;
745 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data);
746
747 if (pci_intr_map(pa, &ih)) {
748 aprint_error_dev(self, "couldn't map interrupt\n");
749 free(isp->isp_param, M_DEVBUF);
750 free(isp->isp_osinfo.chan, M_DEVBUF);
751 return;
752 }
753 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf));
754 if (intrstr == NULL)
755 intrstr = "<I dunno>";
756 pcs->pci_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_BIO,
757 isp_pci_intr, isp, device_xname(self));
758 if (pcs->pci_ih == NULL) {
759 aprint_error_dev(self, "couldn't establish interrupt at %s\n",
760 intrstr);
761 free(isp->isp_param, M_DEVBUF);
762 free(isp->isp_osinfo.chan, M_DEVBUF);
763 return;
764 }
765
766 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
767
768 isp->isp_confopts = device_cfdata(self)->cf_flags;
769 ISP_LOCK(isp);
770 isp_reset(isp, 1);
771 if (isp->isp_state != ISP_RESETSTATE) {
772 ISP_UNLOCK(isp);
773 free(isp->isp_param, M_DEVBUF);
774 free(isp->isp_osinfo.chan, M_DEVBUF);
775 return;
776 }
777 isp_init(isp);
778 if (isp->isp_state != ISP_INITSTATE) {
779 isp_uninit(isp);
780 ISP_UNLOCK(isp);
781 free(isp->isp_param, M_DEVBUF);
782 free(isp->isp_osinfo.chan, M_DEVBUF);
783 return;
784 }
785 /*
786 * Do platform attach.
787 */
788 ISP_UNLOCK(isp);
789 isp_attach(isp);
790 }
791
792 #define IspVirt2Off(a, x) \
793 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \
794 _BLK_REG_SHFT] + ((x) & 0xff))
795
796 #define BXR2(pcs, off) \
797 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off)
798 #define BXW2(pcs, off, v) \
799 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v)
800 #define BXR4(pcs, off) \
801 bus_space_read_4(pcs->pci_st, pcs->pci_sh, off)
802 #define BXW4(pcs, off, v) \
803 bus_space_write_4(pcs->pci_st, pcs->pci_sh, off, v)
804
805
806 static int
isp_pci_rd_debounced(struct ispsoftc * isp,int off,uint16_t * rp)807 isp_pci_rd_debounced(struct ispsoftc *isp, int off, uint16_t *rp)
808 {
809 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
810 uint16_t val0, val1;
811 int i = 0;
812
813 do {
814 val0 = BXR2(pcs, IspVirt2Off(isp, off));
815 val1 = BXR2(pcs, IspVirt2Off(isp, off));
816 } while (val0 != val1 && ++i < 1000);
817 if (val0 != val1) {
818 return (1);
819 }
820 *rp = val0;
821 return (0);
822 }
823
824 #if !defined(ISP_DISABLE_2100_SUPPORT) && \
825 !defined(ISP_DISABLE_2200_SUPPORT) && \
826 !defined(ISP_DISABLE_1020_SUPPORT) && \
827 !defined(ISP_DISABLE_1080_SUPPORT) && \
828 !defined(ISP_DISABLE_12160_SUPPORT)
829 static int
isp_pci_rd_isr(struct ispsoftc * isp,uint32_t * isrp,uint16_t * semap,uint16_t * mbp)830 isp_pci_rd_isr(struct ispsoftc *isp, uint32_t *isrp,
831 uint16_t *semap, uint16_t *mbp)
832 {
833 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
834 uint16_t isr, sema;
835
836 if (IS_2100(isp)) {
837 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) {
838 return (0);
839 }
840 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) {
841 return (0);
842 }
843 } else {
844 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR));
845 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA));
846 }
847 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema);
848 isr &= INT_PENDING_MASK(isp);
849 sema &= BIU_SEMA_LOCK;
850 if (isr == 0 && sema == 0) {
851 return (0);
852 }
853 *isrp = isr;
854 if ((*semap = sema) != 0) {
855 if (IS_2100(isp)) {
856 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) {
857 return (0);
858 }
859 } else {
860 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0));
861 }
862 }
863 return (1);
864 }
865 #endif
866
867 #if !(defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_2322_SUPPORT))
868 static int
isp_pci_rd_isr_2300(struct ispsoftc * isp,uint32_t * isrp,uint16_t * semap,uint16_t * mbox0p)869 isp_pci_rd_isr_2300(struct ispsoftc *isp, uint32_t *isrp,
870 uint16_t *semap, uint16_t *mbox0p)
871 {
872 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
873 uint32_t r2hisr;
874
875 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) {
876 *isrp = 0;
877 return (0);
878 }
879 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh,
880 IspVirt2Off(pcs, BIU_R2HSTSLO));
881 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
882 if ((r2hisr & BIU_R2HST_INTR) == 0) {
883 *isrp = 0;
884 return (0);
885 }
886 switch (r2hisr & BIU_R2HST_ISTAT_MASK) {
887 case ISPR2HST_ROM_MBX_OK:
888 case ISPR2HST_ROM_MBX_FAIL:
889 case ISPR2HST_MBX_OK:
890 case ISPR2HST_MBX_FAIL:
891 case ISPR2HST_ASYNC_EVENT:
892 *isrp = r2hisr & 0xffff;
893 *mbox0p = (r2hisr >> 16);
894 *semap = 1;
895 return (1);
896 case ISPR2HST_RIO_16:
897 *isrp = r2hisr & 0xffff;
898 *mbox0p = ASYNC_RIO16_1;
899 *semap = 1;
900 return (1);
901 case ISPR2HST_FPOST:
902 *isrp = r2hisr & 0xffff;
903 *mbox0p = ASYNC_CMD_CMPLT;
904 *semap = 1;
905 return (1);
906 case ISPR2HST_FPOST_CTIO:
907 *isrp = r2hisr & 0xffff;
908 *mbox0p = ASYNC_CTIO_DONE;
909 *semap = 1;
910 return (1);
911 case ISPR2HST_RSPQ_UPDATE:
912 *isrp = r2hisr & 0xffff;
913 *mbox0p = 0;
914 *semap = 0;
915 return (1);
916 default:
917 return (0);
918 }
919 }
920 #endif
921
922 #ifndef ISP_DISABLE_2400_SUPPORT
923 static int
isp_pci_rd_isr_2400(ispsoftc_t * isp,uint32_t * isrp,uint16_t * semap,uint16_t * mbox0p)924 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp,
925 uint16_t *semap, uint16_t *mbox0p)
926 {
927 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
928 uint32_t r2hisr;
929
930 r2hisr = BXR4(pcs, IspVirt2Off(pcs, BIU2400_R2HSTSLO));
931 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
932 if ((r2hisr & BIU2400_R2HST_INTR) == 0) {
933 *isrp = 0;
934 return (0);
935 }
936 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) {
937 case ISP2400R2HST_ROM_MBX_OK:
938 case ISP2400R2HST_ROM_MBX_FAIL:
939 case ISP2400R2HST_MBX_OK:
940 case ISP2400R2HST_MBX_FAIL:
941 case ISP2400R2HST_ASYNC_EVENT:
942 *isrp = r2hisr & 0xffff;
943 *mbox0p = (r2hisr >> 16);
944 *semap = 1;
945 return (1);
946 case ISP2400R2HST_RSPQ_UPDATE:
947 case ISP2400R2HST_ATIO_RSPQ_UPDATE:
948 case ISP2400R2HST_ATIO_RQST_UPDATE:
949 *isrp = r2hisr & 0xffff;
950 *mbox0p = 0;
951 *semap = 0;
952 return (1);
953 default:
954 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
955 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
956 return (0);
957 }
958 }
959
960 static uint32_t
isp_pci_rd_reg_2400(ispsoftc_t * isp,int regoff)961 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff)
962 {
963 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
964 uint32_t rv;
965 int block = regoff & _BLK_REG_MASK;
966
967 switch (block) {
968 case BIU_BLOCK:
969 break;
970 case MBOX_BLOCK:
971 return (BXR2(pcs, IspVirt2Off(pcs, regoff)));
972 case SXP_BLOCK:
973 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff);
974 return (0xffffffff);
975 case RISC_BLOCK:
976 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff);
977 return (0xffffffff);
978 case DMA_BLOCK:
979 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff);
980 return (0xffffffff);
981 default:
982 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff);
983 return (0xffffffff);
984 }
985
986
987 switch (regoff) {
988 case BIU2400_FLASH_ADDR:
989 case BIU2400_FLASH_DATA:
990 case BIU2400_ICR:
991 case BIU2400_ISR:
992 case BIU2400_CSR:
993 case BIU2400_REQINP:
994 case BIU2400_REQOUTP:
995 case BIU2400_RSPINP:
996 case BIU2400_RSPOUTP:
997 case BIU2400_PRI_REQINP:
998 case BIU2400_PRI_REQOUTP:
999 case BIU2400_ATIO_RSPINP:
1000 case BIU2400_ATIO_RSPOUTP:
1001 case BIU2400_HCCR:
1002 case BIU2400_GPIOD:
1003 case BIU2400_GPIOE:
1004 case BIU2400_HSEMA:
1005 rv = BXR4(pcs, IspVirt2Off(pcs, regoff));
1006 break;
1007 case BIU2400_R2HSTSLO:
1008 rv = BXR4(pcs, IspVirt2Off(pcs, regoff));
1009 break;
1010 case BIU2400_R2HSTSHI:
1011 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)) >> 16;
1012 break;
1013 default:
1014 isp_prt(isp, ISP_LOGERR,
1015 "isp_pci_rd_reg_2400: unknown offset %x", regoff);
1016 rv = 0xffffffff;
1017 break;
1018 }
1019 return (rv);
1020 }
1021
1022 static void
isp_pci_wr_reg_2400(ispsoftc_t * isp,int regoff,uint32_t val)1023 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val)
1024 {
1025 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1026 int block = regoff & _BLK_REG_MASK;
1027
1028 switch (block) {
1029 case BIU_BLOCK:
1030 break;
1031 case MBOX_BLOCK:
1032 BXW2(pcs, IspVirt2Off(pcs, regoff), val);
1033 (void)BXR2(pcs, IspVirt2Off(pcs, regoff));
1034 return;
1035 case SXP_BLOCK:
1036 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff);
1037 return;
1038 case RISC_BLOCK:
1039 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff);
1040 return;
1041 case DMA_BLOCK:
1042 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff);
1043 return;
1044 default:
1045 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x",
1046 regoff);
1047 break;
1048 }
1049
1050 switch (regoff) {
1051 case BIU2400_FLASH_ADDR:
1052 case BIU2400_FLASH_DATA:
1053 case BIU2400_ICR:
1054 case BIU2400_ISR:
1055 case BIU2400_CSR:
1056 case BIU2400_REQINP:
1057 case BIU2400_REQOUTP:
1058 case BIU2400_RSPINP:
1059 case BIU2400_RSPOUTP:
1060 case BIU2400_PRI_REQINP:
1061 case BIU2400_PRI_REQOUTP:
1062 case BIU2400_ATIO_RSPINP:
1063 case BIU2400_ATIO_RSPOUTP:
1064 case BIU2400_HCCR:
1065 case BIU2400_GPIOD:
1066 case BIU2400_GPIOE:
1067 case BIU2400_HSEMA:
1068 BXW4(pcs, IspVirt2Off(pcs, regoff), val);
1069 (void)BXR4(pcs, IspVirt2Off(pcs, regoff));
1070 break;
1071 default:
1072 isp_prt(isp, ISP_LOGERR,
1073 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff);
1074 break;
1075 }
1076 }
1077 #endif
1078
1079 static uint32_t
isp_pci_rd_reg(struct ispsoftc * isp,int regoff)1080 isp_pci_rd_reg(struct ispsoftc *isp, int regoff)
1081 {
1082 uint32_t rv;
1083 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1084 int oldconf = 0;
1085
1086 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1087 /*
1088 * We will assume that someone has paused the RISC processor.
1089 */
1090 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1091 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1092 oldconf | BIU_PCI_CONF1_SXP);
1093 }
1094 rv = BXR2(pcs, IspVirt2Off(isp, regoff));
1095 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1096 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
1097 }
1098 return (rv);
1099 }
1100
1101 static void
isp_pci_wr_reg(struct ispsoftc * isp,int regoff,uint32_t val)1102 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, uint32_t val)
1103 {
1104 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1105 int oldconf = 0;
1106
1107 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1108 /*
1109 * We will assume that someone has paused the RISC processor.
1110 */
1111 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1112 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1113 oldconf | BIU_PCI_CONF1_SXP);
1114 }
1115 BXW2(pcs, IspVirt2Off(isp, regoff), val);
1116 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1117 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
1118 }
1119 }
1120
1121 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT))
1122 static uint32_t
isp_pci_rd_reg_1080(struct ispsoftc * isp,int regoff)1123 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff)
1124 {
1125 uint16_t rv, oc = 0;
1126 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1127
1128 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1129 uint16_t tc;
1130 /*
1131 * We will assume that someone has paused the RISC processor.
1132 */
1133 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1134 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1135 if (regoff & SXP_BANK1_SELECT)
1136 tc |= BIU_PCI1080_CONF1_SXP1;
1137 else
1138 tc |= BIU_PCI1080_CONF1_SXP0;
1139 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc);
1140 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1141 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1142 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1143 oc | BIU_PCI1080_CONF1_DMA);
1144 }
1145 rv = BXR2(pcs, IspVirt2Off(isp, regoff));
1146 if (oc) {
1147 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
1148 }
1149 return (rv);
1150 }
1151
1152 static void
isp_pci_wr_reg_1080(struct ispsoftc * isp,int regoff,uint32_t val)1153 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, uint32_t val)
1154 {
1155 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1156 int oc = 0;
1157
1158 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1159 uint16_t tc;
1160 /*
1161 * We will assume that someone has paused the RISC processor.
1162 */
1163 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1164 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1165 if (regoff & SXP_BANK1_SELECT)
1166 tc |= BIU_PCI1080_CONF1_SXP1;
1167 else
1168 tc |= BIU_PCI1080_CONF1_SXP0;
1169 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc);
1170 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1171 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1172 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1173 oc | BIU_PCI1080_CONF1_DMA);
1174 }
1175 BXW2(pcs, IspVirt2Off(isp, regoff), val);
1176 if (oc) {
1177 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
1178 }
1179 }
1180 #endif
1181
1182 static int
isp_pci_mbxdma(struct ispsoftc * isp)1183 isp_pci_mbxdma(struct ispsoftc *isp)
1184 {
1185 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1186 bus_dma_tag_t dmat = isp->isp_dmatag;
1187 bus_dma_segment_t sg;
1188 bus_size_t len, dbound;
1189 fcparam *fcp;
1190 int rs, i;
1191
1192 if (isp->isp_rquest_dma) /* been here before? */
1193 return (0);
1194
1195 if (isp->isp_type <= ISP_HA_SCSI_1040B) {
1196 dbound = 1 << 24;
1197 } else {
1198 /*
1199 * For 32-bit PCI DMA, the range is 32 bits or zero :-)
1200 */
1201 dbound = 0;
1202 }
1203 len = isp->isp_maxcmds * sizeof (isp_hdl_t);
1204 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK);
1205 if (isp->isp_xflist == NULL) {
1206 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array");
1207 return (1);
1208 }
1209 memset(isp->isp_xflist, 0, len);
1210 for (len = 0; len < isp->isp_maxcmds - 1; len++) {
1211 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1];
1212 }
1213 isp->isp_xffree = isp->isp_xflist;
1214 len = isp->isp_maxcmds * sizeof (bus_dmamap_t);
1215 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK);
1216 if (pcs->pci_xfer_dmap == NULL) {
1217 free(isp->isp_xflist, M_DEVBUF);
1218 isp->isp_xflist = NULL;
1219 isp_prt(isp, ISP_LOGERR, "cannot malloc DMA map array");
1220 return (1);
1221 }
1222 for (i = 0; i < isp->isp_maxcmds; i++) {
1223 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1,
1224 MAXPHYS, dbound, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) {
1225 isp_prt(isp, ISP_LOGERR, "cannot create DMA maps");
1226 break;
1227 }
1228 }
1229 if (i < isp->isp_maxcmds) {
1230 while (--i >= 0) {
1231 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]);
1232 }
1233 free(isp->isp_xflist, M_DEVBUF);
1234 free(pcs->pci_xfer_dmap, M_DEVBUF);
1235 isp->isp_xflist = NULL;
1236 pcs->pci_xfer_dmap = NULL;
1237 return (1);
1238 }
1239
1240 /*
1241 * Allocate and map the request queue.
1242 */
1243 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
1244 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 0)) {
1245 goto dmafail;
1246 }
1247 if (bus_dmamem_map(isp->isp_dmatag, &sg, rs, len,
1248 (void *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
1249 goto dmafail;
1250 }
1251 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT,
1252 &isp->isp_rqdmap)) {
1253 goto dmafail;
1254 }
1255 if (bus_dmamap_load(dmat, isp->isp_rqdmap, isp->isp_rquest, len, NULL,
1256 BUS_DMA_NOWAIT)) {
1257 goto dmafail;
1258 }
1259 isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr;
1260
1261 /*
1262 * Allocate and map the result queue.
1263 */
1264 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
1265 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs,
1266 BUS_DMA_NOWAIT)) {
1267 goto dmafail;
1268 }
1269 if (bus_dmamem_map(dmat, &sg, rs, len,
1270 (void *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
1271 goto dmafail;
1272 }
1273 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT,
1274 &isp->isp_rsdmap)) {
1275 goto dmafail;
1276 }
1277 if (bus_dmamap_load(dmat, isp->isp_rsdmap, isp->isp_result, len, NULL,
1278 BUS_DMA_NOWAIT)) {
1279 goto dmafail;
1280 }
1281 isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr;
1282
1283 if (IS_SCSI(isp)) {
1284 return (0);
1285 }
1286
1287 /*
1288 * Allocate and map an FC scratch area
1289 */
1290 fcp = isp->isp_param;
1291 len = ISP_FC_SCRLEN;
1292 if (bus_dmamem_alloc(dmat, len, sizeof (uint64_t), 0, &sg, 1, &rs,
1293 BUS_DMA_NOWAIT)) {
1294 goto dmafail;
1295 }
1296 if (bus_dmamem_map(dmat, &sg, rs, len,
1297 (void *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
1298 goto dmafail;
1299 }
1300 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT,
1301 &isp->isp_scdmap)) {
1302 goto dmafail;
1303 }
1304 if (bus_dmamap_load(dmat, isp->isp_scdmap, fcp->isp_scratch, len, NULL,
1305 BUS_DMA_NOWAIT)) {
1306 goto dmafail;
1307 }
1308 fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr;
1309 return (0);
1310 dmafail:
1311 isp_prt(isp, ISP_LOGERR, "mailbox DMA setup failure");
1312 for (i = 0; i < isp->isp_maxcmds; i++) {
1313 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]);
1314 }
1315 free(isp->isp_xflist, M_DEVBUF);
1316 free(pcs->pci_xfer_dmap, M_DEVBUF);
1317 isp->isp_xflist = NULL;
1318 pcs->pci_xfer_dmap = NULL;
1319 return (1);
1320 }
1321
1322 static int
isp_pci_dmasetup(struct ispsoftc * isp,struct scsipi_xfer * xs,void * arg)1323 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, void *arg)
1324 {
1325 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1326 ispreq_t *rq = arg;
1327 bus_dmamap_t dmap;
1328 bus_dma_segment_t *dm_segs;
1329 uint32_t nsegs, hidx;
1330 isp_ddir_t ddir;
1331
1332 hidx = isp_handle_index(isp, rq->req_handle);
1333 if (hidx == ISP_BAD_HANDLE_INDEX) {
1334 XS_SETERR(xs, HBA_BOTCH);
1335 return (CMD_COMPLETE);
1336 }
1337 dmap = pcs->pci_xfer_dmap[hidx];
1338 if (xs->datalen == 0) {
1339 ddir = ISP_NOXFR;
1340 nsegs = 0;
1341 dm_segs = NULL;
1342 } else {
1343 int error;
1344 uint32_t flag, flg2;
1345
1346 if (sizeof (bus_addr_t) > 4) {
1347 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) {
1348 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS;
1349 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) {
1350 rq->req_header.rqs_entry_type = RQSTYPE_A64;
1351 }
1352 }
1353
1354 if (xs->xs_control & XS_CTL_DATA_IN) {
1355 flg2 = BUS_DMASYNC_PREREAD;
1356 flag = BUS_DMA_READ;
1357 ddir = ISP_FROM_DEVICE;
1358 } else {
1359 flg2 = BUS_DMASYNC_PREWRITE;
1360 flag = BUS_DMA_WRITE;
1361 ddir = ISP_TO_DEVICE;
1362 }
1363 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data,
1364 xs->datalen, NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ?
1365 BUS_DMA_NOWAIT :
1366 BUS_DMA_WAITOK) | BUS_DMA_STREAMING | flag);
1367 if (error) {
1368 isp_prt(isp, ISP_LOGWARN, "unable to load DMA (%d)",
1369 error);
1370 XS_SETERR(xs, HBA_BOTCH);
1371 if (error == EAGAIN || error == ENOMEM) {
1372 return (CMD_EAGAIN);
1373 } else {
1374 return (CMD_COMPLETE);
1375 }
1376 }
1377 dm_segs = dmap->dm_segs;
1378 nsegs = dmap->dm_nsegs;
1379 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize,
1380 flg2);
1381 }
1382
1383 if (isp_send_cmd(isp, rq, dm_segs, nsegs, xs->datalen, ddir)
1384 != CMD_QUEUED) {
1385 return (CMD_EAGAIN);
1386 } else {
1387 return (CMD_QUEUED);
1388 }
1389 }
1390
1391 static int
isp_pci_intr(void * arg)1392 isp_pci_intr(void *arg)
1393 {
1394 uint32_t isr;
1395 uint16_t sema, mbox;
1396 struct ispsoftc *isp = arg;
1397
1398 isp->isp_intcnt++;
1399 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) {
1400 isp->isp_intbogus++;
1401 return (0);
1402 } else {
1403 isp->isp_osinfo.onintstack = 1;
1404 isp_intr(isp, isr, sema, mbox);
1405 isp->isp_osinfo.onintstack = 0;
1406 return (1);
1407 }
1408 }
1409
1410 static void
isp_pci_dmateardown(struct ispsoftc * isp,XS_T * xs,uint32_t handle)1411 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, uint32_t handle)
1412 {
1413 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1414 uint32_t hidx;
1415 bus_dmamap_t dmap;
1416
1417 hidx = isp_handle_index(isp, handle);
1418 if (hidx == ISP_BAD_HANDLE_INDEX) {
1419 isp_xs_prt(isp, xs, ISP_LOGERR, "bad handle on teardown");
1420 return;
1421 }
1422 dmap = pcs->pci_xfer_dmap[hidx];
1423 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize,
1424 xs->xs_control & XS_CTL_DATA_IN ?
1425 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1426 bus_dmamap_unload(isp->isp_dmatag, dmap);
1427 }
1428
1429 static void
isp_pci_reset0(ispsoftc_t * isp)1430 isp_pci_reset0(ispsoftc_t *isp)
1431 {
1432 ISP_DISABLE_INTS(isp);
1433 }
1434
1435 static void
isp_pci_reset1(ispsoftc_t * isp)1436 isp_pci_reset1(ispsoftc_t *isp)
1437 {
1438 if (!IS_24XX(isp)) {
1439 /* Make sure the BIOS is disabled */
1440 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
1441 }
1442 /* and enable interrupts */
1443 ISP_ENABLE_INTS(isp);
1444 }
1445
1446 static void
isp_pci_dumpregs(struct ispsoftc * isp,const char * msg)1447 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg)
1448 {
1449 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1450 if (msg)
1451 printf("%s: %s\n", device_xname(isp->isp_osinfo.dev), msg);
1452 if (IS_SCSI(isp))
1453 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1));
1454 else
1455 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR));
1456 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR),
1457 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA));
1458 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR));
1459
1460
1461 if (IS_SCSI(isp)) {
1462 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
1463 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n",
1464 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS),
1465 ISP_READ(isp, CDMA_FIFO_STS));
1466 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n",
1467 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS),
1468 ISP_READ(isp, DDMA_FIFO_STS));
1469 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n",
1470 ISP_READ(isp, SXP_INTERRUPT),
1471 ISP_READ(isp, SXP_GROSS_ERR),
1472 ISP_READ(isp, SXP_PINS_CTRL));
1473 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
1474 }
1475 printf(" mbox regs: %x %x %x %x %x\n",
1476 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1),
1477 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3),
1478 ISP_READ(isp, OUTMAILBOX4));
1479 printf(" PCI Status Command/Status=%x\n",
1480 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG));
1481 }
1482