1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
27
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
33 #include "i915_drv.h"
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
42
43 /**
44 * _wait_for - magic (register) wait macro
45 *
46 * Does the right thing for modeset paths when run under kdgb or similar atomic
47 * contexts. Note that it's important that we check the condition again after
48 * having timed out, since the timeout could be due to preemption or similar and
49 * we've never had a chance to check the condition before the timeout.
50 *
51 * TODO: When modesetting has fully transitioned to atomic, the below
52 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
53 * added.
54 */
55 #define _wait_for(COND, US, W) ({ \
56 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
57 int ret__; \
58 for (;;) { \
59 bool expired__ = time_after(jiffies, timeout__); \
60 if (COND) { \
61 ret__ = 0; \
62 break; \
63 } \
64 if (expired__) { \
65 ret__ = -ETIMEDOUT; \
66 break; \
67 } \
68 if ((W) && drm_can_sleep()) { \
69 usleep_range((W), (W)*2); \
70 } else { \
71 cpu_relax(); \
72 } \
73 } \
74 ret__; \
75 })
76
77 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
78
79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
82 #else
83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
84 #endif
85
86 #define _wait_for_atomic(COND, US, ATOMIC) \
87 ({ \
88 int cpu, ret, timeout = (US) * 1000; \
89 u64 base; \
90 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
91 if (!(ATOMIC)) { \
92 preempt_disable(); \
93 cpu = smp_processor_id(); \
94 } \
95 base = local_clock(); \
96 for (;;) { \
97 u64 now = local_clock(); \
98 if (!(ATOMIC)) \
99 preempt_enable(); \
100 if (COND) { \
101 ret = 0; \
102 break; \
103 } \
104 if (now - base >= timeout) { \
105 ret = -ETIMEDOUT; \
106 break; \
107 } \
108 cpu_relax(); \
109 if (!(ATOMIC)) { \
110 preempt_disable(); \
111 if (unlikely(cpu != smp_processor_id())) { \
112 timeout -= now - base; \
113 cpu = smp_processor_id(); \
114 base = local_clock(); \
115 } \
116 } \
117 } \
118 ret; \
119 })
120
121 #define wait_for_us(COND, US) \
122 ({ \
123 int ret__; \
124 BUILD_BUG_ON(!__builtin_constant_p(US)); \
125 if ((US) > 10) \
126 ret__ = _wait_for((COND), (US), 10); \
127 else \
128 ret__ = _wait_for_atomic((COND), (US), 0); \
129 ret__; \
130 })
131
132 #define wait_for_atomic_us(COND, US) \
133 ({ \
134 BUILD_BUG_ON(!__builtin_constant_p(US)); \
135 BUILD_BUG_ON((US) > 50000); \
136 _wait_for_atomic((COND), (US), 1); \
137 })
138
139 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
140
141 #define KHz(x) (1000 * (x))
142 #define MHz(x) KHz(1000 * (x))
143
144 /*
145 * Display related stuff
146 */
147
148 /* store information about an Ixxx DVO */
149 /* The i830->i865 use multiple DVOs with multiple i2cs */
150 /* the i915, i945 have a single sDVO i2c bus - which is different */
151 #define MAX_OUTPUTS 6
152 /* maximum connectors per crtcs in the mode set */
153
154 /* Maximum cursor sizes */
155 #define GEN2_CURSOR_WIDTH 64
156 #define GEN2_CURSOR_HEIGHT 64
157 #define MAX_CURSOR_WIDTH 256
158 #define MAX_CURSOR_HEIGHT 256
159
160 #define INTEL_I2C_BUS_DVO 1
161 #define INTEL_I2C_BUS_SDVO 2
162
163 /* these are outputs from the chip - integrated only
164 external chips are via DVO or SDVO output */
165 enum intel_output_type {
166 INTEL_OUTPUT_UNUSED = 0,
167 INTEL_OUTPUT_ANALOG = 1,
168 INTEL_OUTPUT_DVO = 2,
169 INTEL_OUTPUT_SDVO = 3,
170 INTEL_OUTPUT_LVDS = 4,
171 INTEL_OUTPUT_TVOUT = 5,
172 INTEL_OUTPUT_HDMI = 6,
173 INTEL_OUTPUT_DP = 7,
174 INTEL_OUTPUT_EDP = 8,
175 INTEL_OUTPUT_DSI = 9,
176 INTEL_OUTPUT_UNKNOWN = 10,
177 INTEL_OUTPUT_DP_MST = 11,
178 };
179
180 #define INTEL_DVO_CHIP_NONE 0
181 #define INTEL_DVO_CHIP_LVDS 1
182 #define INTEL_DVO_CHIP_TMDS 2
183 #define INTEL_DVO_CHIP_TVOUT 4
184
185 #define INTEL_DSI_VIDEO_MODE 0
186 #define INTEL_DSI_COMMAND_MODE 1
187
188 struct intel_framebuffer {
189 struct drm_framebuffer base;
190 struct drm_i915_gem_object *obj;
191 struct intel_rotation_info rot_info;
192
193 /* for each plane in the normal GTT view */
194 struct {
195 unsigned int x, y;
196 } normal[2];
197 /* for each plane in the rotated GTT view */
198 struct {
199 unsigned int x, y;
200 unsigned int pitch; /* pixels */
201 } rotated[2];
202 };
203
204 struct intel_fbdev {
205 struct drm_fb_helper helper;
206 struct intel_framebuffer *fb;
207 struct i915_vma *vma;
208 async_cookie_t cookie;
209 int preferred_bpp;
210 };
211
212 struct intel_encoder {
213 struct drm_encoder base;
214
215 enum intel_output_type type;
216 enum port port;
217 unsigned int cloneable;
218 void (*hot_plug)(struct intel_encoder *);
219 bool (*compute_config)(struct intel_encoder *,
220 struct intel_crtc_state *,
221 struct drm_connector_state *);
222 void (*pre_pll_enable)(struct intel_encoder *,
223 const struct intel_crtc_state *,
224 const struct drm_connector_state *);
225 void (*pre_enable)(struct intel_encoder *,
226 const struct intel_crtc_state *,
227 const struct drm_connector_state *);
228 void (*enable)(struct intel_encoder *,
229 const struct intel_crtc_state *,
230 const struct drm_connector_state *);
231 void (*disable)(struct intel_encoder *,
232 const struct intel_crtc_state *,
233 const struct drm_connector_state *);
234 void (*post_disable)(struct intel_encoder *,
235 const struct intel_crtc_state *,
236 const struct drm_connector_state *);
237 void (*post_pll_disable)(struct intel_encoder *,
238 const struct intel_crtc_state *,
239 const struct drm_connector_state *);
240 /* Read out the current hw state of this connector, returning true if
241 * the encoder is active. If the encoder is enabled it also set the pipe
242 * it is connected to in the pipe parameter. */
243 bool (*get_hw_state)(struct intel_encoder *, enum i915_pipe *pipe);
244 /* Reconstructs the equivalent mode flags for the current hardware
245 * state. This must be called _after_ display->get_pipe_config has
246 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
247 * be set correctly before calling this function. */
248 void (*get_config)(struct intel_encoder *,
249 struct intel_crtc_state *pipe_config);
250 /* Returns a mask of power domains that need to be referenced as part
251 * of the hardware state readout code. */
252 u64 (*get_power_domains)(struct intel_encoder *encoder);
253 /*
254 * Called during system suspend after all pending requests for the
255 * encoder are flushed (for example for DP AUX transactions) and
256 * device interrupts are disabled.
257 */
258 void (*suspend)(struct intel_encoder *);
259 int crtc_mask;
260 enum hpd_pin hpd_pin;
261 enum intel_display_power_domain power_domain;
262 /* for communication with audio component; protected by av_mutex */
263 const struct drm_connector *audio_connector;
264 };
265
266 struct intel_panel {
267 struct drm_display_mode *fixed_mode;
268 struct drm_display_mode *alt_fixed_mode;
269 struct drm_display_mode *downclock_mode;
270
271 /* backlight */
272 struct {
273 bool present;
274 u32 level;
275 u32 min;
276 u32 max;
277 bool enabled;
278 bool combination_mode; /* gen 2/4 only */
279 bool active_low_pwm;
280 bool alternate_pwm_increment; /* lpt+ */
281
282 /* PWM chip */
283 bool util_pin_active_low; /* bxt+ */
284 u8 controller; /* bxt+ only */
285 struct pwm_device *pwm;
286
287 struct backlight_device *device;
288
289 /* Connector and platform specific backlight functions */
290 int (*setup)(struct intel_connector *connector, enum i915_pipe pipe);
291 uint32_t (*get)(struct intel_connector *connector);
292 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
293 void (*disable)(const struct drm_connector_state *conn_state);
294 void (*enable)(const struct intel_crtc_state *crtc_state,
295 const struct drm_connector_state *conn_state);
296 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
297 uint32_t hz);
298 void (*power)(struct intel_connector *, bool enable);
299 } backlight;
300 };
301
302 struct intel_connector {
303 struct drm_connector base;
304 /*
305 * The fixed encoder this connector is connected to.
306 */
307 struct intel_encoder *encoder;
308
309 /* ACPI device id for ACPI and driver cooperation */
310 u32 acpi_device_id;
311
312 /* Reads out the current hw, returning true if the connector is enabled
313 * and active (i.e. dpms ON state). */
314 bool (*get_hw_state)(struct intel_connector *);
315
316 /* Panel info for eDP and LVDS */
317 struct intel_panel panel;
318
319 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
320 struct edid *edid;
321 struct edid *detect_edid;
322
323 /* since POLL and HPD connectors may use the same HPD line keep the native
324 state of connector->polled in case hotplug storm detection changes it */
325 u8 polled;
326
327 void *port; /* store this opaque as its illegal to dereference it */
328
329 struct intel_dp *mst_port;
330
331 /* Work struct to schedule a uevent on link train failure */
332 struct work_struct modeset_retry_work;
333 };
334
335 struct intel_digital_connector_state {
336 struct drm_connector_state base;
337
338 enum hdmi_force_audio force_audio;
339 int broadcast_rgb;
340 };
341
342 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
343
344 struct dpll {
345 /* given values */
346 int n;
347 int m1, m2;
348 int p1, p2;
349 /* derived values */
350 int dot;
351 int vco;
352 int m;
353 int p;
354 };
355
356 struct intel_atomic_state {
357 struct drm_atomic_state base;
358
359 struct {
360 /*
361 * Logical state of cdclk (used for all scaling, watermark,
362 * etc. calculations and checks). This is computed as if all
363 * enabled crtcs were active.
364 */
365 struct intel_cdclk_state logical;
366
367 /*
368 * Actual state of cdclk, can be different from the logical
369 * state only when all crtc's are DPMS off.
370 */
371 struct intel_cdclk_state actual;
372 } cdclk;
373
374 bool dpll_set, modeset;
375
376 /*
377 * Does this transaction change the pipes that are active? This mask
378 * tracks which CRTC's have changed their active state at the end of
379 * the transaction (not counting the temporary disable during modesets).
380 * This mask should only be non-zero when intel_state->modeset is true,
381 * but the converse is not necessarily true; simply changing a mode may
382 * not flip the final active status of any CRTC's
383 */
384 unsigned int active_pipe_changes;
385
386 unsigned int active_crtcs;
387 /* minimum acceptable cdclk for each pipe */
388 int min_cdclk[I915_MAX_PIPES];
389
390 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
391
392 /*
393 * Current watermarks can't be trusted during hardware readout, so
394 * don't bother calculating intermediate watermarks.
395 */
396 bool skip_intermediate_wm;
397
398 /* Gen9+ only */
399 struct skl_wm_values wm_results;
400
401 struct i915_sw_fence commit_ready;
402
403 struct llist_node freed;
404 };
405
406 struct intel_plane_state {
407 struct drm_plane_state base;
408 struct drm_rect clip;
409 struct i915_vma *vma;
410
411 struct {
412 u32 offset;
413 int x, y;
414 } main;
415 struct {
416 u32 offset;
417 int x, y;
418 } aux;
419
420 /* plane control register */
421 u32 ctl;
422
423 /*
424 * scaler_id
425 * = -1 : not using a scaler
426 * >= 0 : using a scalers
427 *
428 * plane requiring a scaler:
429 * - During check_plane, its bit is set in
430 * crtc_state->scaler_state.scaler_users by calling helper function
431 * update_scaler_plane.
432 * - scaler_id indicates the scaler it got assigned.
433 *
434 * plane doesn't require a scaler:
435 * - this can happen when scaling is no more required or plane simply
436 * got disabled.
437 * - During check_plane, corresponding bit is reset in
438 * crtc_state->scaler_state.scaler_users by calling helper function
439 * update_scaler_plane.
440 */
441 int scaler_id;
442
443 struct drm_intel_sprite_colorkey ckey;
444 };
445
446 struct intel_initial_plane_config {
447 struct intel_framebuffer *fb;
448 unsigned int tiling;
449 int size;
450 u32 base;
451 };
452
453 #define SKL_MIN_SRC_W 8
454 #define SKL_MAX_SRC_W 4096
455 #define SKL_MIN_SRC_H 8
456 #define SKL_MAX_SRC_H 4096
457 #define SKL_MIN_DST_W 8
458 #define SKL_MAX_DST_W 4096
459 #define SKL_MIN_DST_H 8
460 #define SKL_MAX_DST_H 4096
461
462 struct intel_scaler {
463 int in_use;
464 uint32_t mode;
465 };
466
467 struct intel_crtc_scaler_state {
468 #define SKL_NUM_SCALERS 2
469 struct intel_scaler scalers[SKL_NUM_SCALERS];
470
471 /*
472 * scaler_users: keeps track of users requesting scalers on this crtc.
473 *
474 * If a bit is set, a user is using a scaler.
475 * Here user can be a plane or crtc as defined below:
476 * bits 0-30 - plane (bit position is index from drm_plane_index)
477 * bit 31 - crtc
478 *
479 * Instead of creating a new index to cover planes and crtc, using
480 * existing drm_plane_index for planes which is well less than 31
481 * planes and bit 31 for crtc. This should be fine to cover all
482 * our platforms.
483 *
484 * intel_atomic_setup_scalers will setup available scalers to users
485 * requesting scalers. It will gracefully fail if request exceeds
486 * avilability.
487 */
488 #define SKL_CRTC_INDEX 31
489 unsigned scaler_users;
490
491 /* scaler used by crtc for panel fitting purpose */
492 int scaler_id;
493 };
494
495 /* drm_mode->private_flags */
496 #define I915_MODE_FLAG_INHERITED 1
497 /* Flag to get scanline using frame time stamps */
498 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
499
500 struct intel_pipe_wm {
501 struct intel_wm_level wm[5];
502 uint32_t linetime;
503 bool fbc_wm_enabled;
504 bool pipe_enabled;
505 bool sprites_enabled;
506 bool sprites_scaled;
507 };
508
509 struct skl_plane_wm {
510 struct skl_wm_level wm[8];
511 struct skl_wm_level trans_wm;
512 };
513
514 struct skl_pipe_wm {
515 struct skl_plane_wm planes[I915_MAX_PLANES];
516 uint32_t linetime;
517 };
518
519 enum vlv_wm_level {
520 VLV_WM_LEVEL_PM2,
521 VLV_WM_LEVEL_PM5,
522 VLV_WM_LEVEL_DDR_DVFS,
523 NUM_VLV_WM_LEVELS,
524 };
525
526 struct vlv_wm_state {
527 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
528 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
529 uint8_t num_levels;
530 bool cxsr;
531 };
532
533 struct vlv_fifo_state {
534 u16 plane[I915_MAX_PLANES];
535 };
536
537 enum g4x_wm_level {
538 G4X_WM_LEVEL_NORMAL,
539 G4X_WM_LEVEL_SR,
540 G4X_WM_LEVEL_HPLL,
541 NUM_G4X_WM_LEVELS,
542 };
543
544 struct g4x_wm_state {
545 struct g4x_pipe_wm wm;
546 struct g4x_sr_wm sr;
547 struct g4x_sr_wm hpll;
548 bool cxsr;
549 bool hpll_en;
550 bool fbc_en;
551 };
552
553 struct intel_crtc_wm_state {
554 union {
555 struct {
556 /*
557 * Intermediate watermarks; these can be
558 * programmed immediately since they satisfy
559 * both the current configuration we're
560 * switching away from and the new
561 * configuration we're switching to.
562 */
563 struct intel_pipe_wm intermediate;
564
565 /*
566 * Optimal watermarks, programmed post-vblank
567 * when this state is committed.
568 */
569 struct intel_pipe_wm optimal;
570 } ilk;
571
572 struct {
573 /* gen9+ only needs 1-step wm programming */
574 struct skl_pipe_wm optimal;
575 struct skl_ddb_entry ddb;
576 } skl;
577
578 struct {
579 /* "raw" watermarks (not inverted) */
580 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
581 /* intermediate watermarks (inverted) */
582 struct vlv_wm_state intermediate;
583 /* optimal watermarks (inverted) */
584 struct vlv_wm_state optimal;
585 /* display FIFO split */
586 struct vlv_fifo_state fifo_state;
587 } vlv;
588
589 struct {
590 /* "raw" watermarks */
591 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
592 /* intermediate watermarks */
593 struct g4x_wm_state intermediate;
594 /* optimal watermarks */
595 struct g4x_wm_state optimal;
596 } g4x;
597 };
598
599 /*
600 * Platforms with two-step watermark programming will need to
601 * update watermark programming post-vblank to switch from the
602 * safe intermediate watermarks to the optimal final
603 * watermarks.
604 */
605 bool need_postvbl_update;
606 };
607
608 struct intel_crtc_state {
609 struct drm_crtc_state base;
610
611 /**
612 * quirks - bitfield with hw state readout quirks
613 *
614 * For various reasons the hw state readout code might not be able to
615 * completely faithfully read out the current state. These cases are
616 * tracked with quirk flags so that fastboot and state checker can act
617 * accordingly.
618 */
619 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
620 unsigned long quirks;
621
622 unsigned fb_bits; /* framebuffers to flip */
623 bool update_pipe; /* can a fast modeset be performed? */
624 bool disable_cxsr;
625 bool update_wm_pre, update_wm_post; /* watermarks are updated */
626 bool fb_changed; /* fb on any of the planes is changed */
627 bool fifo_changed; /* FIFO split is changed */
628
629 /* Pipe source size (ie. panel fitter input size)
630 * All planes will be positioned inside this space,
631 * and get clipped at the edges. */
632 int pipe_src_w, pipe_src_h;
633
634 /*
635 * Pipe pixel rate, adjusted for
636 * panel fitter/pipe scaler downscaling.
637 */
638 unsigned int pixel_rate;
639
640 /* Whether to set up the PCH/FDI. Note that we never allow sharing
641 * between pch encoders and cpu encoders. */
642 bool has_pch_encoder;
643
644 /* Are we sending infoframes on the attached port */
645 bool has_infoframe;
646
647 /* CPU Transcoder for the pipe. Currently this can only differ from the
648 * pipe on Haswell and later (where we have a special eDP transcoder)
649 * and Broxton (where we have special DSI transcoders). */
650 enum transcoder cpu_transcoder;
651
652 /*
653 * Use reduced/limited/broadcast rbg range, compressing from the full
654 * range fed into the crtcs.
655 */
656 bool limited_color_range;
657
658 /* Bitmask of encoder types (enum intel_output_type)
659 * driven by the pipe.
660 */
661 unsigned int output_types;
662
663 /* Whether we should send NULL infoframes. Required for audio. */
664 bool has_hdmi_sink;
665
666 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
667 * has_dp_encoder is set. */
668 bool has_audio;
669
670 /*
671 * Enable dithering, used when the selected pipe bpp doesn't match the
672 * plane bpp.
673 */
674 bool dither;
675
676 /*
677 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
678 * compliance video pattern tests.
679 * Disable dither only if it is a compliance test request for
680 * 18bpp.
681 */
682 bool dither_force_disable;
683
684 /* Controls for the clock computation, to override various stages. */
685 bool clock_set;
686
687 /* SDVO TV has a bunch of special case. To make multifunction encoders
688 * work correctly, we need to track this at runtime.*/
689 bool sdvo_tv_clock;
690
691 /*
692 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
693 * required. This is set in the 2nd loop of calling encoder's
694 * ->compute_config if the first pick doesn't work out.
695 */
696 bool bw_constrained;
697
698 /* Settings for the intel dpll used on pretty much everything but
699 * haswell. */
700 struct dpll dpll;
701
702 /* Selected dpll when shared or NULL. */
703 struct intel_shared_dpll *shared_dpll;
704
705 /* Actual register state of the dpll, for shared dpll cross-checking. */
706 struct intel_dpll_hw_state dpll_hw_state;
707
708 /* DSI PLL registers */
709 struct {
710 u32 ctrl, div;
711 } dsi_pll;
712
713 int pipe_bpp;
714 struct intel_link_m_n dp_m_n;
715
716 /* m2_n2 for eDP downclock */
717 struct intel_link_m_n dp_m2_n2;
718 bool has_drrs;
719
720 bool has_psr;
721 bool has_psr2;
722
723 /*
724 * Frequence the dpll for the port should run at. Differs from the
725 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
726 * already multiplied by pixel_multiplier.
727 */
728 int port_clock;
729
730 /* Used by SDVO (and if we ever fix it, HDMI). */
731 unsigned pixel_multiplier;
732
733 uint8_t lane_count;
734
735 /*
736 * Used by platforms having DP/HDMI PHY with programmable lane
737 * latency optimization.
738 */
739 uint8_t lane_lat_optim_mask;
740
741 /* Panel fitter controls for gen2-gen4 + VLV */
742 struct {
743 u32 control;
744 u32 pgm_ratios;
745 u32 lvds_border_bits;
746 } gmch_pfit;
747
748 /* Panel fitter placement and size for Ironlake+ */
749 struct {
750 u32 pos;
751 u32 size;
752 bool enabled;
753 bool force_thru;
754 } pch_pfit;
755
756 /* FDI configuration, only valid if has_pch_encoder is set. */
757 int fdi_lanes;
758 struct intel_link_m_n fdi_m_n;
759
760 bool ips_enabled;
761 bool ips_force_disable;
762
763 bool enable_fbc;
764
765 bool double_wide;
766
767 int pbn;
768
769 struct intel_crtc_scaler_state scaler_state;
770
771 /* w/a for waiting 2 vblanks during crtc enable */
772 enum i915_pipe hsw_workaround_pipe;
773
774 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
775 bool disable_lp_wm;
776
777 struct intel_crtc_wm_state wm;
778
779 /* Gamma mode programmed on the pipe */
780 uint32_t gamma_mode;
781
782 /* bitmask of visible planes (enum plane_id) */
783 u8 active_planes;
784
785 /* HDMI scrambling status */
786 bool hdmi_scrambling;
787
788 /* HDMI High TMDS char rate ratio */
789 bool hdmi_high_tmds_clock_ratio;
790
791 /* output format is YCBCR 4:2:0 */
792 bool ycbcr420;
793 };
794
795 struct intel_crtc {
796 struct drm_crtc base;
797 enum i915_pipe pipe;
798 enum plane plane;
799 /*
800 * Whether the crtc and the connected output pipeline is active. Implies
801 * that crtc->enabled is set, i.e. the current mode configuration has
802 * some outputs connected to this crtc.
803 */
804 bool active;
805 u8 plane_ids_mask;
806 unsigned long long enabled_power_domains;
807 struct intel_overlay *overlay;
808
809 struct intel_crtc_state *config;
810
811 /* global reset count when the last flip was submitted */
812 unsigned int reset_count;
813
814 /* Access to these should be protected by dev_priv->irq_lock. */
815 bool cpu_fifo_underrun_disabled;
816 bool pch_fifo_underrun_disabled;
817
818 /* per-pipe watermark state */
819 struct {
820 /* watermarks currently being used */
821 union {
822 struct intel_pipe_wm ilk;
823 struct vlv_wm_state vlv;
824 struct g4x_wm_state g4x;
825 } active;
826 } wm;
827
828 int scanline_offset;
829
830 struct {
831 unsigned start_vbl_count;
832 ktime_t start_vbl_time;
833 int min_vbl, max_vbl;
834 int scanline_start;
835 } debug;
836
837 /* scalers available on this crtc */
838 int num_scalers;
839 };
840
841 struct intel_plane {
842 struct drm_plane base;
843 u8 plane;
844 enum plane_id id;
845 enum i915_pipe pipe;
846 bool can_scale;
847 int max_downscale;
848 uint32_t frontbuffer_bit;
849
850 struct {
851 u32 base, cntl, size;
852 } cursor;
853
854 /*
855 * NOTE: Do not place new plane state fields here (e.g., when adding
856 * new plane properties). New runtime state should now be placed in
857 * the intel_plane_state structure and accessed via plane_state.
858 */
859
860 void (*update_plane)(struct intel_plane *plane,
861 const struct intel_crtc_state *crtc_state,
862 const struct intel_plane_state *plane_state);
863 void (*disable_plane)(struct intel_plane *plane,
864 struct intel_crtc *crtc);
865 bool (*get_hw_state)(struct intel_plane *plane);
866 int (*check_plane)(struct intel_plane *plane,
867 struct intel_crtc_state *crtc_state,
868 struct intel_plane_state *state);
869 };
870
871 struct intel_watermark_params {
872 u16 fifo_size;
873 u16 max_wm;
874 u8 default_wm;
875 u8 guard_size;
876 u8 cacheline_size;
877 };
878
879 struct cxsr_latency {
880 bool is_desktop : 1;
881 bool is_ddr3 : 1;
882 u16 fsb_freq;
883 u16 mem_freq;
884 u16 display_sr;
885 u16 display_hpll_disable;
886 u16 cursor_sr;
887 u16 cursor_hpll_disable;
888 };
889
890 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
891 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
892 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
893 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
894 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
895 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
896 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
897 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
898 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
899
900 struct intel_hdmi {
901 i915_reg_t hdmi_reg;
902 int ddc_bus;
903 struct {
904 enum drm_dp_dual_mode_type type;
905 int max_tmds_clock;
906 } dp_dual_mode;
907 bool has_hdmi_sink;
908 bool has_audio;
909 bool rgb_quant_range_selectable;
910 struct intel_connector *attached_connector;
911 };
912
913 struct intel_dp_mst_encoder;
914 #define DP_MAX_DOWNSTREAM_PORTS 0x10
915
916 /*
917 * enum link_m_n_set:
918 * When platform provides two set of M_N registers for dp, we can
919 * program them and switch between them incase of DRRS.
920 * But When only one such register is provided, we have to program the
921 * required divider value on that registers itself based on the DRRS state.
922 *
923 * M1_N1 : Program dp_m_n on M1_N1 registers
924 * dp_m2_n2 on M2_N2 registers (If supported)
925 *
926 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
927 * M2_N2 registers are not supported
928 */
929
930 enum link_m_n_set {
931 /* Sets the m1_n1 and m2_n2 */
932 M1_N1 = 0,
933 M2_N2
934 };
935
936 struct intel_dp_compliance_data {
937 unsigned long edid;
938 uint8_t video_pattern;
939 uint16_t hdisplay, vdisplay;
940 uint8_t bpc;
941 };
942
943 struct intel_dp_compliance {
944 unsigned long test_type;
945 struct intel_dp_compliance_data test_data;
946 bool test_active;
947 int test_link_rate;
948 u8 test_lane_count;
949 };
950
951 struct intel_dp {
952 i915_reg_t output_reg;
953 i915_reg_t aux_ch_ctl_reg;
954 i915_reg_t aux_ch_data_reg[5];
955 uint32_t DP;
956 int link_rate;
957 uint8_t lane_count;
958 uint8_t sink_count;
959 bool link_mst;
960 bool has_audio;
961 bool detect_done;
962 bool channel_eq_status;
963 bool reset_link_params;
964 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
965 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
966 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
967 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
968 /* source rates */
969 int num_source_rates;
970 const int *source_rates;
971 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
972 int num_sink_rates;
973 int sink_rates[DP_MAX_SUPPORTED_RATES];
974 bool use_rate_select;
975 /* intersection of source and sink rates */
976 int num_common_rates;
977 int common_rates[DP_MAX_SUPPORTED_RATES];
978 /* Max lane count for the current link */
979 int max_link_lane_count;
980 /* Max rate for the current link */
981 int max_link_rate;
982 /* sink or branch descriptor */
983 struct drm_dp_desc desc;
984 struct drm_dp_aux aux;
985 enum intel_display_power_domain aux_power_domain;
986 uint8_t train_set[4];
987 int panel_power_up_delay;
988 int panel_power_down_delay;
989 int panel_power_cycle_delay;
990 int backlight_on_delay;
991 int backlight_off_delay;
992 struct delayed_work panel_vdd_work;
993 bool want_panel_vdd;
994 unsigned long last_power_on;
995 unsigned long last_backlight_off;
996 ktime_t panel_power_off_time;
997
998 struct notifier_block edp_notifier;
999
1000 /*
1001 * Pipe whose power sequencer is currently locked into
1002 * this port. Only relevant on VLV/CHV.
1003 */
1004 enum i915_pipe pps_pipe;
1005 /*
1006 * Pipe currently driving the port. Used for preventing
1007 * the use of the PPS for any pipe currentrly driving
1008 * external DP as that will mess things up on VLV.
1009 */
1010 enum i915_pipe active_pipe;
1011 /*
1012 * Set if the sequencer may be reset due to a power transition,
1013 * requiring a reinitialization. Only relevant on BXT.
1014 */
1015 bool pps_reset;
1016 struct edp_power_seq pps_delays;
1017
1018 bool can_mst; /* this port supports mst */
1019 bool is_mst;
1020 int active_mst_links;
1021 /* connector directly attached - won't be use for modeset in mst world */
1022 struct intel_connector *attached_connector;
1023
1024 /* mst connector list */
1025 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1026 struct drm_dp_mst_topology_mgr mst_mgr;
1027
1028 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1029 /*
1030 * This function returns the value we have to program the AUX_CTL
1031 * register with to kick off an AUX transaction.
1032 */
1033 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1034 bool has_aux_irq,
1035 int send_bytes,
1036 uint32_t aux_clock_divider);
1037
1038 /* This is called before a link training is starterd */
1039 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1040
1041 /* Displayport compliance testing */
1042 struct intel_dp_compliance compliance;
1043 };
1044
1045 struct intel_lspcon {
1046 bool active;
1047 enum drm_lspcon_mode mode;
1048 };
1049
1050 struct intel_digital_port {
1051 struct intel_encoder base;
1052 enum port port;
1053 u32 saved_port_bits;
1054 struct intel_dp dp;
1055 struct intel_hdmi hdmi;
1056 struct intel_lspcon lspcon;
1057 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1058 bool release_cl2_override;
1059 uint8_t max_lanes;
1060 enum intel_display_power_domain ddi_io_power_domain;
1061
1062 void (*write_infoframe)(struct drm_encoder *encoder,
1063 const struct intel_crtc_state *crtc_state,
1064 unsigned int type,
1065 const void *frame, ssize_t len);
1066 void (*set_infoframes)(struct drm_encoder *encoder,
1067 bool enable,
1068 const struct intel_crtc_state *crtc_state,
1069 const struct drm_connector_state *conn_state);
1070 bool (*infoframe_enabled)(struct drm_encoder *encoder,
1071 const struct intel_crtc_state *pipe_config);
1072 };
1073
1074 struct intel_dp_mst_encoder {
1075 struct intel_encoder base;
1076 enum i915_pipe pipe;
1077 struct intel_digital_port *primary;
1078 struct intel_connector *connector;
1079 };
1080
1081 static inline enum dpio_channel
vlv_dport_to_channel(struct intel_digital_port * dport)1082 vlv_dport_to_channel(struct intel_digital_port *dport)
1083 {
1084 switch (dport->port) {
1085 case PORT_B:
1086 case PORT_D:
1087 return DPIO_CH0;
1088 case PORT_C:
1089 return DPIO_CH1;
1090 default:
1091 BUG();
1092 }
1093 }
1094
1095 static inline enum dpio_phy
vlv_dport_to_phy(struct intel_digital_port * dport)1096 vlv_dport_to_phy(struct intel_digital_port *dport)
1097 {
1098 switch (dport->port) {
1099 case PORT_B:
1100 case PORT_C:
1101 return DPIO_PHY0;
1102 case PORT_D:
1103 return DPIO_PHY1;
1104 default:
1105 BUG();
1106 }
1107 }
1108
1109 static inline enum dpio_channel
vlv_pipe_to_channel(enum i915_pipe pipe)1110 vlv_pipe_to_channel(enum i915_pipe pipe)
1111 {
1112 switch (pipe) {
1113 case PIPE_A:
1114 case PIPE_C:
1115 return DPIO_CH0;
1116 case PIPE_B:
1117 return DPIO_CH1;
1118 default:
1119 BUG();
1120 }
1121 }
1122
1123 static inline struct intel_crtc *
intel_get_crtc_for_pipe(struct drm_i915_private * dev_priv,enum i915_pipe pipe)1124 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe)
1125 {
1126 return dev_priv->pipe_to_crtc_mapping[pipe];
1127 }
1128
1129 static inline struct intel_crtc *
intel_get_crtc_for_plane(struct drm_i915_private * dev_priv,enum plane plane)1130 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1131 {
1132 return dev_priv->plane_to_crtc_mapping[plane];
1133 }
1134
1135 struct intel_load_detect_pipe {
1136 struct drm_atomic_state *restore_state;
1137 };
1138
1139 static inline struct intel_encoder *
intel_attached_encoder(struct drm_connector * connector)1140 intel_attached_encoder(struct drm_connector *connector)
1141 {
1142 return to_intel_connector(connector)->encoder;
1143 }
1144
1145 static inline struct intel_digital_port *
enc_to_dig_port(struct drm_encoder * encoder)1146 enc_to_dig_port(struct drm_encoder *encoder)
1147 {
1148 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1149
1150 switch (intel_encoder->type) {
1151 case INTEL_OUTPUT_UNKNOWN:
1152 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1153 case INTEL_OUTPUT_DP:
1154 case INTEL_OUTPUT_EDP:
1155 case INTEL_OUTPUT_HDMI:
1156 return container_of(encoder, struct intel_digital_port,
1157 base.base);
1158 default:
1159 return NULL;
1160 }
1161 }
1162
1163 static inline struct intel_dp_mst_encoder *
enc_to_mst(struct drm_encoder * encoder)1164 enc_to_mst(struct drm_encoder *encoder)
1165 {
1166 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1167 }
1168
enc_to_intel_dp(struct drm_encoder * encoder)1169 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1170 {
1171 return &enc_to_dig_port(encoder)->dp;
1172 }
1173
1174 static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp * intel_dp)1175 dp_to_dig_port(struct intel_dp *intel_dp)
1176 {
1177 return container_of(intel_dp, struct intel_digital_port, dp);
1178 }
1179
1180 static inline struct intel_lspcon *
dp_to_lspcon(struct intel_dp * intel_dp)1181 dp_to_lspcon(struct intel_dp *intel_dp)
1182 {
1183 return &dp_to_dig_port(intel_dp)->lspcon;
1184 }
1185
1186 static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi * intel_hdmi)1187 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1188 {
1189 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1190 }
1191
1192 static inline struct intel_plane_state *
intel_atomic_get_new_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)1193 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1194 struct intel_plane *plane)
1195 {
1196 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1197 &plane->base));
1198 }
1199
1200 static inline struct intel_crtc_state *
intel_atomic_get_old_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)1201 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1202 struct intel_crtc *crtc)
1203 {
1204 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1205 &crtc->base));
1206 }
1207
1208 static inline struct intel_crtc_state *
intel_atomic_get_new_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)1209 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1210 struct intel_crtc *crtc)
1211 {
1212 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1213 &crtc->base));
1214 }
1215
1216 /* intel_fifo_underrun.c */
1217 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1218 enum i915_pipe pipe, bool enable);
1219 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1220 enum i915_pipe pch_transcoder,
1221 bool enable);
1222 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1223 enum i915_pipe pipe);
1224 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1225 enum i915_pipe pch_transcoder);
1226 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1227 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1228
1229 /* i915_irq.c */
1230 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1231 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1232 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1233 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1234 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1235 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1236 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1237
gen6_sanitize_rps_pm_mask(const struct drm_i915_private * i915,u32 mask)1238 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1239 u32 mask)
1240 {
1241 return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1242 }
1243
1244 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1245 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
intel_irqs_enabled(struct drm_i915_private * dev_priv)1246 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1247 {
1248 /*
1249 * We only use drm_irq_uninstall() at unload and VT switch, so
1250 * this is the only thing we need to check.
1251 */
1252 return dev_priv->runtime_pm.irqs_enabled;
1253 }
1254
1255 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1256 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1257 u8 pipe_mask);
1258 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1259 u8 pipe_mask);
1260 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1261 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1262 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1263
1264 /* intel_crt.c */
1265 void intel_crt_init(struct drm_i915_private *dev_priv);
1266 void intel_crt_reset(struct drm_encoder *encoder);
1267
1268 /* intel_ddi.c */
1269 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1270 const struct intel_crtc_state *old_crtc_state,
1271 const struct drm_connector_state *old_conn_state);
1272 void hsw_fdi_link_train(struct intel_crtc *crtc,
1273 const struct intel_crtc_state *crtc_state);
1274 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1275 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1276 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum i915_pipe *pipe);
1277 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1278 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1279 enum transcoder cpu_transcoder);
1280 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1281 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
1282 struct intel_encoder *
1283 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1284 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1285 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1286 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1287 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1288 struct intel_crtc *intel_crtc);
1289 void intel_ddi_get_config(struct intel_encoder *encoder,
1290 struct intel_crtc_state *pipe_config);
1291
1292 void intel_ddi_clock_get(struct intel_encoder *encoder,
1293 struct intel_crtc_state *pipe_config);
1294 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1295 bool state);
1296 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1297 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1298 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1299
1300 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1301 int plane, unsigned int height);
1302
1303 /* intel_audio.c */
1304 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1305 void intel_audio_codec_enable(struct intel_encoder *encoder,
1306 const struct intel_crtc_state *crtc_state,
1307 const struct drm_connector_state *conn_state);
1308 void intel_audio_codec_disable(struct intel_encoder *encoder);
1309 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1310 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1311 void intel_audio_init(struct drm_i915_private *dev_priv);
1312 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1313
1314 /* intel_cdclk.c */
1315 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1316 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1317 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1318 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1319 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1320 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1321 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1322 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1323 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1324 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1325 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1326 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1327 const struct intel_cdclk_state *b);
1328 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1329 const struct intel_cdclk_state *cdclk_state);
1330
1331 /* intel_display.c */
1332 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe);
1333 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe);
1334 enum i915_pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1335 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1336 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1337 const char *name, u32 reg, int ref_freq);
1338 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1339 const char *name, u32 reg);
1340 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1341 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1342 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1343 unsigned int intel_fb_xy_to_linear(int x, int y,
1344 const struct intel_plane_state *state,
1345 int plane);
1346 void intel_add_fb_offsets(int *x, int *y,
1347 const struct intel_plane_state *state, int plane);
1348 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1349 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1350 void intel_mark_busy(struct drm_i915_private *dev_priv);
1351 void intel_mark_idle(struct drm_i915_private *dev_priv);
1352 int intel_display_suspend(struct drm_device *dev);
1353 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1354 void intel_encoder_destroy(struct drm_encoder *encoder);
1355 int intel_connector_init(struct intel_connector *);
1356 struct intel_connector *intel_connector_alloc(void);
1357 void intel_connector_free(struct intel_connector *connector);
1358 bool intel_connector_get_hw_state(struct intel_connector *connector);
1359 void intel_connector_attach_encoder(struct intel_connector *connector,
1360 struct intel_encoder *encoder);
1361 struct drm_display_mode *
1362 intel_encoder_current_mode(struct intel_encoder *encoder);
1363
1364 enum i915_pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1365 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1366 struct drm_file *file_priv);
1367 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1368 enum i915_pipe pipe);
1369 static inline bool
intel_crtc_has_type(const struct intel_crtc_state * crtc_state,enum intel_output_type type)1370 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1371 enum intel_output_type type)
1372 {
1373 return crtc_state->output_types & (1 << type);
1374 }
1375 static inline bool
intel_crtc_has_dp_encoder(const struct intel_crtc_state * crtc_state)1376 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1377 {
1378 return crtc_state->output_types &
1379 ((1 << INTEL_OUTPUT_DP) |
1380 (1 << INTEL_OUTPUT_DP_MST) |
1381 (1 << INTEL_OUTPUT_EDP));
1382 }
1383 static inline void
intel_wait_for_vblank(struct drm_i915_private * dev_priv,enum i915_pipe pipe)1384 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum i915_pipe pipe)
1385 {
1386 drm_wait_one_vblank(&dev_priv->drm, pipe);
1387 }
1388 static inline void
intel_wait_for_vblank_if_active(struct drm_i915_private * dev_priv,int pipe)1389 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1390 {
1391 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1392
1393 if (crtc->active)
1394 intel_wait_for_vblank(dev_priv, pipe);
1395 }
1396
1397 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1398
1399 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1400 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1401 struct intel_digital_port *dport,
1402 unsigned int expected_mask);
1403 int intel_get_load_detect_pipe(struct drm_connector *connector,
1404 const struct drm_display_mode *mode,
1405 struct intel_load_detect_pipe *old,
1406 struct drm_modeset_acquire_ctx *ctx);
1407 void intel_release_load_detect_pipe(struct drm_connector *connector,
1408 struct intel_load_detect_pipe *old,
1409 struct drm_modeset_acquire_ctx *ctx);
1410 struct i915_vma *
1411 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1412 void intel_unpin_fb_vma(struct i915_vma *vma);
1413 struct drm_framebuffer *
1414 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1415 struct drm_mode_fb_cmd2 *mode_cmd);
1416 int intel_prepare_plane_fb(struct drm_plane *plane,
1417 struct drm_plane_state *new_state);
1418 void intel_cleanup_plane_fb(struct drm_plane *plane,
1419 struct drm_plane_state *old_state);
1420 int intel_plane_atomic_get_property(struct drm_plane *plane,
1421 const struct drm_plane_state *state,
1422 struct drm_property *property,
1423 uint64_t *val);
1424 int intel_plane_atomic_set_property(struct drm_plane *plane,
1425 struct drm_plane_state *state,
1426 struct drm_property *property,
1427 uint64_t val);
1428 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1429 struct drm_crtc_state *crtc_state,
1430 const struct intel_plane_state *old_plane_state,
1431 struct drm_plane_state *plane_state);
1432
1433 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1434 enum i915_pipe pipe);
1435
1436 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
1437 const struct dpll *dpll);
1438 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum i915_pipe pipe);
1439 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1440
1441 /* modesetting asserts */
1442 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1443 enum i915_pipe pipe);
1444 void assert_pll(struct drm_i915_private *dev_priv,
1445 enum i915_pipe pipe, bool state);
1446 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1447 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1448 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1449 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1450 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1451 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1452 enum i915_pipe pipe, bool state);
1453 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1454 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1455 void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, bool state);
1456 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1457 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1458 u32 intel_compute_tile_offset(int *x, int *y,
1459 const struct intel_plane_state *state, int plane);
1460 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1461 void intel_finish_reset(struct drm_i915_private *dev_priv);
1462 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1463 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1464 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1465 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1466 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1467 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1468 unsigned int skl_cdclk_get_vco(unsigned int freq);
1469 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1470 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1471 void intel_dp_get_m_n(struct intel_crtc *crtc,
1472 struct intel_crtc_state *pipe_config);
1473 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1474 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1475 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1476 struct dpll *best_clock);
1477 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1478
1479 bool intel_crtc_active(struct intel_crtc *crtc);
1480 void hsw_enable_ips(struct intel_crtc *crtc);
1481 void hsw_disable_ips(struct intel_crtc *crtc);
1482 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1483 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1484 struct intel_crtc_state *pipe_config);
1485
1486 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1487 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1488
intel_plane_ggtt_offset(const struct intel_plane_state * state)1489 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1490 {
1491 return i915_ggtt_offset(state->vma);
1492 }
1493
1494 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1495 const struct intel_plane_state *plane_state);
1496 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1497 unsigned int rotation);
1498 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1499 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1500
1501 /* intel_csr.c */
1502 void intel_csr_ucode_init(struct drm_i915_private *);
1503 void intel_csr_load_program(struct drm_i915_private *);
1504 void intel_csr_ucode_fini(struct drm_i915_private *);
1505 void intel_csr_ucode_suspend(struct drm_i915_private *);
1506 void intel_csr_ucode_resume(struct drm_i915_private *);
1507
1508 /* intel_dp.c */
1509 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1510 enum port port);
1511 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1512 struct intel_connector *intel_connector);
1513 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1514 int link_rate, uint8_t lane_count,
1515 bool link_mst);
1516 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1517 int link_rate, uint8_t lane_count);
1518 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1519 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1520 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1521 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1522 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1523 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1524 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1525 bool intel_dp_compute_config(struct intel_encoder *encoder,
1526 struct intel_crtc_state *pipe_config,
1527 struct drm_connector_state *conn_state);
1528 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1529 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1530 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1531 bool long_hpd);
1532 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1533 const struct drm_connector_state *conn_state);
1534 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1535 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1536 void intel_edp_panel_on(struct intel_dp *intel_dp);
1537 void intel_edp_panel_off(struct intel_dp *intel_dp);
1538 void intel_dp_mst_suspend(struct drm_device *dev);
1539 void intel_dp_mst_resume(struct drm_device *dev);
1540 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1541 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1542 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1543 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1544 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1545 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1546 void intel_plane_destroy(struct drm_plane *plane);
1547 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1548 const struct intel_crtc_state *crtc_state);
1549 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1550 const struct intel_crtc_state *crtc_state);
1551 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1552 unsigned int frontbuffer_bits);
1553 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1554 unsigned int frontbuffer_bits);
1555
1556 void
1557 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1558 uint8_t dp_train_pat);
1559 void
1560 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1561 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1562 uint8_t
1563 intel_dp_voltage_max(struct intel_dp *intel_dp);
1564 uint8_t
1565 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1566 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1567 uint8_t *link_bw, uint8_t *rate_select);
1568 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1569 bool
1570 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1571
intel_dp_unused_lane_mask(int lane_count)1572 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1573 {
1574 return ~((1 << lane_count) - 1) & 0xf;
1575 }
1576
1577 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1578 int intel_dp_link_required(int pixel_clock, int bpp);
1579 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1580 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1581 struct intel_digital_port *port);
1582
1583 /* intel_dp_aux_backlight.c */
1584 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1585
1586 /* intel_dp_mst.c */
1587 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1588 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1589 /* intel_dsi.c */
1590 void intel_dsi_init(struct drm_i915_private *dev_priv);
1591
1592 /* intel_dsi_dcs_backlight.c */
1593 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1594
1595 /* intel_dvo.c */
1596 void intel_dvo_init(struct drm_i915_private *dev_priv);
1597 /* intel_hotplug.c */
1598 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1599
1600
1601 /* legacy fbdev emulation in intel_fbdev.c */
1602 #ifdef CONFIG_DRM_FBDEV_EMULATION
1603 extern int intel_fbdev_init(struct drm_device *dev);
1604 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1605 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1606 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1607 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1608 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1609 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1610 #else
intel_fbdev_init(struct drm_device * dev)1611 static inline int intel_fbdev_init(struct drm_device *dev)
1612 {
1613 return 0;
1614 }
1615
intel_fbdev_initial_config_async(struct drm_device * dev)1616 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1617 {
1618 }
1619
intel_fbdev_unregister(struct drm_i915_private * dev_priv)1620 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1621 {
1622 }
1623
intel_fbdev_fini(struct drm_i915_private * dev_priv)1624 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1625 {
1626 }
1627
intel_fbdev_set_suspend(struct drm_device * dev,int state,bool synchronous)1628 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1629 {
1630 }
1631
intel_fbdev_output_poll_changed(struct drm_device * dev)1632 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1633 {
1634 }
1635
intel_fbdev_restore_mode(struct drm_device * dev)1636 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1637 {
1638 }
1639 #endif
1640
1641 /* intel_fbc.c */
1642 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1643 struct drm_atomic_state *state);
1644 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1645 void intel_fbc_pre_update(struct intel_crtc *crtc,
1646 struct intel_crtc_state *crtc_state,
1647 struct intel_plane_state *plane_state);
1648 void intel_fbc_post_update(struct intel_crtc *crtc);
1649 void intel_fbc_init(struct drm_i915_private *dev_priv);
1650 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1651 void intel_fbc_enable(struct intel_crtc *crtc,
1652 struct intel_crtc_state *crtc_state,
1653 struct intel_plane_state *plane_state);
1654 void intel_fbc_disable(struct intel_crtc *crtc);
1655 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1656 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1657 unsigned int frontbuffer_bits,
1658 enum fb_op_origin origin);
1659 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1660 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1661 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1662 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1663
1664 /* intel_hdmi.c */
1665 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1666 enum port port);
1667 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1668 struct intel_connector *intel_connector);
1669 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1670 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1671 struct intel_crtc_state *pipe_config,
1672 struct drm_connector_state *conn_state);
1673 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1674 struct drm_connector *connector,
1675 bool high_tmds_clock_ratio,
1676 bool scrambling);
1677 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1678 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1679
1680
1681 /* intel_lvds.c */
1682 void intel_lvds_init(struct drm_i915_private *dev_priv);
1683 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1684 bool intel_is_dual_link_lvds(struct drm_device *dev);
1685
1686
1687 /* intel_modes.c */
1688 int intel_connector_update_modes(struct drm_connector *connector,
1689 struct edid *edid);
1690 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1691 void intel_attach_force_audio_property(struct drm_connector *connector);
1692 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1693 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1694
1695
1696 /* intel_overlay.c */
1697 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1698 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1699 int intel_overlay_switch_off(struct intel_overlay *overlay);
1700 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1701 struct drm_file *file_priv);
1702 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1703 struct drm_file *file_priv);
1704 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1705
1706
1707 /* intel_panel.c */
1708 int intel_panel_init(struct intel_panel *panel,
1709 struct drm_display_mode *fixed_mode,
1710 struct drm_display_mode *alt_fixed_mode,
1711 struct drm_display_mode *downclock_mode);
1712 void intel_panel_fini(struct intel_panel *panel);
1713 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1714 struct drm_display_mode *adjusted_mode);
1715 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1716 struct intel_crtc_state *pipe_config,
1717 int fitting_mode);
1718 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1719 struct intel_crtc_state *pipe_config,
1720 int fitting_mode);
1721 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1722 u32 level, u32 max);
1723 int intel_panel_setup_backlight(struct drm_connector *connector,
1724 enum i915_pipe pipe);
1725 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1726 const struct drm_connector_state *conn_state);
1727 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1728 void intel_panel_destroy_backlight(struct drm_connector *connector);
1729 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1730 extern struct drm_display_mode *intel_find_panel_downclock(
1731 struct drm_i915_private *dev_priv,
1732 struct drm_display_mode *fixed_mode,
1733 struct drm_connector *connector);
1734
1735 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1736 int intel_backlight_device_register(struct intel_connector *connector);
1737 void intel_backlight_device_unregister(struct intel_connector *connector);
1738 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
intel_backlight_device_register(struct intel_connector * connector)1739 static inline int intel_backlight_device_register(struct intel_connector *connector)
1740 {
1741 return 0;
1742 }
intel_backlight_device_unregister(struct intel_connector * connector)1743 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1744 {
1745 }
1746 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1747
1748
1749 /* intel_psr.c */
1750 void intel_psr_enable(struct intel_dp *intel_dp,
1751 const struct intel_crtc_state *crtc_state);
1752 void intel_psr_disable(struct intel_dp *intel_dp,
1753 const struct intel_crtc_state *old_crtc_state);
1754 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1755 unsigned frontbuffer_bits);
1756 void intel_psr_flush(struct drm_i915_private *dev_priv,
1757 unsigned frontbuffer_bits,
1758 enum fb_op_origin origin);
1759 void intel_psr_init(struct drm_i915_private *dev_priv);
1760 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1761 unsigned frontbuffer_bits);
1762 void intel_psr_compute_config(struct intel_dp *intel_dp,
1763 struct intel_crtc_state *crtc_state);
1764
1765 /* intel_runtime_pm.c */
1766 int intel_power_domains_init(struct drm_i915_private *);
1767 void intel_power_domains_fini(struct drm_i915_private *);
1768 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1769 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1770 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1771 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1772 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1773 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1774 const char *
1775 intel_display_power_domain_str(enum intel_display_power_domain domain);
1776
1777 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1778 enum intel_display_power_domain domain);
1779 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1780 enum intel_display_power_domain domain);
1781 void intel_display_power_get(struct drm_i915_private *dev_priv,
1782 enum intel_display_power_domain domain);
1783 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1784 enum intel_display_power_domain domain);
1785 void intel_display_power_put(struct drm_i915_private *dev_priv,
1786 enum intel_display_power_domain domain);
1787
1788 static inline void
assert_rpm_device_not_suspended(struct drm_i915_private * dev_priv)1789 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1790 {
1791 WARN_ONCE(dev_priv->runtime_pm.suspended,
1792 "Device suspended during HW access\n");
1793 }
1794
1795 static inline void
assert_rpm_wakelock_held(struct drm_i915_private * dev_priv)1796 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1797 {
1798 assert_rpm_device_not_suspended(dev_priv);
1799 WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1800 "RPM wakelock ref not held during HW access");
1801 }
1802
1803 /**
1804 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1805 * @dev_priv: i915 device instance
1806 *
1807 * This function disable asserts that check if we hold an RPM wakelock
1808 * reference, while keeping the device-not-suspended checks still enabled.
1809 * It's meant to be used only in special circumstances where our rule about
1810 * the wakelock refcount wrt. the device power state doesn't hold. According
1811 * to this rule at any point where we access the HW or want to keep the HW in
1812 * an active state we must hold an RPM wakelock reference acquired via one of
1813 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1814 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1815 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1816 * users should avoid using this function.
1817 *
1818 * Any calls to this function must have a symmetric call to
1819 * enable_rpm_wakeref_asserts().
1820 */
1821 static inline void
disable_rpm_wakeref_asserts(struct drm_i915_private * dev_priv)1822 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1823 {
1824 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
1825 }
1826
1827 /**
1828 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1829 * @dev_priv: i915 device instance
1830 *
1831 * This function re-enables the RPM assert checks after disabling them with
1832 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1833 * circumstances otherwise its use should be avoided.
1834 *
1835 * Any calls to this function must have a symmetric call to
1836 * disable_rpm_wakeref_asserts().
1837 */
1838 static inline void
enable_rpm_wakeref_asserts(struct drm_i915_private * dev_priv)1839 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1840 {
1841 atomic_dec(&dev_priv->runtime_pm.wakeref_count);
1842 }
1843
1844 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1845 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1846 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1847 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1848
1849 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1850
1851 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1852 bool override, unsigned int mask);
1853 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1854 enum dpio_channel ch, bool override);
1855
1856
1857 /* intel_pm.c */
1858 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1859 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1860 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1861 void intel_update_watermarks(struct intel_crtc *crtc);
1862 void intel_init_pm(struct drm_i915_private *dev_priv);
1863 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1864 void intel_pm_setup(struct drm_i915_private *dev_priv);
1865 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1866 void intel_gpu_ips_teardown(void);
1867 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1868 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1869 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1870 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1871 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1872 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1873 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1874 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1875 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1876 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1877 void gen6_rps_boost(struct drm_i915_gem_request *rq,
1878 struct intel_rps_client *rps);
1879 void g4x_wm_get_hw_state(struct drm_device *dev);
1880 void vlv_wm_get_hw_state(struct drm_device *dev);
1881 void ilk_wm_get_hw_state(struct drm_device *dev);
1882 void skl_wm_get_hw_state(struct drm_device *dev);
1883 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1884 struct skl_ddb_allocation *ddb /* out */);
1885 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1886 struct skl_pipe_wm *out);
1887 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
1888 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1889 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1890 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1891 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1892 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1893 const struct skl_wm_level *l2);
1894 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
1895 const struct skl_ddb_entry **entries,
1896 const struct skl_ddb_entry *ddb,
1897 int ignore);
1898 bool ilk_disable_lp_wm(struct drm_device *dev);
1899 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1900 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
1901 struct intel_crtc_state *cstate);
1902 void intel_init_ipc(struct drm_i915_private *dev_priv);
1903 void intel_enable_ipc(struct drm_i915_private *dev_priv);
intel_rc6_enabled(void)1904 static inline int intel_rc6_enabled(void)
1905 {
1906 return i915_modparams.enable_rc6;
1907 }
1908
1909 /* intel_sdvo.c */
1910 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1911 i915_reg_t reg, enum port port);
1912
1913
1914 /* intel_sprite.c */
1915 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1916 int usecs);
1917 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1918 enum i915_pipe pipe, int plane);
1919 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1920 struct drm_file *file_priv);
1921 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
1922 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
1923 void skl_update_plane(struct intel_plane *plane,
1924 const struct intel_crtc_state *crtc_state,
1925 const struct intel_plane_state *plane_state);
1926 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
1927 bool skl_plane_get_hw_state(struct intel_plane *plane);
1928
1929 /* intel_tv.c */
1930 void intel_tv_init(struct drm_i915_private *dev_priv);
1931
1932 /* intel_atomic.c */
1933 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
1934 const struct drm_connector_state *state,
1935 struct drm_property *property,
1936 uint64_t *val);
1937 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
1938 struct drm_connector_state *state,
1939 struct drm_property *property,
1940 uint64_t val);
1941 int intel_digital_connector_atomic_check(struct drm_connector *conn,
1942 struct drm_connector_state *new_state);
1943 struct drm_connector_state *
1944 intel_digital_connector_duplicate_state(struct drm_connector *connector);
1945
1946 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1947 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1948 struct drm_crtc_state *state);
1949 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1950 void intel_atomic_state_clear(struct drm_atomic_state *);
1951
1952 static inline struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state * state,struct intel_crtc * crtc)1953 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1954 struct intel_crtc *crtc)
1955 {
1956 struct drm_crtc_state *crtc_state;
1957 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1958 if (IS_ERR(crtc_state))
1959 return ERR_CAST(crtc_state);
1960
1961 return to_intel_crtc_state(crtc_state);
1962 }
1963
1964 static inline struct intel_crtc_state *
intel_atomic_get_existing_crtc_state(struct drm_atomic_state * state,struct intel_crtc * crtc)1965 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1966 struct intel_crtc *crtc)
1967 {
1968 struct drm_crtc_state *crtc_state;
1969
1970 crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1971
1972 if (crtc_state)
1973 return to_intel_crtc_state(crtc_state);
1974 else
1975 return NULL;
1976 }
1977
1978 static inline struct intel_plane_state *
intel_atomic_get_existing_plane_state(struct drm_atomic_state * state,struct intel_plane * plane)1979 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1980 struct intel_plane *plane)
1981 {
1982 struct drm_plane_state *plane_state;
1983
1984 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1985
1986 return to_intel_plane_state(plane_state);
1987 }
1988
1989 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
1990 struct intel_crtc *intel_crtc,
1991 struct intel_crtc_state *crtc_state);
1992
1993 /* intel_atomic_plane.c */
1994 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1995 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1996 void intel_plane_destroy_state(struct drm_plane *plane,
1997 struct drm_plane_state *state);
1998 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1999 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2000 struct intel_crtc_state *crtc_state,
2001 const struct intel_plane_state *old_plane_state,
2002 struct intel_plane_state *intel_state);
2003
2004 /* intel_color.c */
2005 void intel_color_init(struct drm_crtc *crtc);
2006 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2007 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2008 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2009
2010 /* intel_lspcon.c */
2011 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2012 void lspcon_resume(struct intel_lspcon *lspcon);
2013 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2014
2015 /* intel_pipe_crc.c */
2016 int intel_pipe_crc_create(struct drm_minor *minor);
2017 #ifdef CONFIG_DEBUG_FS
2018 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2019 size_t *values_cnt);
2020 #else
2021 #define intel_crtc_set_crc_source NULL
2022 #endif
2023 extern const struct file_operations i915_display_crc_ctl_fops;
2024 #endif /* __INTEL_DRV_H__ */
2025