1 /* $NetBSD: intel_device_info.h,v 1.2 2021/12/18 23:45:28 riastradh Exp $ */ 2 3 /* 4 * Copyright © 2014-2017 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _INTEL_DEVICE_INFO_H_ 28 #define _INTEL_DEVICE_INFO_H_ 29 30 #include <uapi/drm/i915_drm.h> 31 32 #include "display/intel_display.h" 33 34 #include "gt/intel_engine_types.h" 35 #include "gt/intel_context_types.h" 36 #include "gt/intel_sseu.h" 37 38 struct drm_printer; 39 struct drm_i915_private; 40 41 /* Keep in gen based order, and chronological order within a gen */ 42 enum intel_platform { 43 INTEL_PLATFORM_UNINITIALIZED = 0, 44 /* gen2 */ 45 INTEL_I830, 46 INTEL_I845G, 47 INTEL_I85X, 48 INTEL_I865G, 49 /* gen3 */ 50 INTEL_I915G, 51 INTEL_I915GM, 52 INTEL_I945G, 53 INTEL_I945GM, 54 INTEL_G33, 55 INTEL_PINEVIEW, 56 /* gen4 */ 57 INTEL_I965G, 58 INTEL_I965GM, 59 INTEL_G45, 60 INTEL_GM45, 61 /* gen5 */ 62 INTEL_IRONLAKE, 63 /* gen6 */ 64 INTEL_SANDYBRIDGE, 65 /* gen7 */ 66 INTEL_IVYBRIDGE, 67 INTEL_VALLEYVIEW, 68 INTEL_HASWELL, 69 /* gen8 */ 70 INTEL_BROADWELL, 71 INTEL_CHERRYVIEW, 72 /* gen9 */ 73 INTEL_SKYLAKE, 74 INTEL_BROXTON, 75 INTEL_KABYLAKE, 76 INTEL_GEMINILAKE, 77 INTEL_COFFEELAKE, 78 /* gen10 */ 79 INTEL_CANNONLAKE, 80 /* gen11 */ 81 INTEL_ICELAKE, 82 INTEL_ELKHARTLAKE, 83 /* gen12 */ 84 INTEL_TIGERLAKE, 85 INTEL_MAX_PLATFORMS 86 }; 87 88 /* 89 * Subplatform bits share the same namespace per parent platform. In other words 90 * it is fine for the same bit to be used on multiple parent platforms. 91 */ 92 93 #define INTEL_SUBPLATFORM_BITS (3) 94 95 /* HSW/BDW/SKL/KBL/CFL */ 96 #define INTEL_SUBPLATFORM_ULT (0) 97 #define INTEL_SUBPLATFORM_ULX (1) 98 99 /* CNL/ICL */ 100 #define INTEL_SUBPLATFORM_PORTF (0) 101 102 enum intel_ppgtt_type { 103 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, 104 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, 105 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, 106 }; 107 108 #define DEV_INFO_FOR_EACH_FLAG(func) \ 109 func(is_mobile); \ 110 func(is_lp); \ 111 func(require_force_probe); \ 112 func(is_dgfx); \ 113 /* Keep has_* in alphabetical order */ \ 114 func(has_64bit_reloc); \ 115 func(gpu_reset_clobbers_display); \ 116 func(has_reset_engine); \ 117 func(has_fpga_dbg); \ 118 func(has_global_mocs); \ 119 func(has_gt_uc); \ 120 func(has_l3_dpf); \ 121 func(has_llc); \ 122 func(has_logical_ring_contexts); \ 123 func(has_logical_ring_elsq); \ 124 func(has_logical_ring_preemption); \ 125 func(has_pooled_eu); \ 126 func(has_rc6); \ 127 func(has_rc6p); \ 128 func(has_rps); \ 129 func(has_runtime_pm); \ 130 func(has_snoop); \ 131 func(has_coherent_ggtt); \ 132 func(unfenced_needs_alignment); \ 133 func(hws_needs_physical); 134 135 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 136 /* Keep in alphabetical order */ \ 137 func(cursor_needs_physical); \ 138 func(has_csr); \ 139 func(has_ddi); \ 140 func(has_dp_mst); \ 141 func(has_dsb); \ 142 func(has_dsc); \ 143 func(has_fbc); \ 144 func(has_gmch); \ 145 func(has_hdcp); \ 146 func(has_hotplug); \ 147 func(has_ipc); \ 148 func(has_modular_fia); \ 149 func(has_overlay); \ 150 func(has_psr); \ 151 func(overlay_needs_physical); \ 152 func(supports_tv); 153 154 struct intel_device_info { 155 u16 gen_mask; 156 157 u8 gen; 158 u8 gt; /* GT number, 0 if undefined */ 159 intel_engine_mask_t engine_mask; /* Engines supported by the HW */ 160 161 enum intel_platform platform; 162 163 enum intel_ppgtt_type ppgtt_type; 164 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ 165 166 unsigned int page_sizes; /* page sizes supported by the HW */ 167 168 u32 memory_regions; /* regions supported by the HW */ 169 170 u32 display_mmio_offset; 171 172 u8 pipe_mask; 173 174 #define DEFINE_FLAG(name) u8 name:1 175 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); 176 #undef DEFINE_FLAG 177 178 struct { 179 #define DEFINE_FLAG(name) u8 name:1 180 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 181 #undef DEFINE_FLAG 182 } display; 183 184 u16 ddb_size; /* in blocks */ 185 186 /* Register offsets for the various display pipes and transcoders */ 187 int pipe_offsets[I915_MAX_TRANSCODERS]; 188 int trans_offsets[I915_MAX_TRANSCODERS]; 189 int cursor_offsets[I915_MAX_PIPES]; 190 191 struct color_luts { 192 u32 degamma_lut_size; 193 u32 gamma_lut_size; 194 u32 degamma_lut_tests; 195 u32 gamma_lut_tests; 196 } color; 197 }; 198 199 struct intel_runtime_info { 200 /* 201 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into 202 * into single runtime conditionals, and also to provide groundwork 203 * for future per platform, or per SKU build optimizations. 204 * 205 * Array can be extended when necessary if the corresponding 206 * BUILD_BUG_ON is hit. 207 */ 208 u32 platform_mask[2]; 209 210 u16 device_id; 211 212 u8 num_sprites[I915_MAX_PIPES]; 213 u8 num_scalers[I915_MAX_PIPES]; 214 215 u8 num_engines; 216 217 /* Slice/subslice/EU info */ 218 struct sseu_dev_info sseu; 219 220 u32 cs_timestamp_frequency_khz; 221 222 /* Media engine access to SFC per instance */ 223 u8 vdbox_sfc_access; 224 }; 225 226 struct intel_driver_caps { 227 unsigned int scheduler; 228 bool has_logical_contexts:1; 229 }; 230 231 const char *intel_platform_name(enum intel_platform platform); 232 233 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv); 234 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); 235 236 void intel_device_info_print_static(const struct intel_device_info *info, 237 struct drm_printer *p); 238 void intel_device_info_print_runtime(const struct intel_runtime_info *info, 239 struct drm_printer *p); 240 void intel_device_info_print_topology(const struct sseu_dev_info *sseu, 241 struct drm_printer *p); 242 243 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv); 244 245 void intel_driver_caps_print(const struct intel_driver_caps *caps, 246 struct drm_printer *p); 247 248 #endif 249