1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 17 18 #include "MCTargetDesc/MipsABIInfo.h" 19 #include "MCTargetDesc/MipsBaseInfo.h" 20 #include "Mips.h" 21 #include "llvm/CodeGen/CallingConvLower.h" 22 #include "llvm/CodeGen/SelectionDAG.h" 23 #include "llvm/IR/Function.h" 24 #include "llvm/Target/TargetLowering.h" 25 #include <deque> 26 #include <string> 27 28 namespace llvm { 29 namespace MipsISD { 30 enum NodeType : unsigned { 31 // Start the numbering from where ISD NodeType finishes. 32 FIRST_NUMBER = ISD::BUILTIN_OP_END, 33 34 // Jump and link (call) 35 JmpLink, 36 37 // Tail call 38 TailCall, 39 40 // Get the Higher 16 bits from a 32-bit immediate 41 // No relation with Mips Hi register 42 Hi, 43 44 // Get the Lower 16 bits from a 32-bit immediate 45 // No relation with Mips Lo register 46 Lo, 47 48 // Handle gp_rel (small data/bss sections) relocation. 49 GPRel, 50 51 // Thread Pointer 52 ThreadPointer, 53 54 // Floating Point Branch Conditional 55 FPBrcond, 56 57 // Floating Point Compare 58 FPCmp, 59 60 // Floating Point Conditional Moves 61 CMovFP_T, 62 CMovFP_F, 63 64 // FP-to-int truncation node. 65 TruncIntFP, 66 67 // Return 68 Ret, 69 70 EH_RETURN, 71 72 // Node used to extract integer from accumulator. 73 MFHI, 74 MFLO, 75 76 // Node used to insert integers to accumulator. 77 MTLOHI, 78 79 // Mult nodes. 80 Mult, 81 Multu, 82 83 // MAdd/Sub nodes 84 MAdd, 85 MAddu, 86 MSub, 87 MSubu, 88 89 // DivRem(u) 90 DivRem, 91 DivRemU, 92 DivRem16, 93 DivRemU16, 94 95 BuildPairF64, 96 ExtractElementF64, 97 98 Wrapper, 99 100 DynAlloc, 101 102 Sync, 103 104 Ext, 105 Ins, 106 107 // EXTR.W instrinsic nodes. 108 EXTP, 109 EXTPDP, 110 EXTR_S_H, 111 EXTR_W, 112 EXTR_R_W, 113 EXTR_RS_W, 114 SHILO, 115 MTHLIP, 116 117 // DPA.W intrinsic nodes. 118 MULSAQ_S_W_PH, 119 MAQ_S_W_PHL, 120 MAQ_S_W_PHR, 121 MAQ_SA_W_PHL, 122 MAQ_SA_W_PHR, 123 DPAU_H_QBL, 124 DPAU_H_QBR, 125 DPSU_H_QBL, 126 DPSU_H_QBR, 127 DPAQ_S_W_PH, 128 DPSQ_S_W_PH, 129 DPAQ_SA_L_W, 130 DPSQ_SA_L_W, 131 DPA_W_PH, 132 DPS_W_PH, 133 DPAQX_S_W_PH, 134 DPAQX_SA_W_PH, 135 DPAX_W_PH, 136 DPSX_W_PH, 137 DPSQX_S_W_PH, 138 DPSQX_SA_W_PH, 139 MULSA_W_PH, 140 141 MULT, 142 MULTU, 143 MADD_DSP, 144 MADDU_DSP, 145 MSUB_DSP, 146 MSUBU_DSP, 147 148 // DSP shift nodes. 149 SHLL_DSP, 150 SHRA_DSP, 151 SHRL_DSP, 152 153 // DSP setcc and select_cc nodes. 154 SETCC_DSP, 155 SELECT_CC_DSP, 156 157 // Vector comparisons. 158 // These take a vector and return a boolean. 159 VALL_ZERO, 160 VANY_ZERO, 161 VALL_NONZERO, 162 VANY_NONZERO, 163 164 // These take a vector and return a vector bitmask. 165 VCEQ, 166 VCLE_S, 167 VCLE_U, 168 VCLT_S, 169 VCLT_U, 170 171 // Element-wise vector max/min. 172 VSMAX, 173 VSMIN, 174 VUMAX, 175 VUMIN, 176 177 // Vector Shuffle with mask as an operand 178 VSHF, // Generic shuffle 179 SHF, // 4-element set shuffle. 180 ILVEV, // Interleave even elements 181 ILVOD, // Interleave odd elements 182 ILVL, // Interleave left elements 183 ILVR, // Interleave right elements 184 PCKEV, // Pack even elements 185 PCKOD, // Pack odd elements 186 187 // Vector Lane Copy 188 INSVE, // Copy element from one vector to another 189 190 // Combined (XOR (OR $a, $b), -1) 191 VNOR, 192 193 // Extended vector element extraction 194 VEXTRACT_SEXT_ELT, 195 VEXTRACT_ZEXT_ELT, 196 197 // Load/Store Left/Right nodes. 198 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 199 LWR, 200 SWL, 201 SWR, 202 LDL, 203 LDR, 204 SDL, 205 SDR 206 }; 207 } 208 209 //===--------------------------------------------------------------------===// 210 // TargetLowering Implementation 211 //===--------------------------------------------------------------------===// 212 class MipsFunctionInfo; 213 class MipsSubtarget; 214 class MipsCCState; 215 216 class MipsTargetLowering : public TargetLowering { 217 bool isMicroMips; 218 public: 219 explicit MipsTargetLowering(const MipsTargetMachine &TM, 220 const MipsSubtarget &STI); 221 222 static const MipsTargetLowering *create(const MipsTargetMachine &TM, 223 const MipsSubtarget &STI); 224 225 /// createFastISel - This method returns a target specific FastISel object, 226 /// or null if the target does not support "fast" ISel. 227 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 228 const TargetLibraryInfo *libInfo) const override; 229 getScalarShiftAmountTy(const DataLayout &,EVT)230 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 231 return MVT::i32; 232 } 233 234 void LowerOperationWrapper(SDNode *N, 235 SmallVectorImpl<SDValue> &Results, 236 SelectionDAG &DAG) const override; 237 238 /// LowerOperation - Provide custom lowering hooks for some operations. 239 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 240 241 /// ReplaceNodeResults - Replace the results of node with an illegal result 242 /// type with new values built out of custom code. 243 /// 244 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 245 SelectionDAG &DAG) const override; 246 247 /// getTargetNodeName - This method returns the name of a target specific 248 // DAG node. 249 const char *getTargetNodeName(unsigned Opcode) const override; 250 251 /// getSetCCResultType - get the ISD::SETCC result ValueType 252 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 253 EVT VT) const override; 254 255 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 256 257 MachineBasicBlock * 258 EmitInstrWithCustomInserter(MachineInstr *MI, 259 MachineBasicBlock *MBB) const override; 260 261 struct LTStr { operatorLTStr262 bool operator()(const char *S1, const char *S2) const { 263 return strcmp(S1, S2) < 0; 264 } 265 }; 266 267 void HandleByVal(CCState *, unsigned &, unsigned) const override; 268 269 unsigned getRegisterByName(const char* RegName, EVT VT, 270 SelectionDAG &DAG) const override; 271 272 /// Returns true if a cast between SrcAS and DestAS is a noop. isNoopAddrSpaceCast(unsigned SrcAS,unsigned DestAS)273 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 274 // Mips doesn't have any special address spaces so we just reserve 275 // the first 256 for software use (e.g. OpenCL) and treat casts 276 // between them as noops. 277 return SrcAS < 256 && DestAS < 256; 278 } 279 280 protected: 281 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; 282 283 // This method creates the following nodes, which are necessary for 284 // computing a local symbol's address: 285 // 286 // (add (load (wrapper $gp, %got(sym)), %lo(sym)) 287 template <class NodeTy> getAddrLocal(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,bool IsN32OrN64)288 SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, 289 bool IsN32OrN64) const { 290 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 291 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 292 getTargetNode(N, Ty, DAG, GOTFlag)); 293 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 294 MachinePointerInfo::getGOT(), false, false, 295 false, 0); 296 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 297 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, 298 getTargetNode(N, Ty, DAG, LoFlag)); 299 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 300 } 301 302 // This method creates the following nodes, which are necessary for 303 // computing a global symbol's address: 304 // 305 // (load (wrapper $gp, %got(sym))) 306 template <class NodeTy> getAddrGlobal(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned Flag,SDValue Chain,const MachinePointerInfo & PtrInfo)307 SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, 308 unsigned Flag, SDValue Chain, 309 const MachinePointerInfo &PtrInfo) const { 310 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 311 getTargetNode(N, Ty, DAG, Flag)); 312 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0); 313 } 314 315 // This method creates the following nodes, which are necessary for 316 // computing a global symbol's address in large-GOT mode: 317 // 318 // (load (wrapper (add %hi(sym), $gp), %lo(sym))) 319 template <class NodeTy> getAddrGlobalLargeGOT(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned HiFlag,unsigned LoFlag,SDValue Chain,const MachinePointerInfo & PtrInfo)320 SDValue getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty, 321 SelectionDAG &DAG, unsigned HiFlag, 322 unsigned LoFlag, SDValue Chain, 323 const MachinePointerInfo &PtrInfo) const { 324 SDValue Hi = 325 DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag)); 326 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty)); 327 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 328 getTargetNode(N, Ty, DAG, LoFlag)); 329 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false, 330 0); 331 } 332 333 // This method creates the following nodes, which are necessary for 334 // computing a symbol's address in non-PIC mode: 335 // 336 // (add %hi(sym), %lo(sym)) 337 template <class NodeTy> getAddrNonPIC(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG)338 SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty, 339 SelectionDAG &DAG) const { 340 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI); 341 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO); 342 return DAG.getNode(ISD::ADD, DL, Ty, 343 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 344 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 345 } 346 347 // This method creates the following nodes, which are necessary for 348 // computing a symbol's address using gp-relative addressing: 349 // 350 // (add $gp, %gp_rel(sym)) 351 template <class NodeTy> getAddrGPRel(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG)352 SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const { 353 assert(Ty == MVT::i32); 354 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL); 355 return DAG.getNode(ISD::ADD, DL, Ty, 356 DAG.getRegister(Mips::GP, Ty), 357 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), 358 GPRel)); 359 } 360 361 /// This function fills Ops, which is the list of operands that will later 362 /// be used when a function call node is created. It also generates 363 /// copyToReg nodes to set up argument registers. 364 virtual void 365 getOpndList(SmallVectorImpl<SDValue> &Ops, 366 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 367 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 368 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 369 SDValue Chain) const; 370 371 protected: 372 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 373 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 374 375 // Subtarget Info 376 const MipsSubtarget &Subtarget; 377 // Cache the ABI from the TargetMachine, we use it everywhere. 378 const MipsABIInfo &ABI; 379 380 private: 381 // Create a TargetGlobalAddress node. 382 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 383 unsigned Flag) const; 384 385 // Create a TargetExternalSymbol node. 386 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, 387 unsigned Flag) const; 388 389 // Create a TargetBlockAddress node. 390 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 391 unsigned Flag) const; 392 393 // Create a TargetJumpTable node. 394 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, 395 unsigned Flag) const; 396 397 // Create a TargetConstantPool node. 398 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, 399 unsigned Flag) const; 400 401 // Lower Operand helpers 402 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 403 CallingConv::ID CallConv, bool isVarArg, 404 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, 405 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 406 TargetLowering::CallLoweringInfo &CLI) const; 407 408 // Lower Operand specifics 409 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 410 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 411 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 412 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 413 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 414 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 415 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 416 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 417 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 418 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 419 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 420 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const; 421 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 422 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; 423 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 424 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 425 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 426 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 427 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 428 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 429 bool IsSRA) const; 430 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const; 431 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 432 433 /// isEligibleForTailCallOptimization - Check whether the call is eligible 434 /// for tail call optimization. 435 virtual bool 436 isEligibleForTailCallOptimization(const CCState &CCInfo, 437 unsigned NextStackOffset, 438 const MipsFunctionInfo &FI) const = 0; 439 440 /// copyByValArg - Copy argument registers which were used to pass a byval 441 /// argument to the stack. Create a stack frame object for the byval 442 /// argument. 443 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, 444 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 445 SmallVectorImpl<SDValue> &InVals, 446 const Argument *FuncArg, unsigned FirstReg, 447 unsigned LastReg, const CCValAssign &VA, 448 MipsCCState &State) const; 449 450 /// passByValArg - Pass a byval argument in registers or on stack. 451 void passByValArg(SDValue Chain, SDLoc DL, 452 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 453 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 454 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 455 unsigned FirstReg, unsigned LastReg, 456 const ISD::ArgFlagsTy &Flags, bool isLittle, 457 const CCValAssign &VA) const; 458 459 /// writeVarArgRegs - Write variable function arguments passed in registers 460 /// to the stack. Also create a stack frame object for the first variable 461 /// argument. 462 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain, 463 SDLoc DL, SelectionDAG &DAG, CCState &State) const; 464 465 SDValue 466 LowerFormalArguments(SDValue Chain, 467 CallingConv::ID CallConv, bool isVarArg, 468 const SmallVectorImpl<ISD::InputArg> &Ins, 469 SDLoc dl, SelectionDAG &DAG, 470 SmallVectorImpl<SDValue> &InVals) const override; 471 472 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 473 SDValue Arg, SDLoc DL, bool IsTailCall, 474 SelectionDAG &DAG) const; 475 476 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 477 SmallVectorImpl<SDValue> &InVals) const override; 478 479 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 480 bool isVarArg, 481 const SmallVectorImpl<ISD::OutputArg> &Outs, 482 LLVMContext &Context) const override; 483 484 SDValue LowerReturn(SDValue Chain, 485 CallingConv::ID CallConv, bool isVarArg, 486 const SmallVectorImpl<ISD::OutputArg> &Outs, 487 const SmallVectorImpl<SDValue> &OutVals, 488 SDLoc dl, SelectionDAG &DAG) const override; 489 490 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; 491 492 // Inline asm support 493 ConstraintType getConstraintType(StringRef Constraint) const override; 494 495 /// Examine constraint string and operand type and determine a weight value. 496 /// The operand object must already have been set up with the operand type. 497 ConstraintWeight getSingleConstraintMatchWeight( 498 AsmOperandInfo &info, const char *constraint) const override; 499 500 /// This function parses registers that appear in inline-asm constraints. 501 /// It returns pair (0, 0) on failure. 502 std::pair<unsigned, const TargetRegisterClass *> 503 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const; 504 505 std::pair<unsigned, const TargetRegisterClass *> 506 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 507 StringRef Constraint, MVT VT) const override; 508 509 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 510 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 511 /// true it means one of the asm constraint of the inline asm instruction 512 /// being processed is 'm'. 513 void LowerAsmOperandForConstraint(SDValue Op, 514 std::string &Constraint, 515 std::vector<SDValue> &Ops, 516 SelectionDAG &DAG) const override; 517 518 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode)519 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 520 if (ConstraintCode == "R") 521 return InlineAsm::Constraint_R; 522 else if (ConstraintCode == "ZC") 523 return InlineAsm::Constraint_ZC; 524 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 525 } 526 527 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 528 Type *Ty, unsigned AS) const override; 529 530 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 531 532 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 533 unsigned SrcAlign, 534 bool IsMemset, bool ZeroMemset, 535 bool MemcpyStrSrc, 536 MachineFunction &MF) const override; 537 538 /// isFPImmLegal - Returns true if the target can instruction select the 539 /// specified FP immediate natively. If false, the legalizer will 540 /// materialize the FP immediate as a load from a constant pool. 541 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 542 543 unsigned getJumpTableEncoding() const override; 544 bool useSoftFloat() const override; 545 546 /// Emit a sign-extension using sll/sra, seb, or seh appropriately. 547 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI, 548 MachineBasicBlock *BB, 549 unsigned Size, unsigned DstReg, 550 unsigned SrcRec) const; 551 552 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 553 unsigned Size, unsigned BinOpcode, bool Nand = false) const; 554 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI, 555 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 556 bool Nand = false) const; 557 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI, 558 MachineBasicBlock *BB, unsigned Size) const; 559 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI, 560 MachineBasicBlock *BB, unsigned Size) const; 561 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const; 562 MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI, 563 MachineBasicBlock *BB, bool isFPCmp, 564 unsigned Opc) const; 565 }; 566 567 /// Create MipsTargetLowering objects. 568 const MipsTargetLowering * 569 createMips16TargetLowering(const MipsTargetMachine &TM, 570 const MipsSubtarget &STI); 571 const MipsTargetLowering * 572 createMipsSETargetLowering(const MipsTargetMachine &TM, 573 const MipsSubtarget &STI); 574 575 namespace Mips { 576 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 577 const TargetLibraryInfo *libInfo); 578 } 579 } 580 581 #endif 582