1 /*- 2 * Copyright (c) 2018 Johannes Lundberg 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #ifndef _PCI_EARLY_QUIRKS_H_ 27 #define _PCI_EARLY_QUIRKS_H_ 28 29 /* 30 * TODO: 31 * Make a common drm/gpu header that both base and out of tree 32 * drm modules can use. 33 */ 34 35 #define PCI_ANY_ID (-1) 36 #define PCI_VENDOR_INTEL 0x8086 37 #define PCI_CLASS_VGA 0x0300 38 39 #define INTEL_BSM 0x5c 40 #define INTEL_BSM_MASK (-(1u << 20)) 41 42 #define INTEL_GMCH_CTRL 0x52 43 #define INTEL_GMCH_VGA_DISABLE (1 << 1) 44 #define SNB_GMCH_CTRL 0x50 45 #define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */ 46 #define SNB_GMCH_GGMS_MASK 0x3 47 #define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */ 48 #define SNB_GMCH_GMS_MASK 0x1f 49 #define BDW_GMCH_GGMS_SHIFT 6 50 #define BDW_GMCH_GGMS_MASK 0x3 51 #define BDW_GMCH_GMS_SHIFT 8 52 #define BDW_GMCH_GMS_MASK 0xff 53 54 #define I830_GMCH_CTRL 0x52 55 #define I830_GMCH_GMS_MASK 0x70 56 #define I830_GMCH_GMS_LOCAL 0x10 57 #define I830_GMCH_GMS_STOLEN_512 0x20 58 #define I830_GMCH_GMS_STOLEN_1024 0x30 59 #define I830_GMCH_GMS_STOLEN_8192 0x40 60 61 #define I855_GMCH_GMS_MASK 0xF0 62 #define I855_GMCH_GMS_STOLEN_0M 0x0 63 #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) 64 #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) 65 #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) 66 #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) 67 #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) 68 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 69 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 70 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 71 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 72 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 73 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 74 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 75 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 76 77 #define INTEL_VGA_DEVICE(id, info) { \ 78 0x8086, id, \ 79 info } 80 81 #define INTEL_I810_IDS(info) \ 82 INTEL_VGA_DEVICE(0x7121, info), /* I810 */ \ 83 INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */ \ 84 INTEL_VGA_DEVICE(0x7125, info) /* I810_E */ 85 86 #define INTEL_I815_IDS(info) \ 87 INTEL_VGA_DEVICE(0x1132, info) /* I815*/ 88 89 #define INTEL_I830_IDS(info) \ 90 INTEL_VGA_DEVICE(0x3577, info) 91 92 #define INTEL_I845G_IDS(info) \ 93 INTEL_VGA_DEVICE(0x2562, info) 94 95 #define INTEL_I85X_IDS(info) \ 96 INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \ 97 INTEL_VGA_DEVICE(0x358e, info) 98 99 #define INTEL_I865G_IDS(info) \ 100 INTEL_VGA_DEVICE(0x2572, info) /* I865_G */ 101 102 #define INTEL_I915G_IDS(info) \ 103 INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \ 104 INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */ 105 106 #define INTEL_I915GM_IDS(info) \ 107 INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */ 108 109 #define INTEL_I945G_IDS(info) \ 110 INTEL_VGA_DEVICE(0x2772, info) /* I945_G */ 111 112 #define INTEL_I945GM_IDS(info) \ 113 INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \ 114 INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */ 115 116 #define INTEL_I965G_IDS(info) \ 117 INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \ 118 INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \ 119 INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \ 120 INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */ 121 122 #define INTEL_G33_IDS(info) \ 123 INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \ 124 INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \ 125 INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */ 126 127 #define INTEL_I965GM_IDS(info) \ 128 INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \ 129 INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */ 130 131 #define INTEL_GM45_IDS(info) \ 132 INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */ 133 134 #define INTEL_G45_IDS(info) \ 135 INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \ 136 INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \ 137 INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \ 138 INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \ 139 INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \ 140 INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */ 141 142 #define INTEL_PINEVIEW_IDS(info) \ 143 INTEL_VGA_DEVICE(0xa001, info), \ 144 INTEL_VGA_DEVICE(0xa011, info) 145 146 #define INTEL_IRONLAKE_D_IDS(info) \ 147 INTEL_VGA_DEVICE(0x0042, info) 148 149 #define INTEL_IRONLAKE_M_IDS(info) \ 150 INTEL_VGA_DEVICE(0x0046, info) 151 152 #define INTEL_SNB_D_GT1_IDS(info) \ 153 INTEL_VGA_DEVICE(0x0102, info), \ 154 INTEL_VGA_DEVICE(0x010A, info) 155 156 #define INTEL_SNB_D_GT2_IDS(info) \ 157 INTEL_VGA_DEVICE(0x0112, info), \ 158 INTEL_VGA_DEVICE(0x0122, info) 159 160 #define INTEL_SNB_D_IDS(info) \ 161 INTEL_SNB_D_GT1_IDS(info), \ 162 INTEL_SNB_D_GT2_IDS(info) 163 164 #define INTEL_SNB_M_GT1_IDS(info) \ 165 INTEL_VGA_DEVICE(0x0106, info) 166 167 #define INTEL_SNB_M_GT2_IDS(info) \ 168 INTEL_VGA_DEVICE(0x0116, info), \ 169 INTEL_VGA_DEVICE(0x0126, info) 170 171 #define INTEL_SNB_M_IDS(info) \ 172 INTEL_SNB_M_GT1_IDS(info), \ 173 INTEL_SNB_M_GT2_IDS(info) 174 175 #define INTEL_IVB_M_GT1_IDS(info) \ 176 INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */ 177 178 #define INTEL_IVB_M_GT2_IDS(info) \ 179 INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ 180 181 #define INTEL_IVB_M_IDS(info) \ 182 INTEL_IVB_M_GT1_IDS(info), \ 183 INTEL_IVB_M_GT2_IDS(info) 184 185 #define INTEL_IVB_D_GT1_IDS(info) \ 186 INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \ 187 INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */ 188 189 #define INTEL_IVB_D_GT2_IDS(info) \ 190 INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \ 191 INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */ 192 193 #define INTEL_IVB_D_IDS(info) \ 194 INTEL_IVB_D_GT1_IDS(info), \ 195 INTEL_IVB_D_GT2_IDS(info) 196 197 #define INTEL_IVB_Q_IDS(info) \ 198 INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */ 199 200 #define INTEL_HSW_GT1_IDS(info) \ 201 INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ 202 INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ 203 INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ 204 INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ 205 INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ 206 INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ 207 INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ 208 INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ 209 INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ 210 INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ 211 INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ 212 INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ 213 INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ 214 INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ 215 INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ 216 INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ 217 INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ 218 INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ 219 INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ 220 INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */ 221 222 #define INTEL_HSW_GT2_IDS(info) \ 223 INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ 224 INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ 225 INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ 226 INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ 227 INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ 228 INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ 229 INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ 230 INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ 231 INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ 232 INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ 233 INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ 234 INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ 235 INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ 236 INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ 237 INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ 238 INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ 239 INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ 240 INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ 241 INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ 242 INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ 243 INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */ 244 245 #define INTEL_HSW_GT3_IDS(info) \ 246 INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ 247 INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ 248 INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ 249 INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ 250 INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ 251 INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ 252 INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ 253 INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ 254 INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ 255 INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ 256 INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ 257 INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ 258 INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ 259 INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ 260 INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \ 261 INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ 262 INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ 263 INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ 264 INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ 265 266 #define INTEL_HSW_IDS(info) \ 267 INTEL_HSW_GT1_IDS(info), \ 268 INTEL_HSW_GT2_IDS(info), \ 269 INTEL_HSW_GT3_IDS(info) 270 271 #define INTEL_VLV_IDS(info) \ 272 INTEL_VGA_DEVICE(0x0f30, info), \ 273 INTEL_VGA_DEVICE(0x0f31, info), \ 274 INTEL_VGA_DEVICE(0x0f32, info), \ 275 INTEL_VGA_DEVICE(0x0f33, info), \ 276 INTEL_VGA_DEVICE(0x0157, info), \ 277 INTEL_VGA_DEVICE(0x0155, info) 278 279 #define INTEL_BDW_GT1_IDS(info) \ 280 INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ 281 INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ 282 INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ 283 INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \ 284 INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ 285 INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */ 286 287 #define INTEL_BDW_GT2_IDS(info) \ 288 INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ 289 INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \ 290 INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \ 291 INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \ 292 INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \ 293 INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */ 294 295 #define INTEL_BDW_GT3_IDS(info) \ 296 INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \ 297 INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \ 298 INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \ 299 INTEL_VGA_DEVICE(0x162E, info), /* ULX */\ 300 INTEL_VGA_DEVICE(0x162A, info), /* Server */ \ 301 INTEL_VGA_DEVICE(0x162D, info) /* Workstation */ 302 303 #define INTEL_BDW_RSVD_IDS(info) \ 304 INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \ 305 INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \ 306 INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \ 307 INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \ 308 INTEL_VGA_DEVICE(0x163A, info), /* Server */ \ 309 INTEL_VGA_DEVICE(0x163D, info) /* Workstation */ 310 311 #define INTEL_BDW_IDS(info) \ 312 INTEL_BDW_GT1_IDS(info), \ 313 INTEL_BDW_GT2_IDS(info), \ 314 INTEL_BDW_GT3_IDS(info), \ 315 INTEL_BDW_RSVD_IDS(info) 316 317 #define INTEL_CHV_IDS(info) \ 318 INTEL_VGA_DEVICE(0x22b0, info), \ 319 INTEL_VGA_DEVICE(0x22b1, info), \ 320 INTEL_VGA_DEVICE(0x22b2, info), \ 321 INTEL_VGA_DEVICE(0x22b3, info) 322 323 #define INTEL_SKL_GT1_IDS(info) \ 324 INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ 325 INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ 326 INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ 327 INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ 328 INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */ 329 330 #define INTEL_SKL_GT2_IDS(info) \ 331 INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \ 332 INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \ 333 INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \ 334 INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \ 335 INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \ 336 INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \ 337 INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */ 338 339 #define INTEL_SKL_GT3_IDS(info) \ 340 INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ 341 INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \ 342 INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \ 343 INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \ 344 INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */ 345 346 #define INTEL_SKL_GT4_IDS(info) \ 347 INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \ 348 INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \ 349 INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \ 350 INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \ 351 INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */ 352 353 #define INTEL_SKL_IDS(info) \ 354 INTEL_SKL_GT1_IDS(info), \ 355 INTEL_SKL_GT2_IDS(info), \ 356 INTEL_SKL_GT3_IDS(info), \ 357 INTEL_SKL_GT4_IDS(info) 358 359 #define INTEL_BXT_IDS(info) \ 360 INTEL_VGA_DEVICE(0x0A84, info), \ 361 INTEL_VGA_DEVICE(0x1A84, info), \ 362 INTEL_VGA_DEVICE(0x1A85, info), \ 363 INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \ 364 INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */ 365 366 #define INTEL_GLK_IDS(info) \ 367 INTEL_VGA_DEVICE(0x3184, info), \ 368 INTEL_VGA_DEVICE(0x3185, info) 369 370 #define INTEL_KBL_GT1_IDS(info) \ 371 INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \ 372 INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \ 373 INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \ 374 INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \ 375 INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ 376 INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \ 377 INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \ 378 INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */ 379 380 #define INTEL_KBL_GT2_IDS(info) \ 381 INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ 382 INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ 383 INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \ 384 INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \ 385 INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ 386 INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \ 387 INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \ 388 INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */ 389 390 #define INTEL_KBL_GT3_IDS(info) \ 391 INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \ 392 INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \ 393 INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */ 394 395 #define INTEL_KBL_GT4_IDS(info) \ 396 INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */ 397 398 #define INTEL_KBL_IDS(info) \ 399 INTEL_KBL_GT1_IDS(info), \ 400 INTEL_KBL_GT2_IDS(info), \ 401 INTEL_KBL_GT3_IDS(info), \ 402 INTEL_KBL_GT4_IDS(info) 403 404 /* CFL S */ 405 #define INTEL_CFL_S_GT1_IDS(info) \ 406 INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \ 407 INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \ 408 INTEL_VGA_DEVICE(0x3E99, info) /* SRV GT1 */ 409 410 #define INTEL_CFL_S_GT2_IDS(info) \ 411 INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \ 412 INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \ 413 INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \ 414 INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \ 415 INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */ 416 417 /* CFL H */ 418 #define INTEL_CFL_H_GT2_IDS(info) \ 419 INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ 420 INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ 421 422 /* CFL U GT1 */ 423 #define INTEL_CFL_U_GT1_IDS(info) \ 424 INTEL_VGA_DEVICE(0x3EA1, info), \ 425 INTEL_VGA_DEVICE(0x3EA4, info) 426 427 /* CFL U GT2 */ 428 #define INTEL_CFL_U_GT2_IDS(info) \ 429 INTEL_VGA_DEVICE(0x3EA0, info), \ 430 INTEL_VGA_DEVICE(0x3EA3, info), \ 431 INTEL_VGA_DEVICE(0x3EA9, info) 432 433 /* CFL U GT3 */ 434 #define INTEL_CFL_U_GT3_IDS(info) \ 435 INTEL_VGA_DEVICE(0x3EA2, info), /* ULT GT3 */ \ 436 INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \ 437 INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \ 438 INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \ 439 INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */ 440 441 #define INTEL_CFL_IDS(info) \ 442 INTEL_CFL_S_GT1_IDS(info), \ 443 INTEL_CFL_S_GT2_IDS(info), \ 444 INTEL_CFL_H_GT2_IDS(info), \ 445 INTEL_CFL_U_GT1_IDS(info), \ 446 INTEL_CFL_U_GT2_IDS(info), \ 447 INTEL_CFL_U_GT3_IDS(info) 448 449 /* CNL */ 450 #define INTEL_CNL_IDS(info) \ 451 INTEL_VGA_DEVICE(0x5A51, info), \ 452 INTEL_VGA_DEVICE(0x5A59, info), \ 453 INTEL_VGA_DEVICE(0x5A41, info), \ 454 INTEL_VGA_DEVICE(0x5A49, info), \ 455 INTEL_VGA_DEVICE(0x5A52, info), \ 456 INTEL_VGA_DEVICE(0x5A5A, info), \ 457 INTEL_VGA_DEVICE(0x5A42, info), \ 458 INTEL_VGA_DEVICE(0x5A4A, info), \ 459 INTEL_VGA_DEVICE(0x5A50, info), \ 460 INTEL_VGA_DEVICE(0x5A40, info), \ 461 INTEL_VGA_DEVICE(0x5A54, info), \ 462 INTEL_VGA_DEVICE(0x5A5C, info), \ 463 INTEL_VGA_DEVICE(0x5A44, info), \ 464 INTEL_VGA_DEVICE(0x5A4C, info) 465 466 /* ICL */ 467 #define INTEL_ICL_11_IDS(info) \ 468 INTEL_VGA_DEVICE(0x8A50, info), \ 469 INTEL_VGA_DEVICE(0x8A51, info), \ 470 INTEL_VGA_DEVICE(0x8A5C, info), \ 471 INTEL_VGA_DEVICE(0x8A5D, info), \ 472 INTEL_VGA_DEVICE(0x8A52, info), \ 473 INTEL_VGA_DEVICE(0x8A5A, info), \ 474 INTEL_VGA_DEVICE(0x8A5B, info), \ 475 INTEL_VGA_DEVICE(0x8A71, info), \ 476 INTEL_VGA_DEVICE(0x8A70, info) 477 478 #endif /* _PCI_EARLY_QUIRKS_H_ */ 479