1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the ARM specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 16 17 18 #include "ARMFrameLowering.h" 19 #include "ARMISelLowering.h" 20 #include "ARMInstrInfo.h" 21 #include "ARMSelectionDAGInfo.h" 22 #include "ARMSubtarget.h" 23 #include "MCTargetDesc/ARMMCTargetDesc.h" 24 #include "Thumb1FrameLowering.h" 25 #include "Thumb1InstrInfo.h" 26 #include "Thumb2InstrInfo.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/DataLayout.h" 29 #include "llvm/MC/MCInstrItineraries.h" 30 #include "llvm/Target/TargetSubtargetInfo.h" 31 #include <string> 32 33 #define GET_SUBTARGETINFO_HEADER 34 #include "ARMGenSubtargetInfo.inc" 35 36 namespace llvm { 37 class GlobalValue; 38 class StringRef; 39 class TargetOptions; 40 class ARMBaseTargetMachine; 41 42 class ARMSubtarget : public ARMGenSubtargetInfo { 43 protected: 44 enum ARMProcFamilyEnum { 45 Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15, 46 CortexA17, CortexR4, CortexR4F, CortexR5, Swift, CortexA53, CortexA57, Krait, 47 }; 48 enum ARMProcClassEnum { 49 None, AClass, RClass, MClass 50 }; 51 52 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. 53 ARMProcFamilyEnum ARMProcFamily; 54 55 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass. 56 ARMProcClassEnum ARMProcClass; 57 58 /// HasV4TOps, HasV5TOps, HasV5TEOps, 59 /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - 60 /// Specify whether target support specific ARM ISA variants. 61 bool HasV4TOps; 62 bool HasV5TOps; 63 bool HasV5TEOps; 64 bool HasV6Ops; 65 bool HasV6MOps; 66 bool HasV6KOps; 67 bool HasV6T2Ops; 68 bool HasV7Ops; 69 bool HasV8Ops; 70 bool HasV8_1aOps; 71 72 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what 73 /// floating point ISAs are supported. 74 bool HasVFPv2; 75 bool HasVFPv3; 76 bool HasVFPv4; 77 bool HasFPARMv8; 78 bool HasNEON; 79 80 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been 81 /// specified. Use the method useNEONForSinglePrecisionFP() to 82 /// determine if NEON should actually be used. 83 bool UseNEONForSinglePrecisionFP; 84 85 /// UseMulOps - True if non-microcoded fused integer multiply-add and 86 /// multiply-subtract instructions should be used. 87 bool UseMulOps; 88 89 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates 90 /// whether the FP VML[AS] instructions are slow (if so, don't use them). 91 bool SlowFPVMLx; 92 93 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator 94 /// forwarding to allow mul + mla being issued back to back. 95 bool HasVMLxForwarding; 96 97 /// SlowFPBrcc - True if floating point compare + branch is slow. 98 bool SlowFPBrcc; 99 100 /// InThumbMode - True if compiling for Thumb, false for ARM. 101 bool InThumbMode; 102 103 /// UseSoftFloat - True if we're using software floating point features. 104 bool UseSoftFloat; 105 106 /// HasThumb2 - True if Thumb2 instructions are supported. 107 bool HasThumb2; 108 109 /// NoARM - True if subtarget does not support ARM mode execution. 110 bool NoARM; 111 112 /// IsR9Reserved - True if R9 is a not available as general purpose register. 113 bool IsR9Reserved; 114 115 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit 116 /// imms (including global addresses). 117 bool UseMovt; 118 119 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker 120 /// must be able to synthesize call stubs for interworking between ARM and 121 /// Thumb. 122 bool SupportsTailCall; 123 124 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF 125 /// only so far) 126 bool HasFP16; 127 128 /// HasD16 - True if subtarget is limited to 16 double precision 129 /// FP registers for VFPv3. 130 bool HasD16; 131 132 /// HasHardwareDivide - True if subtarget supports [su]div 133 bool HasHardwareDivide; 134 135 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode 136 bool HasHardwareDivideInARM; 137 138 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack 139 /// instructions. 140 bool HasT2ExtractPack; 141 142 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier 143 /// instructions. 144 bool HasDataBarrier; 145 146 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions 147 /// over 16-bit ones. 148 bool Pref32BitThumb; 149 150 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions 151 /// that partially update CPSR and add false dependency on the previous 152 /// CPSR setting instruction. 153 bool AvoidCPSRPartialUpdate; 154 155 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting 156 /// movs with shifter operand (i.e. asr, lsl, lsr). 157 bool AvoidMOVsShifterOperand; 158 159 /// HasRAS - Some processors perform return stack prediction. CodeGen should 160 /// avoid issue "normal" call instructions to callees which do not return. 161 bool HasRAS; 162 163 /// HasMPExtension - True if the subtarget supports Multiprocessing 164 /// extension (ARMv7 only). 165 bool HasMPExtension; 166 167 /// HasVirtualization - True if the subtarget supports the Virtualization 168 /// extension. 169 bool HasVirtualization; 170 171 /// FPOnlySP - If true, the floating point unit only supports single 172 /// precision. 173 bool FPOnlySP; 174 175 /// If true, the processor supports the Performance Monitor Extensions. These 176 /// include a generic cycle-counter as well as more fine-grained (often 177 /// implementation-specific) events. 178 bool HasPerfMon; 179 180 /// HasTrustZone - if true, processor supports TrustZone security extensions 181 bool HasTrustZone; 182 183 /// HasCrypto - if true, processor supports Cryptography extensions 184 bool HasCrypto; 185 186 /// HasCRC - if true, processor supports CRC instructions 187 bool HasCRC; 188 189 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are 190 /// particularly effective at zeroing a VFP register. 191 bool HasZeroCycleZeroing; 192 193 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory 194 /// accesses for some types. For details, see 195 /// ARMTargetLowering::allowsMisalignedMemoryAccesses(). 196 bool AllowsUnalignedMem; 197 198 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT 199 /// blocks to conform to ARMv8 rule. 200 bool RestrictIT; 201 202 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith 203 /// and such) instructions in Thumb2 code. 204 bool Thumb2DSP; 205 206 /// NaCl TRAP instruction is generated instead of the regular TRAP. 207 bool UseNaClTrap; 208 209 /// Generate calls via indirect call instructions. 210 bool GenLongCalls; 211 212 /// Target machine allowed unsafe FP math (such as use of NEON fp) 213 bool UnsafeFPMath; 214 215 /// stackAlignment - The minimum alignment known to hold of the stack frame on 216 /// entry to the function and which must be maintained by every function. 217 unsigned stackAlignment; 218 219 /// CPUString - String name of used CPU. 220 std::string CPUString; 221 222 /// IsLittle - The target is Little Endian 223 bool IsLittle; 224 225 /// TargetTriple - What processor and OS we're targeting. 226 Triple TargetTriple; 227 228 /// SchedModel - Processor specific instruction costs. 229 MCSchedModel SchedModel; 230 231 /// Selected instruction itineraries (one entry per itinerary class.) 232 InstrItineraryData InstrItins; 233 234 /// Options passed via command line that could influence the target 235 const TargetOptions &Options; 236 237 const ARMBaseTargetMachine &TM; 238 239 public: 240 /// This constructor initializes the data members to match that 241 /// of the specified triple. 242 /// 243 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, 244 const ARMBaseTargetMachine &TM, bool IsLittle); 245 246 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 247 /// that still makes it profitable to inline the call. getMaxInlineSizeThreshold()248 unsigned getMaxInlineSizeThreshold() const { 249 return 64; 250 } 251 /// ParseSubtargetFeatures - Parses features string setting specified 252 /// subtarget options. Definition of function is auto generated by tblgen. 253 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 254 255 /// initializeSubtargetDependencies - Initializes using a CPU and feature string 256 /// so that we can use initializer lists for subtarget initialization. 257 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); 258 getSelectionDAGInfo()259 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override { 260 return &TSInfo; 261 } getInstrInfo()262 const ARMBaseInstrInfo *getInstrInfo() const override { 263 return InstrInfo.get(); 264 } getTargetLowering()265 const ARMTargetLowering *getTargetLowering() const override { 266 return &TLInfo; 267 } getFrameLowering()268 const ARMFrameLowering *getFrameLowering() const override { 269 return FrameLowering.get(); 270 } getRegisterInfo()271 const ARMBaseRegisterInfo *getRegisterInfo() const override { 272 return &InstrInfo->getRegisterInfo(); 273 } 274 275 private: 276 ARMSelectionDAGInfo TSInfo; 277 // Either Thumb1FrameLowering or ARMFrameLowering. 278 std::unique_ptr<ARMFrameLowering> FrameLowering; 279 // Either Thumb1InstrInfo or Thumb2InstrInfo. 280 std::unique_ptr<ARMBaseInstrInfo> InstrInfo; 281 ARMTargetLowering TLInfo; 282 283 void initializeEnvironment(); 284 void initSubtargetFeatures(StringRef CPU, StringRef FS); 285 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS); 286 287 public: 288 void computeIssueWidth(); 289 hasV4TOps()290 bool hasV4TOps() const { return HasV4TOps; } hasV5TOps()291 bool hasV5TOps() const { return HasV5TOps; } hasV5TEOps()292 bool hasV5TEOps() const { return HasV5TEOps; } hasV6Ops()293 bool hasV6Ops() const { return HasV6Ops; } hasV6MOps()294 bool hasV6MOps() const { return HasV6MOps; } hasV6KOps()295 bool hasV6KOps() const { return HasV6KOps; } hasV6T2Ops()296 bool hasV6T2Ops() const { return HasV6T2Ops; } hasV7Ops()297 bool hasV7Ops() const { return HasV7Ops; } hasV8Ops()298 bool hasV8Ops() const { return HasV8Ops; } hasV8_1aOps()299 bool hasV8_1aOps() const { return HasV8_1aOps; } 300 isCortexA5()301 bool isCortexA5() const { return ARMProcFamily == CortexA5; } isCortexA7()302 bool isCortexA7() const { return ARMProcFamily == CortexA7; } isCortexA8()303 bool isCortexA8() const { return ARMProcFamily == CortexA8; } isCortexA9()304 bool isCortexA9() const { return ARMProcFamily == CortexA9; } isCortexA15()305 bool isCortexA15() const { return ARMProcFamily == CortexA15; } isSwift()306 bool isSwift() const { return ARMProcFamily == Swift; } isCortexM3()307 bool isCortexM3() const { return CPUString == "cortex-m3"; } isLikeA9()308 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); } isCortexR5()309 bool isCortexR5() const { return ARMProcFamily == CortexR5; } isKrait()310 bool isKrait() const { return ARMProcFamily == Krait; } 311 hasARMOps()312 bool hasARMOps() const { return !NoARM; } 313 hasVFP2()314 bool hasVFP2() const { return HasVFPv2; } hasVFP3()315 bool hasVFP3() const { return HasVFPv3; } hasVFP4()316 bool hasVFP4() const { return HasVFPv4; } hasFPARMv8()317 bool hasFPARMv8() const { return HasFPARMv8; } hasNEON()318 bool hasNEON() const { return HasNEON; } hasCrypto()319 bool hasCrypto() const { return HasCrypto; } hasCRC()320 bool hasCRC() const { return HasCRC; } hasVirtualization()321 bool hasVirtualization() const { return HasVirtualization; } useNEONForSinglePrecisionFP()322 bool useNEONForSinglePrecisionFP() const { 323 return hasNEON() && UseNEONForSinglePrecisionFP; 324 } 325 hasDivide()326 bool hasDivide() const { return HasHardwareDivide; } hasDivideInARMMode()327 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; } hasT2ExtractPack()328 bool hasT2ExtractPack() const { return HasT2ExtractPack; } hasDataBarrier()329 bool hasDataBarrier() const { return HasDataBarrier; } hasAnyDataBarrier()330 bool hasAnyDataBarrier() const { 331 return HasDataBarrier || (hasV6Ops() && !isThumb()); 332 } useMulOps()333 bool useMulOps() const { return UseMulOps; } useFPVMLx()334 bool useFPVMLx() const { return !SlowFPVMLx; } hasVMLxForwarding()335 bool hasVMLxForwarding() const { return HasVMLxForwarding; } isFPBrccSlow()336 bool isFPBrccSlow() const { return SlowFPBrcc; } isFPOnlySP()337 bool isFPOnlySP() const { return FPOnlySP; } hasPerfMon()338 bool hasPerfMon() const { return HasPerfMon; } hasTrustZone()339 bool hasTrustZone() const { return HasTrustZone; } hasZeroCycleZeroing()340 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; } prefers32BitThumb()341 bool prefers32BitThumb() const { return Pref32BitThumb; } avoidCPSRPartialUpdate()342 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; } avoidMOVsShifterOperand()343 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; } hasRAS()344 bool hasRAS() const { return HasRAS; } hasMPExtension()345 bool hasMPExtension() const { return HasMPExtension; } hasThumb2DSP()346 bool hasThumb2DSP() const { return Thumb2DSP; } useNaClTrap()347 bool useNaClTrap() const { return UseNaClTrap; } genLongCalls()348 bool genLongCalls() const { return GenLongCalls; } 349 hasFP16()350 bool hasFP16() const { return HasFP16; } hasD16()351 bool hasD16() const { return HasD16; } 352 getTargetTriple()353 const Triple &getTargetTriple() const { return TargetTriple; } 354 isTargetDarwin()355 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } isTargetIOS()356 bool isTargetIOS() const { return TargetTriple.isiOS(); } isTargetLinux()357 bool isTargetLinux() const { return TargetTriple.isOSLinux(); } isTargetNaCl()358 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } isTargetNetBSD()359 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); } isTargetWindows()360 bool isTargetWindows() const { return TargetTriple.isOSWindows(); } 361 isTargetCOFF()362 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } isTargetELF()363 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } isTargetMachO()364 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } 365 366 // ARM EABI is the bare-metal EABI described in ARM ABI documents and 367 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI. 368 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI 369 // even for GNUEABI, so we can make a distinction here and still conform to 370 // the EABI on GNU (and Android) mode. This requires change in Clang, too. 371 // FIXME: The Darwin exception is temporary, while we move users to 372 // "*-*-*-macho" triples as quickly as possible. isTargetAEABI()373 bool isTargetAEABI() const { 374 return (TargetTriple.getEnvironment() == Triple::EABI || 375 TargetTriple.getEnvironment() == Triple::EABIHF) && 376 !isTargetDarwin() && !isTargetWindows(); 377 } 378 379 // ARM Targets that support EHABI exception handling standard 380 // Darwin uses SjLj. Other targets might need more checks. isTargetEHABICompatible()381 bool isTargetEHABICompatible() const { 382 return (TargetTriple.getEnvironment() == Triple::EABI || 383 TargetTriple.getEnvironment() == Triple::GNUEABI || 384 TargetTriple.getEnvironment() == Triple::EABIHF || 385 TargetTriple.getEnvironment() == Triple::GNUEABIHF || 386 TargetTriple.getEnvironment() == Triple::Android) && 387 !isTargetDarwin() && !isTargetWindows(); 388 } 389 isTargetHardFloat()390 bool isTargetHardFloat() const { 391 // FIXME: this is invalid for WindowsCE 392 return TargetTriple.getEnvironment() == Triple::GNUEABIHF || 393 TargetTriple.getEnvironment() == Triple::EABIHF || 394 isTargetWindows(); 395 } isTargetAndroid()396 bool isTargetAndroid() const { 397 return TargetTriple.getEnvironment() == Triple::Android; 398 } 399 400 bool isAPCS_ABI() const; 401 bool isAAPCS_ABI() const; 402 useSoftFloat()403 bool useSoftFloat() const { return UseSoftFloat; } isThumb()404 bool isThumb() const { return InThumbMode; } isThumb1Only()405 bool isThumb1Only() const { return InThumbMode && !HasThumb2; } isThumb2()406 bool isThumb2() const { return InThumbMode && HasThumb2; } hasThumb2()407 bool hasThumb2() const { return HasThumb2; } isMClass()408 bool isMClass() const { return ARMProcClass == MClass; } isRClass()409 bool isRClass() const { return ARMProcClass == RClass; } isAClass()410 bool isAClass() const { return ARMProcClass == AClass; } 411 isV6M()412 bool isV6M() const { 413 return isThumb1Only() && isMClass(); 414 } 415 isR9Reserved()416 bool isR9Reserved() const { return IsR9Reserved; } 417 418 bool useMovt(const MachineFunction &MF) const; 419 supportsTailCall()420 bool supportsTailCall() const { return SupportsTailCall; } 421 allowsUnalignedMem()422 bool allowsUnalignedMem() const { return AllowsUnalignedMem; } 423 restrictIT()424 bool restrictIT() const { return RestrictIT; } 425 getCPUString()426 const std::string & getCPUString() const { return CPUString; } 427 isLittle()428 bool isLittle() const { return IsLittle; } 429 430 unsigned getMispredictionPenalty() const; 431 432 /// This function returns true if the target has sincos() routine in its 433 /// compiler runtime or math libraries. 434 bool hasSinCos() const; 435 436 /// True for some subtargets at > -O0. 437 bool enablePostRAScheduler() const override; 438 439 // enableAtomicExpand- True if we need to expand our atomics. 440 bool enableAtomicExpand() const override; 441 442 /// getInstrItins - Return the instruction itineraries based on subtarget 443 /// selection. getInstrItineraryData()444 const InstrItineraryData *getInstrItineraryData() const override { 445 return &InstrItins; 446 } 447 448 /// getStackAlignment - Returns the minimum alignment known to hold of the 449 /// stack frame on entry to the function and which must be maintained by every 450 /// function for this subtarget. getStackAlignment()451 unsigned getStackAlignment() const { return stackAlignment; } 452 453 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect 454 /// symbol. 455 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const; 456 457 /// True if fast-isel is used. 458 bool useFastISel() const; 459 }; 460 } // End llvm namespace 461 462 #endif // ARMSUBTARGET_H 463