1 /* ISDN4BSD code */ 2 /* 3 * Copyright (c) 1996, 1998 Gary Jennejohn. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 4. Altered versions must be plainly marked as such, and must not be 18 * misrepresented as being the original software and/or documentation. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 *--------------------------------------------------------------------------- 33 * 34 * $Id: hscx.h,v 1.1 2003/04/06 04:37:26 tg Stab $ 35 * 36 * last edit-date: [Sun Feb 14 10:26:56 1999] 37 * 38 * -hm added AVM config register defs 39 * -hm split up for rewrite of Siemens chipset driver 40 * 41 *--------------------------------------------------------------------------- 42 */ 43 44 #ifndef I4B_HSCX_H_ 45 #define I4B_HSCX_H_ 46 47 enum HSCX_VERSIONS { 48 HSCX_VA1, /* 82525 A1 */ 49 HSCX_UNKN1, /* unknown 1 */ 50 HSCX_VA2, /* 82525 A2 */ 51 HSCX_UNKN3, /* unknown 3 */ 52 HSCX_VA3, /* 82525 A3 */ 53 HSCX_V21, /* 82525 2.1 */ 54 HSCX_UNKN /* unknown version */ 55 }; 56 57 #define HSCX_CH_A 0 /* channel A */ 58 #define HSCX_CH_B 1 /* channel B */ 59 60 #define HSCX_FIFO_LEN 32 /* 32 bytes FIFO on chip */ 61 62 /* 63 * definitions of registers and bits for the HSCX ISDN chip. 64 */ 65 66 typedef struct hscx_reg { 67 68 /* 32 byte deep FIFO always first */ 69 70 unsigned char hscx_fifo [HSCX_FIFO_LEN]; 71 72 /* most registers can be read/written, but have different names */ 73 /* so define a union with read/write names to make that clear */ 74 75 union { 76 struct { 77 unsigned char hscx_ista; 78 unsigned char hscx_star; 79 unsigned char hscx_mode; 80 unsigned char hscx_timr; 81 unsigned char hscx_exir; 82 unsigned char hscx_rbcl; 83 unsigned char dummy_26; 84 unsigned char hscx_rsta; 85 unsigned char hscx_ral1; 86 unsigned char hscx_rhcr; 87 unsigned char dummy_2a; 88 unsigned char dummy_2b; 89 unsigned char hscx_ccr2; 90 unsigned char hscx_rbch; 91 unsigned char hscx_vstr; 92 unsigned char hscx_ccr; 93 unsigned char dummy_30; 94 unsigned char dummy_31; 95 unsigned char dummy_32; 96 unsigned char dummy_33; 97 } hscx_r; 98 struct { 99 unsigned char hscx_mask; 100 unsigned char hscx_cmdr; 101 unsigned char hscx_mode; 102 unsigned char hscx_timr; 103 unsigned char hscx_xad1; 104 unsigned char hscx_xad2; 105 unsigned char hscx_rah1; 106 unsigned char hscx_rah2; 107 unsigned char hscx_ral1; 108 unsigned char hscx_ral2; 109 unsigned char hscx_xbcl; 110 unsigned char hscx_bgr; 111 unsigned char hscx_ccr2; 112 unsigned char hscx_xbch; 113 unsigned char hscx_rlcr; 114 unsigned char hscx_ccr1; 115 unsigned char hscx_tsax; 116 unsigned char hscx_tsar; 117 unsigned char hscx_xccr; 118 unsigned char hscx_rccr; 119 } hscx_w; 120 } hscx_rw; 121 } hscx_reg_t; 122 123 #define REG_OFFSET(type, field) (int)(&(((type *)0)->field)) 124 125 /* HSCX read registers */ 126 127 #define h_ista hscx_rw.hscx_r.hscx_ista 128 #define H_ISTA REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ista) 129 #define h_star hscx_rw.hscx_r.hscx_star 130 #define H_STAR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_star) 131 #define h_mode hscx_rw.hscx_r.hscx_mode 132 #define H_MODE REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_mode) 133 #define h_timr hscx_rw.hscx_r.hscx_timr 134 #define H_TIMR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_timr) 135 #define h_exir hscx_rw.hscx_r.hscx_exir 136 #define H_EXIR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_exir) 137 #define h_rbcl hscx_rw.hscx_r.hscx_rbcl 138 #define H_RBCL REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rbcl) 139 #define h_rsta hscx_rw.hscx_r.hscx_rsta 140 #define H_RSTA REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rsta) 141 #define h_ral1 hscx_rw.hscx_r.hscx_ral1 142 #define H_RAL1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ral1) 143 #define h_rhcr hscx_rw.hscx_r.hscx_rhcr 144 #define H_RHCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rhcr) 145 #define h_ccr2 hscx_rw.hscx_r.hscx_ccr2 146 #define H_CCR2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ccr2) 147 #define h_rbch hscx_rw.hscx_r.hscx_rbch 148 #define H_RBCH REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rbch) 149 #define h_vstr hscx_rw.hscx_r.hscx_vstr 150 #define H_VSTR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_vstr) 151 #define h_ccr hscx_rw.hscx_r.hscx_ccr 152 #define H_CCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ccr) 153 154 /* HSCX write registers - for hscx_mode, hscx_timr, hscx_ral1, hscx_ccr2 */ 155 /* see read registers */ 156 157 #define h_mask hscx_rw.hscx_w.hscx_mask 158 #define H_MASK REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_mask) 159 #define h_cmdr hscx_rw.hscx_w.hscx_cmdr 160 #define H_CMDR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_cmdr) 161 #define h_xad1 hscx_rw.hscx_w.hscx_xad1 162 #define H_XAD1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xad1) 163 #define h_xad2 hscx_rw.hscx_w.hscx_xad2 164 #define H_XAD2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xad2) 165 #define h_rah1 hscx_rw.hscx_w.hscx_rah1 166 #define H_RAH1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rah1) 167 #define h_rah2 hscx_rw.hscx_w.hscx_rah2 168 #define H_RAH2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rah2) 169 #define h_ral2 hscx_rw.hscx_w.hscx_ral2 170 #define H_RAL2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_ral2) 171 #define h_xbcl hscx_rw.hscx_w.hscx_xbcl 172 #define H_XBCL REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xbcl) 173 #define h_bgr hscx_rw.hscx_w.hscx_bgr 174 #define H_BGR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_bgr) 175 #define h_xbch hscx_rw.hscx_w.hscx_xbch 176 #define H_XBCH REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xbch) 177 #define h_rlcr hscx_rw.hscx_w.hscx_rlcr 178 #define H_RLCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rlcr) 179 #define h_ccr1 hscx_rw.hscx_w.hscx_ccr1 180 #define H_CCR1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_ccr1) 181 #define h_tsax hscx_rw.hscx_w.hscx_tsax 182 #define H_TSAX REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_tsax) 183 #define h_tsar hscx_rw.hscx_w.hscx_tsar 184 #define H_TSAR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_tsar) 185 #define h_xccr hscx_rw.hscx_w.hscx_xccr 186 #define H_XCCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xccr) 187 #define h_rccr hscx_rw.hscx_w.hscx_rccr 188 #define H_RCCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rccr) 189 190 #define HSCX_ISTA_RME 0x80 191 #define HSCX_ISTA_RPF 0x40 192 #define HSCX_ISTA_RSC 0x20 193 #define HSCX_ISTA_XPR 0x10 194 #define HSCX_ISTA_TIN 0x08 195 #define HSCX_ISTA_ICA 0x04 196 #define HSCX_ISTA_EXA 0x02 197 #define HSCX_ISTA_EXB 0x01 198 199 #define HSCX_MASK_RME 0x80 200 #define HSCX_MASK_RPF 0x40 201 #define HSCX_MASK_RSC 0x20 202 #define HSCX_MASK_XPR 0x10 203 #define HSCX_MASK_TIN 0x08 204 #define HSCX_MASK_ICA 0x04 205 #define HSCX_MASK_EXA 0x02 206 #define HSCX_MASK_EXB 0x01 207 208 #define HSCX_EXIR_XMR 0x80 209 #define HSCX_EXIR_XDU 0x40 210 #define HSCX_EXIR_PCE 0x20 211 #define HSCX_EXIR_RFO 0x10 212 #define HSCX_EXIR_CSC 0x08 213 #define HSCX_EXIR_RFS 0x04 214 215 /* the other bits are always 0 */ 216 217 #define HSCX_STAR_XDOV 0x80 218 #define HSCX_STAR_XFW 0x40 219 #define HSCX_STAR_XRNR 0x20 220 #define HSCX_STAR_RRNR 0x10 221 #define HSCX_STAR_RLI 0x08 222 #define HSCX_STAR_CEC 0x04 223 #define HSCX_STAR_CTS 0x02 224 #define HSCX_STAR_WFA 0x01 225 226 #define HSCX_CMDR_RMC 0x80 227 #define HSCX_CMDR_RHR 0x40 228 /* also known as XREP in transparent mode */ 229 #define HSCX_CMDR_RNR 0x20 230 #define HSCX_CMDR_STI 0x10 231 #define HSCX_CMDR_XTF 0x08 232 #define HSCX_CMDR_XIF 0x04 233 #define HSCX_CMDR_XME 0x02 234 #define HSCX_CMDR_XRES 0x01 235 236 #define HSCX_MODE_MDS1 0x80 237 #define HSCX_MODE_MDS0 0x40 238 #define HSCX_MODE_ADM 0x20 239 #define HSCX_MODE_TMD 0x10 240 #define HSCX_MODE_RAC 0x08 241 #define HSCX_MODE_RTS 0x04 242 #define HSCX_MODE_TRS 0x02 243 #define HSCX_MODE_TLP 0x01 244 245 #define HSCX_RSTA_VFR 0x80 246 #define HSCX_RSTA_RDO 0x40 247 #define HSCX_RSTA_CRC 0x20 248 #define HSCX_RSTA_RAB 0x10 249 #define HSCX_RSTA_HA1 0x08 250 #define HSCX_RSTA_HA0 0x04 251 #define HSCX_RSTA_CR 0x02 252 #define HSCX_RSTA_LA 0x01 253 254 #define HSCX_RSTA_MASK 0xf0 /* the interesting ones */ 255 256 /* only used in DMA mode */ 257 #define HSCX_XBCH_DMA 0x80 258 #define HSCX_XBCH_NRM 0x40 259 #define HSCX_XBCH_CAS 0x20 260 #define HSCX_XBCH_XC 0x10 261 /* the rest are bits 11 thru 8 of the byte count */ 262 263 #define HSCX_RBCH_DMA 0x80 264 #define HSCX_RBCH_NRM 0x40 265 #define HSCX_RBCH_CAS 0x20 266 #define HSCX_RBCH_OV 0x10 267 /* the rest are bits 11 thru 8 of the byte count */ 268 269 #define HSCX_VSTR_CD 0x80 270 /* bits 6 thru 4 are 0 */ 271 /* bits 3 thru 0 are the version number */ 272 273 #define HSCX_RLCR_RC 0x80 274 /* the rest of the bits are used to set the received length */ 275 276 #define HSCX_CCR1_PU 0x80 277 /* bits 6 and 5 are SC1 SC0 */ 278 #define HSCX_CCR1_ODS 0x10 279 #define HSCX_CCR1_ITF 0x08 280 #define HSCX_CCR1_CM2 0x04 281 #define HSCX_CCR1_CM1 0x02 282 #define HSCX_CCR1_CM0 0x01 283 284 /* for clock mode 5 */ 285 #define HSCX_CCR2_SOC2 0x80 286 #define HSCX_CCR2_SOC1 0x40 287 #define HSCX_CCR2_XCS0 0x20 288 #define HSCX_CCR2_RCS0 0x10 289 #define HSCX_CCR2_TIO 0x08 290 #define HSCX_CCR2_CIE 0x04 291 #define HSCX_CCR2_RIE 0x02 292 #define HSCX_CCR2_DIV 0x01 293 294 /* bits 7 thru 2 are TSNX */ 295 #define HSCX_TSAX_XCS2 0x02 296 #define HSCX_TSAX_XCS1 0x01 297 298 /* bits 7 thru 2 are TSNR */ 299 #define HSCX_TSAR_RCS2 0x02 300 #define HSCX_TSAR_RCS1 0x01 301 302 #endif /* I4B_HSCX_H_ */ 303