1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #include "lldb/Core/ArchSpec.h"
11
12 #include <stdio.h>
13 #include <errno.h>
14
15 #include <string>
16
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/Support/COFF.h"
19 #include "llvm/Support/ELF.h"
20 #include "llvm/Support/Host.h"
21
22 #include "lldb/Core/RegularExpression.h"
23 #include "lldb/Core/StringList.h"
24 #include "lldb/Host/Endian.h"
25 #include "lldb/Host/HostInfo.h"
26 #include "lldb/Target/Platform.h"
27 #include "lldb/Target/Process.h"
28 #include "lldb/Target/RegisterContext.h"
29 #include "lldb/Target/Thread.h"
30 #include "lldb/Utility/NameMatches.h"
31 #include "lldb/Utility/SafeMachO.h"
32 #include "Plugins/Process/Utility/ARMDefines.h"
33 #include "Plugins/Process/Utility/InstructionUtils.h"
34
35 using namespace lldb;
36 using namespace lldb_private;
37
38 #define ARCH_SPEC_SEPARATOR_CHAR '-'
39
40
41 static bool cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match);
42
43 namespace lldb_private {
44
45 struct CoreDefinition
46 {
47 ByteOrder default_byte_order;
48 uint32_t addr_byte_size;
49 uint32_t min_opcode_byte_size;
50 uint32_t max_opcode_byte_size;
51 llvm::Triple::ArchType machine;
52 ArchSpec::Core core;
53 const char * const name;
54 };
55
56 }
57
58 // This core information can be looked using the ArchSpec::Core as the index
59 static const CoreDefinition g_core_definitions[] =
60 {
61 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_generic , "arm" },
62 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4 , "armv4" },
63 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4t , "armv4t" },
64 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5 , "armv5" },
65 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5e , "armv5e" },
66 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5t , "armv5t" },
67 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6 , "armv6" },
68 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6m , "armv6m" },
69 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7 , "armv7" },
70 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7f , "armv7f" },
71 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7s , "armv7s" },
72 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7k , "armv7k" },
73 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7m , "armv7m" },
74 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7em , "armv7em" },
75 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_xscale , "xscale" },
76 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumb , "thumb" },
77 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv4t , "thumbv4t" },
78 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5 , "thumbv5" },
79 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5e , "thumbv5e" },
80 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6 , "thumbv6" },
81 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6m , "thumbv6m" },
82 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7 , "thumbv7" },
83 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7f , "thumbv7f" },
84 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7s , "thumbv7s" },
85 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7k , "thumbv7k" },
86 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7m , "thumbv7m" },
87 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7em , "thumbv7em" },
88 { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_arm64 , "arm64" },
89 { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_armv8 , "armv8" },
90 { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_aarch64 , "aarch64" },
91
92 // mips32, mips32r2, mips32r3, mips32r5, mips32r6
93 { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32 , "mips" },
94 { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r2 , "mipsr2" },
95 { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r3 , "mipsr3" },
96 { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r5 , "mipsr5" },
97 { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r6 , "mipsr6" },
98 { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el , "mipsel" },
99 { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r2el , "mipsr2el" },
100 { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r3el , "mipsr3el" },
101 { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r5el , "mipsr5el" },
102 { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r6el , "mipsr6el" },
103
104 // mips64, mips64r2, mips64r3, mips64r5, mips64r6
105 { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" },
106 { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r2 , "mips64r2" },
107 { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r3 , "mips64r3" },
108 { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r5 , "mips64r5" },
109 { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r6 , "mips64r6" },
110 { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64el , "mips64el" },
111 { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r2el , "mips64r2el" },
112 { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r3el , "mips64r3el" },
113 { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r5el , "mips64r5el" },
114 { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r6el , "mips64r6el" },
115
116 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_generic , "powerpc" },
117 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc601 , "ppc601" },
118 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc602 , "ppc602" },
119 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603 , "ppc603" },
120 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603e , "ppc603e" },
121 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603ev , "ppc603ev" },
122 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604 , "ppc604" },
123 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604e , "ppc604e" },
124 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc620 , "ppc620" },
125 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc750 , "ppc750" },
126 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7400 , "ppc7400" },
127 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7450 , "ppc7450" },
128 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc970 , "ppc970" },
129
130 { eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_generic , "powerpc64" },
131 { eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_ppc970_64 , "ppc970-64" },
132
133 { eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc , ArchSpec::eCore_sparc_generic , "sparc" },
134 { eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, ArchSpec::eCore_sparc9_generic , "sparcv9" },
135
136 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i386 , "i386" },
137 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486 , "i486" },
138 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486sx , "i486sx" },
139 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i686 , "i686" },
140
141 { eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64 , "x86_64" },
142 { eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64h , "x86_64h" },
143 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_generic, "hexagon" },
144 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4" },
145 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5" },
146
147 { eByteOrderLittle, 4, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach32 , "unknown-mach-32" },
148 { eByteOrderLittle, 8, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach64 , "unknown-mach-64" },
149
150 { eByteOrderBig , 4, 1, 1 , llvm::Triple::kalimba , ArchSpec::eCore_kalimba3 , "kalimba3" },
151 { eByteOrderLittle, 4, 1, 1 , llvm::Triple::kalimba , ArchSpec::eCore_kalimba4 , "kalimba4" },
152 { eByteOrderLittle, 4, 1, 1 , llvm::Triple::kalimba , ArchSpec::eCore_kalimba5 , "kalimba5" }
153 };
154
155 // Ensure that we have an entry in the g_core_definitions for each core. If you comment out an entry above,
156 // you will need to comment out the corresponding ArchSpec::Core enumeration.
157 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == ArchSpec::kNumCores, "make sure we have one core definition for each core");
158
159
160 struct ArchDefinitionEntry
161 {
162 ArchSpec::Core core;
163 uint32_t cpu;
164 uint32_t sub;
165 uint32_t cpu_mask;
166 uint32_t sub_mask;
167 };
168
169 struct ArchDefinition
170 {
171 ArchitectureType type;
172 size_t num_entries;
173 const ArchDefinitionEntry *entries;
174 const char *name;
175 };
176
177
178 size_t
AutoComplete(const char * name,StringList & matches)179 ArchSpec::AutoComplete (const char *name, StringList &matches)
180 {
181 uint32_t i;
182 if (name && name[0])
183 {
184 for (i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
185 {
186 if (NameMatches(g_core_definitions[i].name, eNameMatchStartsWith, name))
187 matches.AppendString (g_core_definitions[i].name);
188 }
189 }
190 else
191 {
192 for (i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
193 matches.AppendString (g_core_definitions[i].name);
194 }
195 return matches.GetSize();
196 }
197
198
199
200 #define CPU_ANY (UINT32_MAX)
201
202 //===----------------------------------------------------------------------===//
203 // A table that gets searched linearly for matches. This table is used to
204 // convert cpu type and subtypes to architecture names, and to convert
205 // architecture names to cpu types and subtypes. The ordering is important and
206 // allows the precedence to be set when the table is built.
207 #define SUBTYPE_MASK 0x00FFFFFFu
208 static const ArchDefinitionEntry g_macho_arch_entries[] =
209 {
210 { ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , CPU_ANY, UINT32_MAX , UINT32_MAX },
211 { ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK },
212 { ArchSpec::eCore_arm_armv4 , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
213 { ArchSpec::eCore_arm_armv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
214 { ArchSpec::eCore_arm_armv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK },
215 { ArchSpec::eCore_arm_armv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK },
216 { ArchSpec::eCore_arm_armv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
217 { ArchSpec::eCore_arm_armv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
218 { ArchSpec::eCore_arm_armv5t , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
219 { ArchSpec::eCore_arm_xscale , llvm::MachO::CPU_TYPE_ARM , 8 , UINT32_MAX , SUBTYPE_MASK },
220 { ArchSpec::eCore_arm_armv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK },
221 { ArchSpec::eCore_arm_armv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK },
222 { ArchSpec::eCore_arm_armv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK },
223 { ArchSpec::eCore_arm_armv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK },
224 { ArchSpec::eCore_arm_armv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK },
225 { ArchSpec::eCore_arm_armv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK },
226 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 1 , UINT32_MAX , SUBTYPE_MASK },
227 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 0 , UINT32_MAX , SUBTYPE_MASK },
228 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 13 , UINT32_MAX , SUBTYPE_MASK },
229 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , CPU_ANY, UINT32_MAX , SUBTYPE_MASK },
230 { ArchSpec::eCore_thumb , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK },
231 { ArchSpec::eCore_thumbv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
232 { ArchSpec::eCore_thumbv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
233 { ArchSpec::eCore_thumbv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
234 { ArchSpec::eCore_thumbv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK },
235 { ArchSpec::eCore_thumbv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK },
236 { ArchSpec::eCore_thumbv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK },
237 { ArchSpec::eCore_thumbv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK },
238 { ArchSpec::eCore_thumbv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK },
239 { ArchSpec::eCore_thumbv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK },
240 { ArchSpec::eCore_thumbv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK },
241 { ArchSpec::eCore_thumbv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK },
242 { ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , CPU_ANY, UINT32_MAX , UINT32_MAX },
243 { ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , 0 , UINT32_MAX , SUBTYPE_MASK },
244 { ArchSpec::eCore_ppc_ppc601 , llvm::MachO::CPU_TYPE_POWERPC , 1 , UINT32_MAX , SUBTYPE_MASK },
245 { ArchSpec::eCore_ppc_ppc602 , llvm::MachO::CPU_TYPE_POWERPC , 2 , UINT32_MAX , SUBTYPE_MASK },
246 { ArchSpec::eCore_ppc_ppc603 , llvm::MachO::CPU_TYPE_POWERPC , 3 , UINT32_MAX , SUBTYPE_MASK },
247 { ArchSpec::eCore_ppc_ppc603e , llvm::MachO::CPU_TYPE_POWERPC , 4 , UINT32_MAX , SUBTYPE_MASK },
248 { ArchSpec::eCore_ppc_ppc603ev , llvm::MachO::CPU_TYPE_POWERPC , 5 , UINT32_MAX , SUBTYPE_MASK },
249 { ArchSpec::eCore_ppc_ppc604 , llvm::MachO::CPU_TYPE_POWERPC , 6 , UINT32_MAX , SUBTYPE_MASK },
250 { ArchSpec::eCore_ppc_ppc604e , llvm::MachO::CPU_TYPE_POWERPC , 7 , UINT32_MAX , SUBTYPE_MASK },
251 { ArchSpec::eCore_ppc_ppc620 , llvm::MachO::CPU_TYPE_POWERPC , 8 , UINT32_MAX , SUBTYPE_MASK },
252 { ArchSpec::eCore_ppc_ppc750 , llvm::MachO::CPU_TYPE_POWERPC , 9 , UINT32_MAX , SUBTYPE_MASK },
253 { ArchSpec::eCore_ppc_ppc7400 , llvm::MachO::CPU_TYPE_POWERPC , 10 , UINT32_MAX , SUBTYPE_MASK },
254 { ArchSpec::eCore_ppc_ppc7450 , llvm::MachO::CPU_TYPE_POWERPC , 11 , UINT32_MAX , SUBTYPE_MASK },
255 { ArchSpec::eCore_ppc_ppc970 , llvm::MachO::CPU_TYPE_POWERPC , 100 , UINT32_MAX , SUBTYPE_MASK },
256 { ArchSpec::eCore_ppc64_generic , llvm::MachO::CPU_TYPE_POWERPC64 , 0 , UINT32_MAX , SUBTYPE_MASK },
257 { ArchSpec::eCore_ppc64_ppc970_64 , llvm::MachO::CPU_TYPE_POWERPC64 , 100 , UINT32_MAX , SUBTYPE_MASK },
258 { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , 3 , UINT32_MAX , SUBTYPE_MASK },
259 { ArchSpec::eCore_x86_32_i486 , llvm::MachO::CPU_TYPE_I386 , 4 , UINT32_MAX , SUBTYPE_MASK },
260 { ArchSpec::eCore_x86_32_i486sx , llvm::MachO::CPU_TYPE_I386 , 0x84 , UINT32_MAX , SUBTYPE_MASK },
261 { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , CPU_ANY, UINT32_MAX , UINT32_MAX },
262 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 3 , UINT32_MAX , SUBTYPE_MASK },
263 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 4 , UINT32_MAX , SUBTYPE_MASK },
264 { ArchSpec::eCore_x86_64_x86_64h , llvm::MachO::CPU_TYPE_X86_64 , 8 , UINT32_MAX , SUBTYPE_MASK },
265 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , CPU_ANY, UINT32_MAX , UINT32_MAX },
266 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
267 { ArchSpec::eCore_uknownMach32 , 0 , 0 , 0xFF000000u, 0x00000000u },
268 { ArchSpec::eCore_uknownMach64 , llvm::MachO::CPU_ARCH_ABI64 , 0 , 0xFF000000u, 0x00000000u }
269 };
270 static const ArchDefinition g_macho_arch_def = {
271 eArchTypeMachO,
272 llvm::array_lengthof(g_macho_arch_entries),
273 g_macho_arch_entries,
274 "mach-o"
275 };
276
277 //===----------------------------------------------------------------------===//
278 // A table that gets searched linearly for matches. This table is used to
279 // convert cpu type and subtypes to architecture names, and to convert
280 // architecture names to cpu types and subtypes. The ordering is important and
281 // allows the precedence to be set when the table is built.
282 static const ArchDefinitionEntry g_elf_arch_entries[] =
283 {
284 { ArchSpec::eCore_sparc_generic , llvm::ELF::EM_SPARC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Sparc
285 { ArchSpec::eCore_x86_32_i386 , llvm::ELF::EM_386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80386
286 { ArchSpec::eCore_x86_32_i486 , llvm::ELF::EM_IAMCU , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel MCU // FIXME: is this correct?
287 { ArchSpec::eCore_ppc_generic , llvm::ELF::EM_PPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC
288 { ArchSpec::eCore_ppc64_generic , llvm::ELF::EM_PPC64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC64
289 { ArchSpec::eCore_arm_generic , llvm::ELF::EM_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
290 { ArchSpec::eCore_arm_aarch64 , llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM64
291 { ArchSpec::eCore_sparc9_generic , llvm::ELF::EM_SPARCV9, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // SPARC V9
292 { ArchSpec::eCore_x86_64_x86_64 , llvm::ELF::EM_X86_64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // AMD64
293 { ArchSpec::eCore_mips32 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32
294 { ArchSpec::eCore_mips32r2 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32r2
295 { ArchSpec::eCore_mips32r6 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32r6
296 { ArchSpec::eCore_mips32el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32el
297 { ArchSpec::eCore_mips32r2el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32r2el
298 { ArchSpec::eCore_mips32r6el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32r6el
299 { ArchSpec::eCore_mips64 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64
300 { ArchSpec::eCore_mips64r2 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64r2
301 { ArchSpec::eCore_mips64r6 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64r6
302 { ArchSpec::eCore_mips64el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64el
303 { ArchSpec::eCore_mips64r2el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64r2el
304 { ArchSpec::eCore_mips64r6el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64r6el
305 { ArchSpec::eCore_hexagon_generic , llvm::ELF::EM_HEXAGON, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // HEXAGON
306 { ArchSpec::eCore_kalimba3 , llvm::ELF::EM_CSR_KALIMBA, llvm::Triple::KalimbaSubArch_v3, 0xFFFFFFFFu, 0xFFFFFFFFu }, // KALIMBA
307 { ArchSpec::eCore_kalimba4 , llvm::ELF::EM_CSR_KALIMBA, llvm::Triple::KalimbaSubArch_v4, 0xFFFFFFFFu, 0xFFFFFFFFu }, // KALIMBA
308 { ArchSpec::eCore_kalimba5 , llvm::ELF::EM_CSR_KALIMBA, llvm::Triple::KalimbaSubArch_v5, 0xFFFFFFFFu, 0xFFFFFFFFu } // KALIMBA
309 };
310
311 static const ArchDefinition g_elf_arch_def = {
312 eArchTypeELF,
313 llvm::array_lengthof(g_elf_arch_entries),
314 g_elf_arch_entries,
315 "elf",
316 };
317
318 static const ArchDefinitionEntry g_coff_arch_entries[] =
319 {
320 { ArchSpec::eCore_x86_32_i386 , llvm::COFF::IMAGE_FILE_MACHINE_I386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80x86
321 { ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC
322 { ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC (with FPU)
323 { ArchSpec::eCore_arm_generic , llvm::COFF::IMAGE_FILE_MACHINE_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
324 { ArchSpec::eCore_arm_armv7 , llvm::COFF::IMAGE_FILE_MACHINE_ARMNT , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7
325 { ArchSpec::eCore_thumb , llvm::COFF::IMAGE_FILE_MACHINE_THUMB , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7
326 { ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // AMD64
327 };
328
329 static const ArchDefinition g_coff_arch_def = {
330 eArchTypeCOFF,
331 llvm::array_lengthof(g_coff_arch_entries),
332 g_coff_arch_entries,
333 "pe-coff",
334 };
335
336 //===----------------------------------------------------------------------===//
337 // Table of all ArchDefinitions
338 static const ArchDefinition *g_arch_definitions[] = {
339 &g_macho_arch_def,
340 &g_elf_arch_def,
341 &g_coff_arch_def
342 };
343
344 static const size_t k_num_arch_definitions = llvm::array_lengthof(g_arch_definitions);
345
346 //===----------------------------------------------------------------------===//
347 // Static helper functions.
348
349
350 // Get the architecture definition for a given object type.
351 static const ArchDefinition *
FindArchDefinition(ArchitectureType arch_type)352 FindArchDefinition (ArchitectureType arch_type)
353 {
354 for (unsigned int i = 0; i < k_num_arch_definitions; ++i)
355 {
356 const ArchDefinition *def = g_arch_definitions[i];
357 if (def->type == arch_type)
358 return def;
359 }
360 return NULL;
361 }
362
363 // Get an architecture definition by name.
364 static const CoreDefinition *
FindCoreDefinition(llvm::StringRef name)365 FindCoreDefinition (llvm::StringRef name)
366 {
367 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
368 {
369 if (name.equals_lower(g_core_definitions[i].name))
370 return &g_core_definitions[i];
371 }
372 return NULL;
373 }
374
375 static inline const CoreDefinition *
FindCoreDefinition(ArchSpec::Core core)376 FindCoreDefinition (ArchSpec::Core core)
377 {
378 if (core >= 0 && core < llvm::array_lengthof(g_core_definitions))
379 return &g_core_definitions[core];
380 return NULL;
381 }
382
383 // Get a definition entry by cpu type and subtype.
384 static const ArchDefinitionEntry *
FindArchDefinitionEntry(const ArchDefinition * def,uint32_t cpu,uint32_t sub)385 FindArchDefinitionEntry (const ArchDefinition *def, uint32_t cpu, uint32_t sub)
386 {
387 if (def == NULL)
388 return NULL;
389
390 const ArchDefinitionEntry *entries = def->entries;
391 for (size_t i = 0; i < def->num_entries; ++i)
392 {
393 if (entries[i].cpu == (cpu & entries[i].cpu_mask))
394 if (entries[i].sub == (sub & entries[i].sub_mask))
395 return &entries[i];
396 }
397 return NULL;
398 }
399
400 static const ArchDefinitionEntry *
FindArchDefinitionEntry(const ArchDefinition * def,ArchSpec::Core core)401 FindArchDefinitionEntry (const ArchDefinition *def, ArchSpec::Core core)
402 {
403 if (def == NULL)
404 return NULL;
405
406 const ArchDefinitionEntry *entries = def->entries;
407 for (size_t i = 0; i < def->num_entries; ++i)
408 {
409 if (entries[i].core == core)
410 return &entries[i];
411 }
412 return NULL;
413 }
414
415 //===----------------------------------------------------------------------===//
416 // Constructors and destructors.
417
ArchSpec()418 ArchSpec::ArchSpec() :
419 m_triple (),
420 m_core (kCore_invalid),
421 m_byte_order (eByteOrderInvalid),
422 m_distribution_id (),
423 m_flags (0)
424 {
425 }
426
ArchSpec(const char * triple_cstr,Platform * platform)427 ArchSpec::ArchSpec (const char *triple_cstr, Platform *platform) :
428 m_triple (),
429 m_core (kCore_invalid),
430 m_byte_order (eByteOrderInvalid),
431 m_distribution_id (),
432 m_flags (0)
433 {
434 if (triple_cstr)
435 SetTriple(triple_cstr, platform);
436 }
437
438
ArchSpec(const char * triple_cstr)439 ArchSpec::ArchSpec (const char *triple_cstr) :
440 m_triple (),
441 m_core (kCore_invalid),
442 m_byte_order (eByteOrderInvalid),
443 m_distribution_id (),
444 m_flags (0)
445 {
446 if (triple_cstr)
447 SetTriple(triple_cstr);
448 }
449
ArchSpec(const llvm::Triple & triple)450 ArchSpec::ArchSpec(const llvm::Triple &triple) :
451 m_triple (),
452 m_core (kCore_invalid),
453 m_byte_order (eByteOrderInvalid),
454 m_distribution_id (),
455 m_flags (0)
456 {
457 SetTriple(triple);
458 }
459
ArchSpec(ArchitectureType arch_type,uint32_t cpu,uint32_t subtype)460 ArchSpec::ArchSpec (ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) :
461 m_triple (),
462 m_core (kCore_invalid),
463 m_byte_order (eByteOrderInvalid),
464 m_distribution_id (),
465 m_flags (0)
466 {
467 SetArchitecture (arch_type, cpu, subtype);
468 }
469
~ArchSpec()470 ArchSpec::~ArchSpec()
471 {
472 }
473
474 //===----------------------------------------------------------------------===//
475 // Assignment and initialization.
476
477 const ArchSpec&
operator =(const ArchSpec & rhs)478 ArchSpec::operator= (const ArchSpec& rhs)
479 {
480 if (this != &rhs)
481 {
482 m_triple = rhs.m_triple;
483 m_core = rhs.m_core;
484 m_byte_order = rhs.m_byte_order;
485 m_distribution_id = rhs.m_distribution_id;
486 m_flags = rhs.m_flags;
487 }
488 return *this;
489 }
490
491 void
Clear()492 ArchSpec::Clear()
493 {
494 m_triple = llvm::Triple();
495 m_core = kCore_invalid;
496 m_byte_order = eByteOrderInvalid;
497 m_distribution_id.Clear ();
498 m_flags = 0;
499 }
500
501 //===----------------------------------------------------------------------===//
502 // Predicates.
503
504
505 const char *
GetArchitectureName() const506 ArchSpec::GetArchitectureName () const
507 {
508 const CoreDefinition *core_def = FindCoreDefinition (m_core);
509 if (core_def)
510 return core_def->name;
511 return "unknown";
512 }
513
514 uint32_t
GetMachOCPUType() const515 ArchSpec::GetMachOCPUType () const
516 {
517 const CoreDefinition *core_def = FindCoreDefinition (m_core);
518 if (core_def)
519 {
520 const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core);
521 if (arch_def)
522 {
523 return arch_def->cpu;
524 }
525 }
526 return LLDB_INVALID_CPUTYPE;
527 }
528
529 uint32_t
GetMachOCPUSubType() const530 ArchSpec::GetMachOCPUSubType () const
531 {
532 const CoreDefinition *core_def = FindCoreDefinition (m_core);
533 if (core_def)
534 {
535 const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core);
536 if (arch_def)
537 {
538 return arch_def->sub;
539 }
540 }
541 return LLDB_INVALID_CPUTYPE;
542 }
543
544 uint32_t
GetDataByteSize() const545 ArchSpec::GetDataByteSize () const
546 {
547 switch (m_core)
548 {
549 case eCore_kalimba3:
550 return 4;
551 case eCore_kalimba4:
552 return 1;
553 case eCore_kalimba5:
554 return 4;
555 default:
556 return 1;
557 }
558 return 1;
559 }
560
561 uint32_t
GetCodeByteSize() const562 ArchSpec::GetCodeByteSize () const
563 {
564 switch (m_core)
565 {
566 case eCore_kalimba3:
567 return 4;
568 case eCore_kalimba4:
569 return 1;
570 case eCore_kalimba5:
571 return 1;
572 default:
573 return 1;
574 }
575 return 1;
576 }
577
578 llvm::Triple::ArchType
GetMachine() const579 ArchSpec::GetMachine () const
580 {
581 const CoreDefinition *core_def = FindCoreDefinition (m_core);
582 if (core_def)
583 return core_def->machine;
584
585 return llvm::Triple::UnknownArch;
586 }
587
588 const ConstString&
GetDistributionId() const589 ArchSpec::GetDistributionId () const
590 {
591 return m_distribution_id;
592 }
593
594 void
SetDistributionId(const char * distribution_id)595 ArchSpec::SetDistributionId (const char* distribution_id)
596 {
597 m_distribution_id.SetCString (distribution_id);
598 }
599
600 uint32_t
GetAddressByteSize() const601 ArchSpec::GetAddressByteSize() const
602 {
603 const CoreDefinition *core_def = FindCoreDefinition (m_core);
604 if (core_def)
605 return core_def->addr_byte_size;
606 return 0;
607 }
608
609 ByteOrder
GetDefaultEndian() const610 ArchSpec::GetDefaultEndian () const
611 {
612 const CoreDefinition *core_def = FindCoreDefinition (m_core);
613 if (core_def)
614 return core_def->default_byte_order;
615 return eByteOrderInvalid;
616 }
617
618 bool
CharIsSignedByDefault() const619 ArchSpec::CharIsSignedByDefault () const
620 {
621 switch (m_triple.getArch()) {
622 default:
623 return true;
624
625 case llvm::Triple::aarch64:
626 case llvm::Triple::aarch64_be:
627 case llvm::Triple::arm:
628 case llvm::Triple::armeb:
629 case llvm::Triple::thumb:
630 case llvm::Triple::thumbeb:
631 return m_triple.isOSDarwin() || m_triple.isOSWindows();
632
633 case llvm::Triple::ppc:
634 case llvm::Triple::ppc64:
635 return m_triple.isOSDarwin();
636
637 case llvm::Triple::ppc64le:
638 case llvm::Triple::systemz:
639 case llvm::Triple::xcore:
640 return false;
641 }
642 }
643
644 lldb::ByteOrder
GetByteOrder() const645 ArchSpec::GetByteOrder () const
646 {
647 if (m_byte_order == eByteOrderInvalid)
648 return GetDefaultEndian();
649 return m_byte_order;
650 }
651
652 //===----------------------------------------------------------------------===//
653 // Mutators.
654
655 bool
SetTriple(const llvm::Triple & triple)656 ArchSpec::SetTriple (const llvm::Triple &triple)
657 {
658 m_triple = triple;
659
660 llvm::StringRef arch_name (m_triple.getArchName());
661 const CoreDefinition *core_def = FindCoreDefinition (arch_name);
662 if (core_def)
663 {
664 m_core = core_def->core;
665 // Set the byte order to the default byte order for an architecture.
666 // This can be modified if needed for cases when cores handle both
667 // big and little endian
668 m_byte_order = core_def->default_byte_order;
669 }
670 else
671 {
672 Clear();
673 }
674
675
676 return IsValid();
677 }
678
679 static bool
ParseMachCPUDashSubtypeTriple(const char * triple_cstr,ArchSpec & arch)680 ParseMachCPUDashSubtypeTriple (const char *triple_cstr, ArchSpec &arch)
681 {
682 // Accept "12-10" or "12.10" as cpu type/subtype
683 if (isdigit(triple_cstr[0]))
684 {
685 char *end = NULL;
686 errno = 0;
687 uint32_t cpu = (uint32_t)::strtoul (triple_cstr, &end, 0);
688 if (errno == 0 && cpu != 0 && end && ((*end == '-') || (*end == '.')))
689 {
690 errno = 0;
691 uint32_t sub = (uint32_t)::strtoul (end + 1, &end, 0);
692 if (errno == 0 && end && ((*end == '-') || (*end == '.') || (*end == '\0')))
693 {
694 if (arch.SetArchitecture (eArchTypeMachO, cpu, sub))
695 {
696 if (*end == '-')
697 {
698 llvm::StringRef vendor_os (end + 1);
699 size_t dash_pos = vendor_os.find('-');
700 if (dash_pos != llvm::StringRef::npos)
701 {
702 llvm::StringRef vendor_str(vendor_os.substr(0, dash_pos));
703 arch.GetTriple().setVendorName(vendor_str);
704 const size_t vendor_start_pos = dash_pos+1;
705 dash_pos = vendor_os.find('-', vendor_start_pos);
706 if (dash_pos == llvm::StringRef::npos)
707 {
708 if (vendor_start_pos < vendor_os.size())
709 arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos));
710 }
711 else
712 {
713 arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos, dash_pos - vendor_start_pos));
714 }
715 }
716 }
717 return true;
718 }
719 }
720 }
721 }
722 return false;
723 }
724 bool
SetTriple(const char * triple_cstr)725 ArchSpec::SetTriple (const char *triple_cstr)
726 {
727 if (triple_cstr && triple_cstr[0])
728 {
729 if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this))
730 return true;
731
732 llvm::StringRef triple_stref (triple_cstr);
733 if (triple_stref.startswith (LLDB_ARCH_DEFAULT))
734 {
735 // Special case for the current host default architectures...
736 if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT))
737 *this = HostInfo::GetArchitecture(HostInfo::eArchKind32);
738 else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT))
739 *this = HostInfo::GetArchitecture(HostInfo::eArchKind64);
740 else if (triple_stref.equals (LLDB_ARCH_DEFAULT))
741 *this = HostInfo::GetArchitecture(HostInfo::eArchKindDefault);
742 }
743 else
744 {
745 std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref));
746 triple_stref = normalized_triple_sstr;
747 SetTriple (llvm::Triple (triple_stref));
748 }
749 }
750 else
751 Clear();
752 return IsValid();
753 }
754
755 bool
SetTriple(const char * triple_cstr,Platform * platform)756 ArchSpec::SetTriple (const char *triple_cstr, Platform *platform)
757 {
758 if (triple_cstr && triple_cstr[0])
759 {
760 if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this))
761 return true;
762
763 llvm::StringRef triple_stref (triple_cstr);
764 if (triple_stref.startswith (LLDB_ARCH_DEFAULT))
765 {
766 // Special case for the current host default architectures...
767 if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT))
768 *this = HostInfo::GetArchitecture(HostInfo::eArchKind32);
769 else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT))
770 *this = HostInfo::GetArchitecture(HostInfo::eArchKind64);
771 else if (triple_stref.equals (LLDB_ARCH_DEFAULT))
772 *this = HostInfo::GetArchitecture(HostInfo::eArchKindDefault);
773 }
774 else
775 {
776 ArchSpec raw_arch (triple_cstr);
777
778 std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref));
779 triple_stref = normalized_triple_sstr;
780 llvm::Triple normalized_triple (triple_stref);
781
782 const bool os_specified = normalized_triple.getOSName().size() > 0;
783 const bool vendor_specified = normalized_triple.getVendorName().size() > 0;
784 const bool env_specified = normalized_triple.getEnvironmentName().size() > 0;
785
786 // If we got an arch only, then default the vendor, os, environment
787 // to match the platform if one is supplied
788 if (!(os_specified || vendor_specified || env_specified))
789 {
790 if (platform)
791 {
792 // If we were given a platform, use the platform's system
793 // architecture. If this is not available (might not be
794 // connected) use the first supported architecture.
795 ArchSpec compatible_arch;
796 if (platform->IsCompatibleArchitecture (raw_arch, false, &compatible_arch))
797 {
798 if (compatible_arch.IsValid())
799 {
800 const llvm::Triple &compatible_triple = compatible_arch.GetTriple();
801 if (!vendor_specified)
802 normalized_triple.setVendor(compatible_triple.getVendor());
803 if (!os_specified)
804 normalized_triple.setOS(compatible_triple.getOS());
805 if (!env_specified && compatible_triple.getEnvironmentName().size())
806 normalized_triple.setEnvironment(compatible_triple.getEnvironment());
807 }
808 }
809 else
810 {
811 *this = raw_arch;
812 return IsValid();
813 }
814 }
815 else
816 {
817 // No platform specified, fall back to the host system for
818 // the default vendor, os, and environment.
819 llvm::Triple host_triple(llvm::sys::getDefaultTargetTriple());
820 if (!vendor_specified)
821 normalized_triple.setVendor(host_triple.getVendor());
822 if (!vendor_specified)
823 normalized_triple.setOS(host_triple.getOS());
824 if (!env_specified && host_triple.getEnvironmentName().size())
825 normalized_triple.setEnvironment(host_triple.getEnvironment());
826 }
827 }
828 SetTriple (normalized_triple);
829 }
830 }
831 else
832 Clear();
833 return IsValid();
834 }
835
836 void
MergeFrom(const ArchSpec & other)837 ArchSpec::MergeFrom(const ArchSpec &other)
838 {
839 if (GetTriple().getVendor() == llvm::Triple::UnknownVendor && !TripleVendorWasSpecified())
840 GetTriple().setVendor(other.GetTriple().getVendor());
841 if (GetTriple().getOS() == llvm::Triple::UnknownOS && !TripleOSWasSpecified())
842 GetTriple().setOS(other.GetTriple().getOS());
843 if (GetTriple().getArch() == llvm::Triple::UnknownArch)
844 GetTriple().setArch(other.GetTriple().getArch());
845 if (GetTriple().getEnvironment() == llvm::Triple::UnknownEnvironment)
846 GetTriple().setEnvironment(other.GetTriple().getEnvironment());
847 }
848
849 bool
SetArchitecture(ArchitectureType arch_type,uint32_t cpu,uint32_t sub,uint32_t os)850 ArchSpec::SetArchitecture (ArchitectureType arch_type, uint32_t cpu, uint32_t sub, uint32_t os)
851 {
852 m_core = kCore_invalid;
853 bool update_triple = true;
854 const ArchDefinition *arch_def = FindArchDefinition(arch_type);
855 if (arch_def)
856 {
857 const ArchDefinitionEntry *arch_def_entry = FindArchDefinitionEntry (arch_def, cpu, sub);
858 if (arch_def_entry)
859 {
860 const CoreDefinition *core_def = FindCoreDefinition (arch_def_entry->core);
861 if (core_def)
862 {
863 m_core = core_def->core;
864 update_triple = false;
865 // Always use the architecture name because it might be more descriptive
866 // than the architecture enum ("armv7" -> llvm::Triple::arm).
867 m_triple.setArchName(llvm::StringRef(core_def->name));
868 if (arch_type == eArchTypeMachO)
869 {
870 m_triple.setVendor (llvm::Triple::Apple);
871 switch (core_def->machine)
872 {
873 case llvm::Triple::aarch64:
874 case llvm::Triple::arm:
875 case llvm::Triple::thumb:
876 m_triple.setOS (llvm::Triple::IOS);
877 break;
878
879 case llvm::Triple::x86:
880 case llvm::Triple::x86_64:
881 // Don't set the OS for x86_64 or for x86 as we want to leave it as an "unspecified unknown"
882 // which means if we ask for the OS from the llvm::Triple we get back llvm::Triple::UnknownOS, but
883 // if we ask for the string value for the OS it will come back empty (unspecified).
884 // We do this because we now have iOS and MacOSX as the OS values for x86 and x86_64 for
885 // normal desktop and simulator binaries. And if we compare a "x86_64-apple-ios" to a "x86_64-apple-"
886 // triple, it will say it is compatible (because the OS is unspecified in the second one and will match
887 // anything in the first
888 break;
889
890 default:
891 m_triple.setOS (llvm::Triple::MacOSX);
892 break;
893 }
894 }
895 else if (arch_type == eArchTypeELF)
896 {
897 switch (os)
898 {
899 case llvm::ELF::ELFOSABI_AIX: m_triple.setOS (llvm::Triple::OSType::AIX); break;
900 case llvm::ELF::ELFOSABI_FREEBSD: m_triple.setOS (llvm::Triple::OSType::FreeBSD); break;
901 case llvm::ELF::ELFOSABI_GNU: m_triple.setOS (llvm::Triple::OSType::Linux); break;
902 case llvm::ELF::ELFOSABI_NETBSD: m_triple.setOS (llvm::Triple::OSType::NetBSD); break;
903 case llvm::ELF::ELFOSABI_OPENBSD: m_triple.setOS (llvm::Triple::OSType::OpenBSD); break;
904 case llvm::ELF::ELFOSABI_SOLARIS: m_triple.setOS (llvm::Triple::OSType::Solaris); break;
905 }
906 }
907 // Fall back onto setting the machine type if the arch by name failed...
908 if (m_triple.getArch () == llvm::Triple::UnknownArch)
909 m_triple.setArch (core_def->machine);
910 }
911 }
912 }
913 CoreUpdated(update_triple);
914 return IsValid();
915 }
916
917 uint32_t
GetMinimumOpcodeByteSize() const918 ArchSpec::GetMinimumOpcodeByteSize() const
919 {
920 const CoreDefinition *core_def = FindCoreDefinition (m_core);
921 if (core_def)
922 return core_def->min_opcode_byte_size;
923 return 0;
924 }
925
926 uint32_t
GetMaximumOpcodeByteSize() const927 ArchSpec::GetMaximumOpcodeByteSize() const
928 {
929 const CoreDefinition *core_def = FindCoreDefinition (m_core);
930 if (core_def)
931 return core_def->max_opcode_byte_size;
932 return 0;
933 }
934
935 bool
IsExactMatch(const ArchSpec & rhs) const936 ArchSpec::IsExactMatch (const ArchSpec& rhs) const
937 {
938 return IsEqualTo (rhs, true);
939 }
940
941 bool
IsCompatibleMatch(const ArchSpec & rhs) const942 ArchSpec::IsCompatibleMatch (const ArchSpec& rhs) const
943 {
944 return IsEqualTo (rhs, false);
945 }
946
947 bool
IsEqualTo(const ArchSpec & rhs,bool exact_match) const948 ArchSpec::IsEqualTo (const ArchSpec& rhs, bool exact_match) const
949 {
950 // explicitly ignoring m_distribution_id in this method.
951
952 if (GetByteOrder() != rhs.GetByteOrder())
953 return false;
954
955 const ArchSpec::Core lhs_core = GetCore ();
956 const ArchSpec::Core rhs_core = rhs.GetCore ();
957
958 const bool core_match = cores_match (lhs_core, rhs_core, true, exact_match);
959
960 if (core_match)
961 {
962 const llvm::Triple &lhs_triple = GetTriple();
963 const llvm::Triple &rhs_triple = rhs.GetTriple();
964
965 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
966 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
967 if (lhs_triple_vendor != rhs_triple_vendor)
968 {
969 if (exact_match)
970 {
971 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
972 const bool lhs_vendor_specified = TripleVendorWasSpecified();
973 // Both architectures had the vendor specified, so if they aren't
974 // equal then we return false
975 if (rhs_vendor_specified && lhs_vendor_specified)
976 return false;
977 }
978
979 // Only fail if both vendor types are not unknown
980 if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
981 rhs_triple_vendor != llvm::Triple::UnknownVendor)
982 return false;
983 }
984
985 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
986 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
987 if (lhs_triple_os != rhs_triple_os)
988 {
989 if (exact_match)
990 {
991 const bool rhs_os_specified = rhs.TripleOSWasSpecified();
992 const bool lhs_os_specified = TripleOSWasSpecified();
993 // Both architectures had the OS specified, so if they aren't
994 // equal then we return false
995 if (rhs_os_specified && lhs_os_specified)
996 return false;
997 }
998
999 // Only fail if both os types are not unknown
1000 if (lhs_triple_os != llvm::Triple::UnknownOS &&
1001 rhs_triple_os != llvm::Triple::UnknownOS)
1002 return false;
1003 }
1004
1005 const llvm::Triple::EnvironmentType lhs_triple_env = lhs_triple.getEnvironment();
1006 const llvm::Triple::EnvironmentType rhs_triple_env = rhs_triple.getEnvironment();
1007
1008 if (lhs_triple_env != rhs_triple_env)
1009 {
1010 // Only fail if both environment types are not unknown
1011 if (lhs_triple_env != llvm::Triple::UnknownEnvironment &&
1012 rhs_triple_env != llvm::Triple::UnknownEnvironment)
1013 return false;
1014 }
1015 return true;
1016 }
1017 return false;
1018 }
1019
1020 //===----------------------------------------------------------------------===//
1021 // Helper methods.
1022
1023 void
CoreUpdated(bool update_triple)1024 ArchSpec::CoreUpdated (bool update_triple)
1025 {
1026 const CoreDefinition *core_def = FindCoreDefinition (m_core);
1027 if (core_def)
1028 {
1029 if (update_triple)
1030 m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
1031 m_byte_order = core_def->default_byte_order;
1032 }
1033 else
1034 {
1035 if (update_triple)
1036 m_triple = llvm::Triple();
1037 m_byte_order = eByteOrderInvalid;
1038 }
1039 }
1040
1041 //===----------------------------------------------------------------------===//
1042 // Operators.
1043
1044 static bool
cores_match(const ArchSpec::Core core1,const ArchSpec::Core core2,bool try_inverse,bool enforce_exact_match)1045 cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match)
1046 {
1047 if (core1 == core2)
1048 return true;
1049
1050 switch (core1)
1051 {
1052 case ArchSpec::kCore_any:
1053 return true;
1054
1055 case ArchSpec::eCore_arm_generic:
1056 if (enforce_exact_match)
1057 break;
1058 // Fall through to case below
1059 case ArchSpec::kCore_arm_any:
1060 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
1061 return true;
1062 if (core2 >= ArchSpec::kCore_thumb_first && core2 <= ArchSpec::kCore_thumb_last)
1063 return true;
1064 if (core2 == ArchSpec::kCore_arm_any)
1065 return true;
1066 break;
1067
1068 case ArchSpec::kCore_x86_32_any:
1069 if ((core2 >= ArchSpec::kCore_x86_32_first && core2 <= ArchSpec::kCore_x86_32_last) || (core2 == ArchSpec::kCore_x86_32_any))
1070 return true;
1071 break;
1072
1073 case ArchSpec::kCore_x86_64_any:
1074 if ((core2 >= ArchSpec::kCore_x86_64_first && core2 <= ArchSpec::kCore_x86_64_last) || (core2 == ArchSpec::kCore_x86_64_any))
1075 return true;
1076 break;
1077
1078 case ArchSpec::kCore_ppc_any:
1079 if ((core2 >= ArchSpec::kCore_ppc_first && core2 <= ArchSpec::kCore_ppc_last) || (core2 == ArchSpec::kCore_ppc_any))
1080 return true;
1081 break;
1082
1083 case ArchSpec::kCore_ppc64_any:
1084 if ((core2 >= ArchSpec::kCore_ppc64_first && core2 <= ArchSpec::kCore_ppc64_last) || (core2 == ArchSpec::kCore_ppc64_any))
1085 return true;
1086 break;
1087
1088 case ArchSpec::eCore_arm_armv6m:
1089 if (!enforce_exact_match)
1090 {
1091 if (core2 == ArchSpec::eCore_arm_generic)
1092 return true;
1093 try_inverse = false;
1094 if (core2 == ArchSpec::eCore_arm_armv7)
1095 return true;
1096 if (core2 == ArchSpec::eCore_arm_armv6m)
1097 return true;
1098 }
1099 break;
1100
1101 case ArchSpec::kCore_hexagon_any:
1102 if ((core2 >= ArchSpec::kCore_hexagon_first && core2 <= ArchSpec::kCore_hexagon_last) || (core2 == ArchSpec::kCore_hexagon_any))
1103 return true;
1104 break;
1105
1106 case ArchSpec::eCore_arm_armv7em:
1107 if (!enforce_exact_match)
1108 {
1109 if (core2 == ArchSpec::eCore_arm_generic)
1110 return true;
1111 if (core2 == ArchSpec::eCore_arm_armv7m)
1112 return true;
1113 if (core2 == ArchSpec::eCore_arm_armv6m)
1114 return true;
1115 if (core2 == ArchSpec::eCore_arm_armv7)
1116 return true;
1117 try_inverse = true;
1118 }
1119 break;
1120
1121 case ArchSpec::eCore_arm_armv7m:
1122 if (!enforce_exact_match)
1123 {
1124 if (core2 == ArchSpec::eCore_arm_generic)
1125 return true;
1126 if (core2 == ArchSpec::eCore_arm_armv6m)
1127 return true;
1128 if (core2 == ArchSpec::eCore_arm_armv7)
1129 return true;
1130 if (core2 == ArchSpec::eCore_arm_armv7em)
1131 return true;
1132 try_inverse = true;
1133 }
1134 break;
1135
1136 case ArchSpec::eCore_arm_armv7f:
1137 case ArchSpec::eCore_arm_armv7k:
1138 case ArchSpec::eCore_arm_armv7s:
1139 if (!enforce_exact_match)
1140 {
1141 if (core2 == ArchSpec::eCore_arm_generic)
1142 return true;
1143 if (core2 == ArchSpec::eCore_arm_armv7)
1144 return true;
1145 try_inverse = false;
1146 }
1147 break;
1148
1149 case ArchSpec::eCore_x86_64_x86_64h:
1150 if (!enforce_exact_match)
1151 {
1152 try_inverse = false;
1153 if (core2 == ArchSpec::eCore_x86_64_x86_64)
1154 return true;
1155 }
1156 break;
1157
1158 case ArchSpec::eCore_arm_armv8:
1159 if (!enforce_exact_match)
1160 {
1161 if (core2 == ArchSpec::eCore_arm_arm64)
1162 return true;
1163 if (core2 == ArchSpec::eCore_arm_aarch64)
1164 return true;
1165 try_inverse = false;
1166 }
1167 break;
1168
1169 case ArchSpec::eCore_arm_aarch64:
1170 if (!enforce_exact_match)
1171 {
1172 if (core2 == ArchSpec::eCore_arm_arm64)
1173 return true;
1174 if (core2 == ArchSpec::eCore_arm_armv8)
1175 return true;
1176 try_inverse = false;
1177 }
1178 break;
1179
1180 case ArchSpec::eCore_arm_arm64:
1181 if (!enforce_exact_match)
1182 {
1183 if (core2 == ArchSpec::eCore_arm_aarch64)
1184 return true;
1185 if (core2 == ArchSpec::eCore_arm_armv8)
1186 return true;
1187 try_inverse = false;
1188 }
1189 break;
1190
1191 case ArchSpec::eCore_mips32:
1192 if (!enforce_exact_match)
1193 {
1194 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= ArchSpec::kCore_mips32_last)
1195 return true;
1196 try_inverse = false;
1197 }
1198 break;
1199
1200 case ArchSpec::eCore_mips32el:
1201 if (!enforce_exact_match)
1202 {
1203 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= ArchSpec::kCore_mips32el_last)
1204 return true;
1205 try_inverse = false;
1206 }
1207
1208 case ArchSpec::eCore_mips64:
1209 if (!enforce_exact_match)
1210 {
1211 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= ArchSpec::kCore_mips32_last)
1212 return true;
1213 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= ArchSpec::kCore_mips64_last)
1214 return true;
1215 try_inverse = false;
1216 }
1217
1218 case ArchSpec::eCore_mips64el:
1219 if (!enforce_exact_match)
1220 {
1221 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= ArchSpec::kCore_mips32el_last)
1222 return true;
1223 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= ArchSpec::kCore_mips64el_last)
1224 return true;
1225 try_inverse = false;
1226 }
1227
1228 case ArchSpec::eCore_mips64r2:
1229 case ArchSpec::eCore_mips64r3:
1230 case ArchSpec::eCore_mips64r5:
1231 if (!enforce_exact_match)
1232 {
1233 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
1234 return true;
1235 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
1236 return true;
1237 try_inverse = false;
1238 }
1239 break;
1240
1241 case ArchSpec::eCore_mips64r2el:
1242 case ArchSpec::eCore_mips64r3el:
1243 case ArchSpec::eCore_mips64r5el:
1244 if (!enforce_exact_match)
1245 {
1246 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
1247 return true;
1248 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
1249 return true;
1250 try_inverse = false;
1251 }
1252 break;
1253
1254 case ArchSpec::eCore_mips32r2:
1255 case ArchSpec::eCore_mips32r3:
1256 case ArchSpec::eCore_mips32r5:
1257 if (!enforce_exact_match)
1258 {
1259 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
1260 return true;
1261 }
1262 break;
1263
1264 case ArchSpec::eCore_mips32r2el:
1265 case ArchSpec::eCore_mips32r3el:
1266 case ArchSpec::eCore_mips32r5el:
1267 if (!enforce_exact_match)
1268 {
1269 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
1270 return true;
1271 }
1272 break;
1273
1274 case ArchSpec::eCore_mips32r6:
1275 if (!enforce_exact_match)
1276 {
1277 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1278 return true;
1279 }
1280 break;
1281
1282 case ArchSpec::eCore_mips32r6el:
1283 if (!enforce_exact_match)
1284 {
1285 if (core2 == ArchSpec::eCore_mips32el || core2 == ArchSpec::eCore_mips32r6el)
1286 return true;
1287 return true;
1288 }
1289 break;
1290
1291 case ArchSpec::eCore_mips64r6:
1292 if (!enforce_exact_match)
1293 {
1294 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1295 return true;
1296 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
1297 return true;
1298 }
1299 break;
1300
1301 case ArchSpec::eCore_mips64r6el:
1302 if (!enforce_exact_match)
1303 {
1304 if (core2 == ArchSpec::eCore_mips32el || core2 == ArchSpec::eCore_mips32r6el)
1305 return true;
1306 if (core2 == ArchSpec::eCore_mips64el || core2 == ArchSpec::eCore_mips64r6el)
1307 return true;
1308 }
1309 break;
1310
1311 default:
1312 break;
1313 }
1314 if (try_inverse)
1315 return cores_match (core2, core1, false, enforce_exact_match);
1316 return false;
1317 }
1318
1319 bool
operator <(const ArchSpec & lhs,const ArchSpec & rhs)1320 lldb_private::operator<(const ArchSpec& lhs, const ArchSpec& rhs)
1321 {
1322 const ArchSpec::Core lhs_core = lhs.GetCore ();
1323 const ArchSpec::Core rhs_core = rhs.GetCore ();
1324 return lhs_core < rhs_core;
1325 }
1326
1327 static void
StopInfoOverrideCallbackTypeARM(lldb_private::Thread & thread)1328 StopInfoOverrideCallbackTypeARM(lldb_private::Thread &thread)
1329 {
1330 // We need to check if we are stopped in Thumb mode in a IT instruction
1331 // and detect if the condition doesn't pass. If this is the case it means
1332 // we won't actually execute this instruction. If this happens we need to
1333 // clear the stop reason to no thread plans think we are stopped for a
1334 // reason and the plans should keep going.
1335 //
1336 // We do this because when single stepping many ARM processes, debuggers
1337 // often use the BVR/BCR registers that says "stop when the PC is not
1338 // equal to its current value". This method of stepping means we can end
1339 // up stopping on instructions inside an if/then block that wouldn't get
1340 // executed. By fixing this we can stop the debugger from seeming like
1341 // you stepped through both the "if" _and_ the "else" clause when source
1342 // level stepping because the debugger stops regardless due to the BVR/BCR
1343 // triggering a stop.
1344 //
1345 // It also means we can set breakpoints on instructions inside an an
1346 // if/then block and correctly skip them if we use the BKPT instruction.
1347 // The ARM and Thumb BKPT instructions are unconditional even when executed
1348 // in a Thumb IT block.
1349 //
1350 // If your debugger inserts software traps in ARM/Thumb code, it will
1351 // need to use 16 and 32 bit instruction for 16 and 32 bit thumb
1352 // instructions respectively. If your debugger inserts a 16 bit thumb
1353 // trap on top of a 32 bit thumb instruction for an opcode that is inside
1354 // an if/then, it will change the it/then to conditionally execute your
1355 // 16 bit trap and then cause your program to crash if it executes the
1356 // trailing 16 bits (the second half of the 32 bit thumb instruction you
1357 // partially overwrote).
1358
1359 RegisterContextSP reg_ctx_sp (thread.GetRegisterContext());
1360 if (reg_ctx_sp)
1361 {
1362 const uint32_t cpsr = reg_ctx_sp->GetFlags(0);
1363 if (cpsr != 0)
1364 {
1365 // Read the J and T bits to get the ISETSTATE
1366 const uint32_t J = Bit32(cpsr, 24);
1367 const uint32_t T = Bit32(cpsr, 5);
1368 const uint32_t ISETSTATE = J << 1 | T;
1369 if (ISETSTATE == 0)
1370 {
1371 // NOTE: I am pretty sure we want to enable the code below
1372 // that detects when we stop on an instruction in ARM mode
1373 // that is conditional and the condition doesn't pass. This
1374 // can happen if you set a breakpoint on an instruction that
1375 // is conditional. We currently will _always_ stop on the
1376 // instruction which is bad. You can also run into this while
1377 // single stepping and you could appear to run code in the "if"
1378 // and in the "else" clause because it would stop at all of the
1379 // conditional instructions in both.
1380 // In such cases, we really don't want to stop at this location.
1381 // I will check with the lldb-dev list first before I enable this.
1382 #if 0
1383 // ARM mode: check for condition on intsruction
1384 const addr_t pc = reg_ctx_sp->GetPC();
1385 Error error;
1386 // If we fail to read the opcode we will get UINT64_MAX as the
1387 // result in "opcode" which we can use to detect if we read a
1388 // valid opcode.
1389 const uint64_t opcode = thread.GetProcess()->ReadUnsignedIntegerFromMemory(pc, 4, UINT64_MAX, error);
1390 if (opcode <= UINT32_MAX)
1391 {
1392 const uint32_t condition = Bits32((uint32_t)opcode, 31, 28);
1393 if (ARMConditionPassed(condition, cpsr) == false)
1394 {
1395 // We ARE stopped on an ARM instruction whose condition doesn't
1396 // pass so this instruction won't get executed.
1397 // Regardless of why it stopped, we need to clear the stop info
1398 thread.SetStopInfo (StopInfoSP());
1399 }
1400 }
1401 #endif
1402 }
1403 else if (ISETSTATE == 1)
1404 {
1405 // Thumb mode
1406 const uint32_t ITSTATE = Bits32 (cpsr, 15, 10) << 2 | Bits32 (cpsr, 26, 25);
1407 if (ITSTATE != 0)
1408 {
1409 const uint32_t condition = Bits32(ITSTATE, 7, 4);
1410 if (ARMConditionPassed(condition, cpsr) == false)
1411 {
1412 // We ARE stopped in a Thumb IT instruction on an instruction whose
1413 // condition doesn't pass so this instruction won't get executed.
1414 // Regardless of why it stopped, we need to clear the stop info
1415 thread.SetStopInfo (StopInfoSP());
1416 }
1417 }
1418 }
1419 }
1420 }
1421 }
1422
1423 ArchSpec::StopInfoOverrideCallbackType
GetStopInfoOverrideCallback() const1424 ArchSpec::GetStopInfoOverrideCallback () const
1425 {
1426 const llvm::Triple::ArchType machine = GetMachine();
1427 if (machine == llvm::Triple::arm)
1428 return StopInfoOverrideCallbackTypeARM;
1429 return NULL;
1430 }
1431