1 /* $NetBSD: gemini_gmacreg.h,v 1.4 2024/05/13 00:25:23 msaitoh Exp $ */ 2 /*- 3 * Copyright (c) 2008 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas <matt@3am-software.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _ARM_GEMINI_GEMINI_GMACREG_H 32 #define _ARM_GEMINI_GEMINI_GMACREG_H 33 34 #define GMAC_GLOBAL_OFFSET 0x0000 35 #define GMAC_GLOBAL_SIZE 0x2000 36 37 #define GMAC_TOE_VERSION 0x0000 38 #define GMAC_TOE_DEVID(x) (((x) >> 4) & 0xfff) 39 #define GMAC_TOE_REVID(x) (((x) >> 0) & 0x00f) 40 41 #define GMAC_SWFREEQ_BASE 0x0004 42 #define GMAC_HWFREEQ_BASE 0x0008 43 44 #define FREEQ_SIZE 0x000f /* 2^n from 3 to 15 */ 45 46 #define GMAC_SKBSIZE 0x0010 47 #define SKB_SIZE_SET(hw,sw) (((hw) << 16) | (sw)) 48 49 #define GMAC_SWFREEQ_RWPTR 0x0014 50 #define GMAC_HWFREEQ_RWPTR 0x0018 51 52 #define GMAC_INT0_STATUS 0x0020 53 #define GMAC_INT0_MASK 0x0024 54 #define GMAC_INT0_SELECT 0x0028 55 56 #define INT0_TXDERR1 __BIT(31) /* GMAC1 AHB bus err while TX */ 57 #define INT0_TXPERR1 __BIT(30) /* GMAC1 TX descriptor error */ 58 #define INT0_TXDERR0 __BIT(29) /* GMAC0 AHB bus err while TX */ 59 #define INT0_TXPERR0 __BIT(28) /* GMAC0 TX descriptor error */ 60 #define INT0_RXDERR1 __BIT(27) /* GMAC1 AHB bus err while RX */ 61 #define INT0_RXPERR1 __BIT(26) /* GMAC1 RX descriptor error */ 62 #define INT0_RXDERR0 __BIT(25) /* GMAC0 AHB bus err while RX */ 63 #define INT0_RXPERR0 __BIT(24) /* GMAC0 RX descriptor error */ 64 #define INT0_SWTXQ15_FIN __BIT(23) /* GMAC1 SW TX queue 5 finish */ 65 #define INT0_SWTXQ14_FIN __BIT(22) /* GMAC1 SW TX queue 4 finish */ 66 #define INT0_SWTXQ13_FIN __BIT(21) /* GMAC1 SW TX queue 3 finish */ 67 #define INT0_SWTXQ12_FIN __BIT(20) /* GMAC1 SW TX queue 2 finish */ 68 #define INT0_SWTXQ11_FIN __BIT(19) /* GMAC1 SW TX queue 1 finish */ 69 #define INT0_SWTXQ10_FIN __BIT(18) /* GMAC1 SW TX queue 0 finish */ 70 #define INT0_SWTXQ1n_FIN(n) __BIT(18 + n) 71 #define INT0_SWTXQ1_FIN __BITS(18,23) 72 #define INT0_SWTXQ05_FIN __BIT(17) /* GMAC0 SW TX queue 5 finish */ 73 #define INT0_SWTXQ04_FIN __BIT(16) /* GMAC0 SW TX queue 4 finish */ 74 #define INT0_SWTXQ03_FIN __BIT(15) /* GMAC0 SW TX queue 3 finish */ 75 #define INT0_SWTXQ02_FIN __BIT(14) /* GMAC0 SW TX queue 2 finish */ 76 #define INT0_SWTXQ01_FIN __BIT(13) /* GMAC0 SW TX queue 1 finish */ 77 #define INT0_SWTXQ00_FIN __BIT(12) /* GMAC0 SW TX queue 0 finish */ 78 #define INT0_SWTXQ0n_FIN(n) __BIT(12 + n) 79 #define INT0_SWTXQ0_FIN __BITS(12,17) 80 #define INT0_SWTXQ_FIN __BITS(12,23) 81 #define INT0_SWTXQ15_EOF __BIT(11) /* GMAC1 SW TX queue 5 EOF */ 82 #define INT0_SWTXQ14_EOF __BIT(10) /* GMAC1 SW TX queue 4 EOF */ 83 #define INT0_SWTXQ13_EOF __BIT( 9) /* GMAC1 SW TX queue 3 EOF */ 84 #define INT0_SWTXQ12_EOF __BIT( 8) /* GMAC1 SW TX queue 2 EOF */ 85 #define INT0_SWTXQ11_EOF __BIT( 7) /* GMAC1 SW TX queue 1 EOF */ 86 #define INT0_SWTXQ10_EOF __BIT( 6) /* GMAC1 SW TX queue 0 EOF */ 87 #define INT0_SWTXQ1n_EOF(n) __BIT( 6 + n) 88 #define INT0_SWTXQ1_EOF __BITS(6,11) 89 #define INT0_SWTXQ05_EOF __BIT( 5) /* GMAC0 SW TX queue 5 EOF */ 90 #define INT0_SWTXQ04_EOF __BIT( 4) /* GMAC0 SW TX queue 4 EOF */ 91 #define INT0_SWTXQ03_EOF __BIT( 3) /* GMAC0 SW TX queue 3 EOF */ 92 #define INT0_SWTXQ02_EOF __BIT( 2) /* GMAC0 SW TX queue 2 EOF */ 93 #define INT0_SWTXQ01_EOF __BIT( 1) /* GMAC0 SW TX queue 1 EOF */ 94 #define INT0_SWTXQ00_EOF __BIT( 0) /* GMAC0 SW TX queue 0 EOF */ 95 #define INT0_SWTXQ0n_EOF(n) __BIT( n) 96 #define INT0_SWTXQ0_EOF __BITS(0,5) 97 #define INT0_SWTXQ_EOF __BITS(0,11) 98 99 #define INT0_TXDERR (INT0_TXDERR0|INT0_TXDERR1) 100 #define INT0_TXPERR (INT0_TXPERR0|INT0_TXPERR1) 101 #define INT0_RXDERR (INT0_RXDERR0|INT0_RXDERR1) 102 #define INT0_RXPERR (INT0_RXPERR0|INT0_RXPERR1) 103 104 #define INT0_SWTXQn_FIN(n) (INT0_SWTXQ0n_FIN(n)|INT0_SWTXQ1n_FIN(n)) 105 #define INT0_SWTXQn_EOF(n) (INT0_SWTXQ0n_EOF(n)|INT0_SWTXQ1n_EOF(n)) 106 107 #define INT0_GMAC0 \ 108 (INT0_TXDERR0|INT0_TXPERR0|INT0_RXDERR0|INT0_RXPERR0 \ 109 |INT0_SWTXQ05_FIN|INT0_SWTXQ04_FIN|INT0_SWTXQ03_FIN \ 110 |INT0_SWTXQ02_FIN|INT0_SWTXQ01_FIN|INT0_SWTXQ00_FIN \ 111 |INT0_SWTXQ05_EOF|INT0_SWTXQ04_EOF|INT0_SWTXQ03_EOF \ 112 |INT0_SWTXQ02_EOF|INT0_SWTXQ01_EOF|INT0_SWTXQ00_EOF) 113 #define INT0_GMAC1 \ 114 (INT0_TXDERR1|INT0_TXPERR1|INT0_RXDERR1|INT0_RXPERR1 \ 115 |INT0_SWTXQ15_FIN|INT0_SWTXQ14_FIN|INT0_SWTXQ13_FIN \ 116 |INT0_SWTXQ12_FIN|INT0_SWTXQ11_FIN|INT0_SWTXQ10_FIN \ 117 |INT0_SWTXQ15_EOF|INT0_SWTXQ14_EOF|INT0_SWTXQ13_EOF \ 118 |INT0_SWTXQ12_EOF|INT0_SWTXQ11_EOF|INT0_SWTXQ10_EOF) 119 120 #define GMAC_INT1_STATUS 0x0030 121 #define GMAC_INT1_MASK 0x0034 122 #define GMAC_INT1_SELECT 0x0038 123 124 #define INT1_TOE_IQ3_FULL __BIT(31) /* TOE Intr Queue3 Full */ 125 #define INT1_TOE_IQ2_FULL __BIT(30) /* TOE Intr Queue2 Full */ 126 #define INT1_TOE_IQ1_FULL __BIT(29) /* TOE Intr Queue1 Full */ 127 #define INT1_TOE_IQ0_FULL __BIT(28) /* TOE Intr Queue0 Full */ 128 #define INT1_TOE_IQ3_NONEMPTY __BIT(27) /* TOE Intr Queue3 !Empty */ 129 #define INT1_TOE_IQ2_NONEMPTY __BIT(26) /* TOE Intr Queue2 !Empty */ 130 #define INT1_TOE_IQ1_NONEMPTY __BIT(25) /* TOE Intr Queue1 !Empty */ 131 #define INT1_TOE_IQ0_NONEMPTY __BIT(24) /* TOE Intr Queue0 !Empty */ 132 #define INT1_HWTQ13_EOF __BIT(23) /* GMAC1 HW TX Queue3 EOF */ 133 #define INT1_HWTQ12_EOF __BIT(22) /* GMAC1 HW TX Queue2 EOF */ 134 #define INT1_HWTQ11_EOF __BIT(21) /* GMAC1 HW TX Queue1 EOF */ 135 #define INT1_HWTQ10_EOF __BIT(20) /* GMAC1 HW TX Queue0 EOF */ 136 #define INT1_HWTQ03_EOF __BIT(19) /* GMAC0 HW TX Queue3 EOF */ 137 #define INT1_HWTQ02_EOF __BIT(18) /* GMAC0 HW TX Queue2 EOF */ 138 #define INT1_HWTQ01_EOF __BIT(17) /* GMAC0 HW TX Queue1 EOF */ 139 #define INT1_HWTQ00_EOF __BIT(16) /* GMAC0 HW TX Queue0 EOF */ 140 #define INT1_CLASS_Q_EOF(n) __BIT((n)+2) /* Classfication Q[n] EOF */ 141 #define INT1_DEF_RXQ1_EOF __BIT(1) /* GMAC1 Default RX Queue EOF */ 142 #define INT1_DEF_RXQ0_EOF __BIT(0) /* GMAC0 Default RX Queue EOF */ 143 144 #define INT1_DEF_RXQ_EOF (INT1_DEF_RXQ0_EOF|INT1_DEF_RXQ1_EOF) 145 #define INT1_HWTQ3_EOF (INT1_HWTQ03_EOF|INT1_HWTQ13_EOF) 146 #define INT1_HWTQ2_EOF (INT1_HWTQ02_EOF|INT1_HWTQ12_EOF) 147 #define INT1_HWTQ1_EOF (INT1_HWTQ01_EOF|INT1_HWTQ11_EOF) 148 #define INT1_HWTQ0_EOF (INT1_HWTQ00_EOF|INT1_HWTQ10_EOF) 149 150 #define INT1_GMAC0 \ 151 (INT1_HWTQ03_EOF|INT1_HWTQ02_EOF|INT1_HWTQ01_EOF|INT1_HWTQ00_EOF \ 152 |INT1_DEF_RXQ0_EOF) 153 #define INT1_GMAC1 \ 154 (INT1_HWTQ13_EOF|INT1_HWTQ12_EOF|INT1_HWTQ11_EOF|INT1_HWTQ10_EOF \ 155 |INT1_DEF_RXQ1_EOF) 156 157 #define GMAC_INT2_STATUS 0x0040 158 #define GMAC_INT2_MASK 0x0044 159 #define GMAC_INT2_SELECT 0x0048 160 161 #define INT2_TOE_QFULL(n) __BIT((n)-32) /* TOE (32-63) Q[n] Full */ 162 #define INT2_GMAC0 0 163 #define INT2_GMAC1 0 164 165 #define GMAC_INT3_STATUS 0x0050 166 #define GMAC_INT3_MASK 0x0054 167 #define GMAC_INT3_SELECT 0x0058 168 169 #define INT3_TOE_QFULL(n) __BIT((n)) /* TOE (0-31) Q[n] Full */ 170 #define INT3_GMAC0 0 171 #define INT3_GMAC1 0 172 173 #define GMAC_INT4_STATUS 0x0060 174 #define GMAC_INT4_MASK 0x0064 175 #define GMAC_INT4_SELECT 0x0068 176 177 #define INT4_TX_FAIL0 __BIT(23) /* GMAC0 TX fail */ 178 #define INT4_TX_FAIL1 __BIT(23+8) /* GMAC1 TX fail */ 179 #define INT4_TX_FAIL (INT4_TX_FAIL0|INT4_TX_FAIL1) 180 #define INT4_MIB_HEMIWRAP0 __BIT(22) /* GMAC0 MIB counters 1/2 */ 181 #define INT4_MIB_HEMIWRAP1 __BIT(22+8) /* GMAC1 MIB counters 1/2 */ 182 #define INT4_MIB_HEMIWRAP (INT4_MIB_HEMIWRAP0|INT4_MIB_HEMIWRAP1) 183 #define INT4_RX_XON0 __BIT(21) /* GMAC0 RX Pause On */ 184 #define INT4_RX_XON1 __BIT(21+8) /* GMAC1 RX Pause On */ 185 #define INT4_RX_XON (INT4_RX_XON0|INT4_RX_XON1) 186 #define INT4_TX_XON0 __BIT(20) /* GMAC0 TX Pause On */ 187 #define INT4_TX_XON1 __BIT(20+8) /* GMAC1 TX Pause On */ 188 #define INT4_TX_XON (INT4_TX_XON0|INT4_TX_XON1) 189 #define INT4_RX_XOFF0 __BIT(19) /* GMAC0 RX Pause Off */ 190 #define INT4_RX_XOFF1 __BIT(19+8) /* GMAC1 RX Pause Off */ 191 #define INT4_RX_XOFF (INT4_RX_XOFF0|INT4_RX_XOFF1) 192 #define INT4_TX_XOFF0 __BIT(18) /* GMAC0 TX Pause Off */ 193 #define INT4_TX_XOFF1 __BIT(18+8) /* GMAC1 TX Pause Off */ 194 #define INT4_TX_XOFF (INT4_TX_XOFF0|INT4_TX_XOFF1) 195 #define INT4_RX_FIFO_OVRN0 __BIT(17) /* GMAC0 RX FIFO overrun */ 196 #define INT4_RX_FIFO_OVRN1 __BIT(17+8) /* GMAC1 RX FIFO overrun */ 197 #define INT4_RX_FIFO_OVRN (INT4_RX_FIFO_OVRN0|INT4_RX_FIFO_OVRN1) 198 #define INT4_RGMII_STSCHG0 __BIT(16) /* GMAC0 RGMII status change */ 199 #define INT4_RGMII_STSCHG1 __BIT(16+8) /* GMAC1 RGMII status change */ 200 #define INT4_RGMII_STSCHG (INT4_RGMII_STSCHG0|INT4_RGMII_STSCHG1) 201 #define INT4_CLASS_Q_FULL(n) __BIT((n)+2) /* Classification Q[n] Full */ 202 #define INT4_HW_FREEQ_EMPTY __BIT(1) /* HW Free Q empty */ 203 #define INT4_SW_FREEQ_EMPTY __BIT(0) /* SW Free Q empty */ 204 205 #define INT4_GMAC0 __BITS(16,23) 206 #define INT4_GMAC1 (__BITS(24,31)|INT4_HW_FREEQ_EMPTY) 207 208 #define GMAC_QFE_THRESHOLD 0x0070 209 #define QFE_TOEQ_THRESHOLD_MASK __BITS(24,31) 210 #define QFE_TOEQ_THRESHOLD_GET(x) (((x) >> 24) & 0xff) 211 #define QFE_TOEQ_THRESHOLD(x) (((x) & 0xff) << 24) 212 #define QFE_INTQ_THRESHOLD_MASK __BITS(16,23) 213 #define QFE_INTQ_THRESHOLD_GET(x) (((x) >> 16) & 0xff) 214 #define QFE_INTQ_THRESHOLD(x) (((x) & 0xff) << 16) 215 #define QFE_HWFQ_THRESHOLD_MASK __BITS(8,15) 216 #define QFE_HWFQ_THRESHOLD_GET(x) (((x) >> 8) & 0xff) 217 #define QFE_HWFQ_THRESHOLD(x) (((x) & 0xff) << 8) 218 #define QFE_SWFQ_THRESHOLD_MASK __BITS(0,7) 219 #define QFE_SWFQ_THRESHOLD_GET(x) (((x) >> 0) & 0xff) 220 #define QFE_SWFQ_THRESHOLD(x) (((x) & 0xff) << 0) 221 222 #define GMAC_NONTOE_QH_OFFSET 0x2000 223 #define GMAC_NONTOE_QH_SIZE 0x1000 224 225 #define GMAC_DEF_RXQn_BASE(n) (0x2000 + (n) * 4) 226 #define GMAC_DEF_RXQn_RWPTR(n) (0x2004 + (n) * 4) 227 #define GMAC_DEF_RXQ0_BASE 0x2000 228 #define GMAC_DEF_RXQ0_RWPTR 0x2004 229 #define GMAC_DEF_RXQ1_BASE 0x2008 230 #define GMAC_DEF_RXQ1_RWPTR 0x200c 231 232 #define GMAC_TOE_QH_OFFSET 0x3000 233 #define GMAC_TOE_QH_SIZE 0x1000 234 235 #define GMAC_VBIT_MEM_OFFSET 0x4000 236 #define GMAC_VBIT_MEM_SIZE 0x2000 237 238 #define GMAC_ABIT_MEM_OFFSET 0x6000 239 #define GMAC_ABIT_MEM_SIZE 0x2000 240 241 #define GMAC_PORT0_DMA_OFFSET 0x8000 242 #define GMAC_PORT_DMA_SIZE 0x2000 243 244 #define GMAC_DMAVR 0x0000 245 #define DMAVR_RXDMA_ENABLE __BIT(31) 246 #define DMAVR_TXDMA_ENABLE __BIT(30) 247 #define DMAVR_LOOPBACK __BIT(29) 248 #define DMAVR_DROP_SMALL_ACK __BIT(28) 249 #define DMAVR_EXTRABYTES_MASK __BITS(16,17) 250 #define DMAVR_EXTRABYTES_GET(x) (((x) >> 16) & DMAR_EXTRABYTES_MASK) 251 #define DMAVR_EXTRABYTES(x) (((x) & 3) << 16) 252 #define DMAVR_RXBURSTSIZE_MASK __BITS(10,11) 253 #define DMAVR_RXBURSTSIZE_GET(x) (((x) >> 10) & DMAR_BURSTSIZE_MASK) 254 #define DMAVR_RXBURSTSIZE(x) (((x) & 3) << 10) 255 #define DMAVR_RXBUSWIDTH_MASK __BITS(8,9) 256 #define DMAVR_RXBUSWIDTH_GET(x) (((x) >> 8) & DMAVR_BUSWIDTH_MASK) 257 #define DMAVR_RXBUSWIDTH(x) (((x) & 3) << 8) 258 #define DMAVR_TXBURSTSIZE_MASK __BITS(2,3) 259 #define DMAVR_TXBURSTSIZE_GET(x) (((x) >> 2) & DMAR_BURSTSIZE_MASK) 260 #define DMAVR_TXBURSTSIZE(x) (((x) & 3) << 2) 261 #define DMAVR_TXBUSWIDTH_MASK __BITS(0,1) 262 #define DMAVR_TXBUSWIDTH_GET(x) (((x) >> 0) & DMAVR_BUSWIDTH_MASK) 263 #define DMAVR_TXBUSWIDTH(x) (((x) & 3) << 0) 264 #define DMAVR_BURSTSIZE_4W 0 265 #define DMAVR_BURSTSIZE_8W 1 266 #define DMAVR_BURSTSIZE_16W 2 267 #define DMAVR_BURSTSIZE_32W 3 268 #define DMAVR_BURSTSIZE_MASK 3 269 #define DMAVR_BUSWIDTH_8BITS 0 270 #define DMAVR_BUSWIDTH_16BITS 2 271 #define DMAVR_BUSWIDTH_32BITS 3 272 #define DMAVR_BUSWIDTH_MASK 3 273 #define GMAC_TX_WEIGHTING_1 0x0004 274 #define GMAC_TX_WEIGHTING_2 0x0008 275 #define GMAC_SW_TX_Qn_RWPTR(n) (0x000c+(n)*4) 276 #define GMAC_SW_TX_Q0_RWPTR GMAC_SW_TX_Qn_RWPTR(0) 277 #define GMAC_SW_TX_Q1_RWPTR GMAC_SW_TX_Qn_RWPTR(1) 278 #define GMAC_SW_TX_Q2_RWPTR GMAC_SW_TX_Qn_RWPTR(2) 279 #define GMAC_SW_TX_Q3_RWPTR GMAC_SW_TX_Qn_RWPTR(3) 280 #define GMAC_SW_TX_Q4_RWPTR GMAC_SW_TX_Qn_RWPTR(4) 281 #define GMAC_SW_TX_Q5_RWPTR GMAC_SW_TX_Qn_RWPTR(5) 282 #define GMAC_HW_TX_Qn_RWPTR(n) (0x0024+(n)*4) 283 #define GMAC_HW_TX_Q0_RWPTR GMAC_HW_TX_Qn_RWPTR(0) 284 #define GMAC_HW_TX_Q1_RWPTR GMAC_HW_TX_Qn_RWPTR(1) 285 #define GMAC_HW_TX_Q2_RWPTR GMAC_HW_TX_Qn_RWPTR(2) 286 #define GMAC_HW_TX_Q3_RWPTR GMAC_HW_TX_Qn_RWPTR(3) 287 288 #define GMAC_DMA_TX_1ST_DESC 0x0038 289 #define GMAC_DMA_TX_CUR_DESC 0x003c 290 #define GMAC_DMA_TX_DESC(n) (0x0040+(n)*4) 291 #define GMAC_DMA_TX_DESC0 GMAC_DMA_TX_DESC(0) 292 #define GMAC_DMA_TX_DESC1 GMAC_DMA_TX_DESC(1) 293 #define GMAC_DMA_TX_DESC2 GMAC_DMA_TX_DESC(2) 294 #define GMAC_DMA_TX_DESC3 GMAC_DMA_TX_DESC(3) 295 #define GMAC_SW_TX_Q_BASE 0x0050 296 #define GMAC_HW_TX_Q_BASE 0x0054 297 298 #define GMAC_DMA_RX_1ST_DESC 0x0058 299 #define GMAC_DMA_RX_CUR_DESC 0x005c 300 #define GMAC_DMA_RX_DESC(n) (0x0060+(n)*4) 301 #define GMAC_DMA_RX_DESC0 GMAC_DMA_RX_DESC(0) 302 #define GMAC_DMA_RX_DESC1 GMAC_DMA_RX_DESC(1) 303 #define GMAC_DMA_RX_DESC2 GMAC_DMA_RX_DESC(2) 304 #define GMAC_DMA_RX_DESC3 GMAC_DMA_RX_DESC(3) 305 306 #define GMAC_HEE_AO_EL0 0x0070 /* HashEngineEna/ActionOff/EntryLen */ 307 #define GMAC_HEE_AO_EL1 0x0070 /* HashEngineEna/ActionOff/EntryLen */ 308 309 #define GMAC_RULEMATCH0(n) (0x0078+(n)*12) 310 #define GMAC_RULEMATCH1(n) (0x0080+(n)*12) 311 #define GMAC_RULEMATCH2(n) (0x0084+(n)*12) 312 313 #define GMAC_SUPPORTEDPROTO(n) (0x00a8+(n)*4) 314 #define GMAC_HRT_AHB_WEIGHTING 0x00c8 /* Hash/Rx/Tx AHB Weighting */ 315 316 #define HRT_AHB_TQDV_START __BITS(20,24) 317 #define HRT_AHB_RX_PREREQ __BITS(15,19) 318 #define HRT_AHB_TX_WEIGHT __BITS(10,14) 319 #define HRT_AHB_RX_WEIGHT __BITS(5,9) 320 #define HRT_AHB_HASH_WEIGHT __BITS(0,4) 321 322 #define GMAC_PORTn_DMA_OFFSET(n) (0x8000 + (n) * 0x4000) 323 #define GMAC_PORTn_GMAC_OFFSET(n) (0xa000 + (n) * 0x4000) 324 #define GMAC_PORTn_DMA_SIZE 0x2000 325 #define GMAC_PORTn_GMAC_SIZE 0x2000 326 327 #define GMAC_STA_ADD0 0x0000 328 #define GMAC_STA_ADD1 0x0004 329 #define GMAC_STA_ADD2 0x0008 330 331 #define GMAC_RX_FILTER 0x000c 332 #define RXFILTER_PROMISC_ALL __BIT(4) 333 #define RXFILTER_PROMISC __BIT(3) 334 #define RXFILTER_BROADCAST __BIT(2) 335 #define RXFILTER_MULTICAST __BIT(1) 336 #define RXFILTER_UNICAST __BIT(0) 337 338 #define GMAC_MCAST_FILTER0 0x0010 339 #define GMAC_MCAST_FILTER1 0x0014 340 341 #define GMAC_CONFIG0 0x0018 342 343 #define CONFIG0_PORT1_CLASSIFY_QCHECK_EN __BIT(29) 344 #define CONFIG0_PORT0_CLASSIFY_QCHECK_EN __BIT(28) 345 #define CONFIG0_PORT1_TOE_ALMOSTFULL_EN __BIT(27) 346 #define CONFIG0_PORT0_TOE_ALMOSTFULL_EN __BIT(26) 347 #define CONFIG0_PORT1_RX_HW_QCHECK_EN __BIT(25) 348 #define CONFIG0_PORT0_RX_HW_QCHECK_EN __BIT(24) 349 #define CONFIG0_RX_ER_DETECTING_INDEX_DIS __BIT(23) 350 #define CONFIG0_IPV6_STRICT_ORDER __BIT(22) 351 #define CONFIG0_INVERSE_RXC_RGMII __BIT(21) 352 #define CONFIG0_R_LATCHED_MMII __BIT(20) 353 #define CONFIG0_VLAN_TAG_REMOVAL __BIT(19) 354 #define CONFIG0_IPV6_RX_CHECKSUM_ENABLE __BIT(18) 355 #define CONFIG0_IPV4_RX_CHECKSUM_ENABLE __BIT(17) 356 #define CONFIG0_RGMII_INBAND_STATUS_ENABLE __BIT(16) 357 #define CONFIG0_TX_FLOWCTL_ENABLE __BIT(15) 358 #define CONFIG0_RX_FLOWCTL_ENABLE __BIT(14) 359 #define CONFIG0_SIM_TEST __BIT(13) 360 #define CONFIG0_BACKOFF_MASK __BITS(11,12) 361 #define CONFIG0_BACKOFF_GET(x) (((x) >> 11) & CONFIG0_BACKOFF_MASK) 362 #define CONFIG0_BACKOFF(x) (((x) & CONFIG0_BACKOFF_MASK) << 11) 363 #define CONFIG0_BACKOFF_NORMAL 0 364 #define CONFIG0_BACKOFF_2X 1 365 #define CONFIG0_BACKOFF_4X 2 366 #define CONFIG0_BACKOFF_DISABLE 3 367 #define CONFIG0_MAXLEN_MASK __BITS(8,10) 368 #define CONFIG0_MAXLEN_GET(x) (((x) >> 8) & CONFIG0_MAXLEN_MASK) 369 #define CONFIG0_MAXLEN(x) (((x) & CONFIG0_MAXLEN_MASK) << 8) 370 #define CONFIG0_MAXLEN_1536 0 371 #define CONFIG0_MAXLEN_1518 1 372 #define CONFIG0_MAXLEN_1522 2 373 #define CONFIG0_MAXLEN_1548 3 374 #define CONFIG0_MAXLEN_JUMBO 4 375 #define CONFIG0_IFG_ADJUST_MASK __BITS(4,7) 376 #define CONFIG0_IFG_ADJUST_GET(x) (((x) >> 4) & CONFIG0_IFG_ADJUST_MASK) 377 #define CONFIG0_IFG_ADJUST(x) (((x) & CONFIG0_IFG_ADJUST_MASK) << 4) 378 #define CONFIG0_DROP_16COLL_ENABLE __BIT(3) 379 #define CONFIG0_LOOPBACK __BIT(2) 380 #define CONFIG0_RX_DISABLE __BIT(1) 381 #define CONFIG0_TX_DISABLE __BIT(0) 382 383 #define GMAC_STATUS 0x002c 384 #define STATUS_PHYMODE_MASK __BITS(5,6) 385 #define STATUS_PHYMODE_MII (0 << 5) 386 #define STATUS_PHYMODE_GMII (1 << 5) 387 #define STATUS_PHYMODE_RGMII_A (2 << 5) 388 #define STATUS_PHYMODE_RGMII_B (3 << 5) 389 #define STATUS_DUPLEX_FULL __BIT(3) 390 #define STATUS_SPEED_MASK __BITS(1,2) 391 #define STATUS_SPEED_10M (0 << 1) 392 #define STATUS_SPEED_100M (1 << 1) 393 #define STATUS_SPEED_1000M (2 << 1) 394 #define STATUS_LINK_ON __BIT(0) 395 396 #define DESC0_DROP __BIT(31) 397 #define DESC0_DERR __BIT(30) 398 #define DESC0_PERR __BIT(29) 399 #define DESC0_STATUS __BITS(22, 28) 400 #define DESC0_DESC_CNT __BITS(16, 21) 401 #define DESC0_BUF_SIZE __BITS(0, 15) 402 403 #define DESC0_RXCSUMSTS_GET(x) (((x) >> 26) & 7) 404 #define DESC0_RXCSUMSTS_IPALL_OK 0 /* IP Hdr OK & TCP/UDP OK */ 405 #define DESC0_RXCSUMSTS_IPHDR_OK 1 /* IP Hdr OK (!TCP/UDP) */ 406 #define DESC0_RXCSUMSTS_NOTIP 2 /* Not an IP PKT */ 407 #define DESC0_RXCSUMSTS_INVALID 3 /* Invalid PKT */ 408 #define DESC0_RXCSUMSTS__RSVR4 4 409 #define DESC0_RXCSUMSTS_IPHDR_BAD 5 /* IP Hdr BAD */ 410 #define DESC0_RXCSUMSTS_IPPAY_BAD 6 /* IP Hdr OK, TDP/UDP BAD */ 411 #define DESC0_RXCSUMSTS__RSVR7 7 412 413 #define DESC0_RXSTS_GET(x) (((x) >> 22) & 15) 414 #define DESC0_RXSTS_GOOD 0 /* good frame */ 415 #define DESC0_RXSTS_LONG 1 /* long frame (CRC OK) */ 416 #define DESC0_RXSTS_RUNT 2 /* runt frame */ 417 #define DESC0_RXSTS_NOSFD 3 /* SFD not found */ 418 #define DESC0_RXSTS_BADCRC 4 /* bad CRC */ 419 #define DESC0_RXSTS_LONG_BADCRC 5 /* Too long with bad CRC */ 420 #define DESC0_RXSTS_BADALIGN 6 /* Alignment error */ 421 #define DESC0_RXSTS_ALLBAD 7 /* Long & bad CRC & Align Err */ 422 #define DESC0_RXSTS_PAUSE 8 /* Pause Frame received */ 423 #define DESC0_RXSTS_RX_ER 9 /* RX_ER Error detected */ 424 #define DESC0_RXSTS_ADDR_FILTER 10 /* DA is not matched */ 425 #define DESC0_RXSTS_OVERRUN 11 /* RX FIFO Overrun */ 426 427 #define DESC0_TXSTS_OK __BIT(22) /* TX successful */ 428 429 #define DESC1_RX_SWID __BITS(16, 31) 430 #define DESC1_TX_FLAG __BITS(16, 31) 431 #define DESC1_BUFLEN __BITS(0, 15) 432 433 #define DESC1_TX_IPLEN_FIXED __BITS(22) /* IPLEN is fixed */ 434 #define DESC1_TX_TSS_BYPASS __BITS(21) /* TSS Bypass */ 435 #define DESC1_TX_UDP_CSUM_EN __BITS(20) /* Calc UDP CSUM */ 436 #define DESC1_TX_TCP_CSUM_EN __BITS(19) /* Calc TCP CSUM */ 437 #define DESC1_TX_IPV6_EN __BITS(18) /* Calc UDP CSUM */ 438 #define DESC1_TX_IPV4_CSUM_EN __BITS(17) /* Calc IP HDR CSUM */ 439 #define DESC1_TX_SEG_OFFLOAD_EN __BITS(16) /* TSS Bypass */ 440 441 #define DESC2_BUFADDR __BITS(2,31) 442 443 #define DESC3_SOF __BIT(31) 444 #define DESC3_EOF __BIT(30) 445 #define DESC3_EOFIE __BIT(29) 446 447 #define DESC3_RX_CTL __BIT(28) 448 #define DESC3_RX_OSQ __BIT(27) 449 #define DESC3_RX_OPT __BIT(26) 450 #define DESC3_RX_ABN __BIT(25) 451 #define DESC3_RX_DACK __BIT(24) 452 #define DESC3_RX_L3_OFF __BITS(16, 32) 453 #define DESC3_RX_L4_OFF __BITS(8, 15) 454 #define DESC3_RX_L7_OFF __BITS(0, 7) 455 456 #define DESC3_TX_TSS_MTU __BITS(0, 10) 457 458 typedef struct { 459 volatile uint32_t d_desc0; 460 volatile uint32_t d_desc1; 461 uint32_t d_bufaddr; 462 volatile uint32_t d_desc3; 463 } gmac_desc_t; 464 465 #endif /* _ARM_GEMINI_GEMINI_GMACREG_H */ 466