1 /* $MirOS: src/gnu/usr.bin/binutils/gas/config/tc-i386.h,v 1.5 2005/07/07 16:22:50 tg Exp $ */ 2 3 /* tc-i386.h -- Header file for tc-i386.c 4 Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 5 2001, 2002, 2003, 2004 6 Free Software Foundation, Inc. 7 8 This file is part of GAS, the GNU Assembler. 9 10 GAS is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2, or (at your option) 13 any later version. 14 15 GAS is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GAS; see the file COPYING. If not, write to the Free 22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 23 02110-1301, USA. */ 24 25 #ifndef TC_I386 26 #define TC_I386 1 27 28 #ifndef BFD_ASSEMBLER 29 #error So, do you know what you are doing? 30 #endif 31 32 #ifdef ANSI_PROTOTYPES 33 struct fix; 34 #endif 35 36 #define TARGET_BYTES_BIG_ENDIAN 0 37 38 #define TARGET_ARCH bfd_arch_i386 39 #define TARGET_MACH (i386_mach ()) 40 extern unsigned long i386_mach (void); 41 42 #ifdef TE_FreeBSD 43 #define AOUT_TARGET_FORMAT "a.out-i386-freebsd" 44 #endif 45 #ifdef TE_NetBSD 46 #define AOUT_TARGET_FORMAT "a.out-i386-netbsd" 47 #endif 48 #ifdef TE_386BSD 49 #define AOUT_TARGET_FORMAT "a.out-i386-bsd" 50 #endif 51 #ifdef TE_LINUX 52 #define AOUT_TARGET_FORMAT "a.out-i386-linux" 53 #endif 54 #ifdef TE_Mach 55 #define AOUT_TARGET_FORMAT "a.out-mach3" 56 #endif 57 #ifdef TE_DYNIX 58 #define AOUT_TARGET_FORMAT "a.out-i386-dynix" 59 #endif 60 #ifndef AOUT_TARGET_FORMAT 61 #define AOUT_TARGET_FORMAT "a.out-i386" 62 #endif 63 64 #ifdef TE_FreeBSD 65 #define ELF_TARGET_FORMAT "elf32-i386-freebsd" 66 #elif defined (TE_VXWORKS) 67 #define ELF_TARGET_FORMAT "elf32-i386-vxworks" 68 #endif 69 70 #ifndef ELF_TARGET_FORMAT 71 #define ELF_TARGET_FORMAT "elf32-i386" 72 #endif 73 74 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 75 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 76 extern const char *i386_target_format PARAMS ((void)); 77 #define TARGET_FORMAT i386_target_format () 78 #else 79 #ifdef OBJ_ELF 80 #define TARGET_FORMAT ELF_TARGET_FORMAT 81 #endif 82 #ifdef OBJ_AOUT 83 #define TARGET_FORMAT AOUT_TARGET_FORMAT 84 #endif 85 #endif 86 87 #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)) 88 #define md_end i386_elf_emit_arch_note 89 extern void i386_elf_emit_arch_note PARAMS ((void)); 90 #endif 91 92 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0 93 94 #define LOCAL_LABELS_FB 1 95 96 extern const char extra_symbol_chars[]; 97 #define tc_symbol_chars extra_symbol_chars 98 99 #define MAX_OPERANDS 3 /* max operands per insn */ 100 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */ 101 #define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */ 102 103 /* Prefixes will be emitted in the order defined below. 104 WAIT_PREFIX must be the first prefix since FWAIT is really is an 105 instruction, and so must come before any prefixes. */ 106 #define WAIT_PREFIX 0 107 #define LOCKREP_PREFIX 1 108 #define ADDR_PREFIX 2 109 #define DATA_PREFIX 3 110 #define SEG_PREFIX 4 111 #define REX_PREFIX 5 /* must come last. */ 112 #define MAX_PREFIXES 6 /* max prefixes per opcode */ 113 114 /* we define the syntax here (modulo base,index,scale syntax) */ 115 #define REGISTER_PREFIX '%' 116 #define IMMEDIATE_PREFIX '$' 117 #define ABSOLUTE_PREFIX '*' 118 119 #define TWO_BYTE_OPCODE_ESCAPE 0x0f 120 #define NOP_OPCODE (char) 0x90 121 122 /* register numbers */ 123 #define EBP_REG_NUM 5 124 #define ESP_REG_NUM 4 125 126 /* modrm_byte.regmem for twobyte escape */ 127 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM 128 /* index_base_byte.index for no index register addressing */ 129 #define NO_INDEX_REGISTER ESP_REG_NUM 130 /* index_base_byte.base for no base register addressing */ 131 #define NO_BASE_REGISTER EBP_REG_NUM 132 #define NO_BASE_REGISTER_16 6 133 134 /* these are the instruction mnemonic suffixes. */ 135 #define WORD_MNEM_SUFFIX 'w' 136 #define BYTE_MNEM_SUFFIX 'b' 137 #define SHORT_MNEM_SUFFIX 's' 138 #define LONG_MNEM_SUFFIX 'l' 139 #define QWORD_MNEM_SUFFIX 'q' 140 /* Intel Syntax */ 141 #define LONG_DOUBLE_MNEM_SUFFIX 'x' 142 143 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ 144 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ 145 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) 146 147 #define END_OF_INSN '\0' 148 149 typedef struct 150 { 151 /* instruction name sans width suffix ("mov" for movl insns) */ 152 char *name; 153 154 /* how many operands */ 155 unsigned int operands; 156 157 /* base_opcode is the fundamental opcode byte without optional 158 prefix(es). */ 159 unsigned int base_opcode; 160 161 /* extension_opcode is the 3 bit extension for group <n> insns. 162 This field is also used to store the 8-bit opcode suffix for the 163 AMD 3DNow! instructions. 164 If this template has no extension opcode (the usual case) use None */ 165 unsigned int extension_opcode; 166 #define None 0xffff /* If no extension_opcode is possible. */ 167 168 /* cpu feature flags */ 169 unsigned int cpu_flags; 170 #define Cpu086 0x1 /* Any old cpu will do, 0 does the same */ 171 #define Cpu186 0x2 /* i186 or better required */ 172 #define Cpu286 0x4 /* i286 or better required */ 173 #define Cpu386 0x8 /* i386 or better required */ 174 #define Cpu486 0x10 /* i486 or better required */ 175 #define Cpu586 0x20 /* i585 or better required */ 176 #define Cpu686 0x40 /* i686 or better required */ 177 #define CpuP4 0x80 /* Pentium4 or better required */ 178 #define CpuK6 0x100 /* AMD K6 or better required*/ 179 #define CpuAthlon 0x200 /* AMD Athlon or better required*/ 180 #define CpuSledgehammer 0x400 /* Sledgehammer or better required */ 181 #define CpuMMX 0x800 /* MMX support required */ 182 #define CpuMMX2 0x1000 /* extended MMX support (with SSE or 3DNow!Ext) required */ 183 #define CpuSSE 0x2000 /* Streaming SIMD extensions required */ 184 #define CpuSSE2 0x4000 /* Streaming SIMD extensions 2 required */ 185 #define Cpu3dnow 0x8000 /* 3dnow! support required */ 186 #define Cpu3dnowA 0x10000 /* 3dnow!Extensions support required */ 187 #define CpuSSE3 0x20000 /* Streaming SIMD extensions 3 required */ 188 #define CpuPNI CpuSSE3 /* Prescott New Instructions required */ 189 #define CpuPadLock 0x40000 /* VIA PadLock required */ 190 #define CpuSVME 0x80000 /* AMD Secure Virtual Machine Ext-s required */ 191 192 /* These flags are set by gas depending on the flag_code. */ 193 #define Cpu64 0x4000000 /* 64bit support required */ 194 #define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ 195 196 /* The default value for unknown CPUs - enable all features to avoid problems. */ 197 #define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \ 198 |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI \ 199 |Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME) 200 201 /* the bits in opcode_modifier are used to generate the final opcode from 202 the base_opcode. These bits also are used to detect alternate forms of 203 the same instruction */ 204 unsigned int opcode_modifier; 205 206 /* opcode_modifier bits: */ 207 #define W 0x1 /* set if operands can be words or dwords 208 encoded the canonical way */ 209 #define D 0x2 /* D = 0 if Reg --> Regmem; 210 D = 1 if Regmem --> Reg: MUST BE 0x2 */ 211 #define Modrm 0x4 212 #define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */ 213 #define ShortForm 0x10 /* register is in low 3 bits of opcode */ 214 #define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */ 215 #define Jump 0x40 /* special case for jump insns. */ 216 #define JumpDword 0x80 /* call and jump */ 217 #define JumpByte 0x100 /* loop and jecxz */ 218 #define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */ 219 #define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */ 220 #define Seg2ShortForm 0x800 /* encoding of load segment reg insns */ 221 #define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */ 222 #define Size16 0x2000 /* needs size prefix if in 32-bit mode */ 223 #define Size32 0x4000 /* needs size prefix if in 16-bit mode */ 224 #define Size64 0x8000 /* needs size prefix if in 16-bit mode */ 225 #define IgnoreSize 0x10000 /* instruction ignores operand size prefix */ 226 #define DefaultSize 0x20000 /* default insn size depends on mode */ 227 #define No_bSuf 0x40000 /* b suffix on instruction illegal */ 228 #define No_wSuf 0x80000 /* w suffix on instruction illegal */ 229 #define No_lSuf 0x100000 /* l suffix on instruction illegal */ 230 #define No_sSuf 0x200000 /* s suffix on instruction illegal */ 231 #define No_qSuf 0x400000 /* q suffix on instruction illegal */ 232 #define No_xSuf 0x800000 /* x suffix on instruction illegal */ 233 #define FWait 0x1000000 /* instruction needs FWAIT */ 234 #define IsString 0x2000000 /* quick test for string instructions */ 235 #define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */ 236 #define IsPrefix 0x8000000 /* opcode is a prefix */ 237 #define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */ 238 #define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */ 239 #define Rex64 0x40000000 /* instruction require Rex64 prefix. */ 240 #define Ugh 0x80000000 /* deprecated fp insn, gets a warning */ 241 242 /* operand_types[i] describes the type of operand i. This is made 243 by OR'ing together all of the possible type masks. (e.g. 244 'operand_types[i] = Reg|Imm' specifies that operand i can be 245 either a register or an immediate operand. */ 246 unsigned int operand_types[3]; 247 248 /* operand_types[i] bits */ 249 /* register */ 250 #define Reg8 0x1 /* 8 bit reg */ 251 #define Reg16 0x2 /* 16 bit reg */ 252 #define Reg32 0x4 /* 32 bit reg */ 253 #define Reg64 0x8 /* 64 bit reg */ 254 /* immediate */ 255 #define Imm8 0x10 /* 8 bit immediate */ 256 #define Imm8S 0x20 /* 8 bit immediate sign extended */ 257 #define Imm16 0x40 /* 16 bit immediate */ 258 #define Imm32 0x80 /* 32 bit immediate */ 259 #define Imm32S 0x100 /* 32 bit immediate sign extended */ 260 #define Imm64 0x200 /* 64 bit immediate */ 261 #define Imm1 0x400 /* 1 bit immediate */ 262 /* memory */ 263 #define BaseIndex 0x800 264 /* Disp8,16,32 are used in different ways, depending on the 265 instruction. For jumps, they specify the size of the PC relative 266 displacement, for baseindex type instructions, they specify the 267 size of the offset relative to the base register, and for memory 268 offset instructions such as `mov 1234,%al' they specify the size of 269 the offset relative to the segment base. */ 270 #define Disp8 0x1000 /* 8 bit displacement */ 271 #define Disp16 0x2000 /* 16 bit displacement */ 272 #define Disp32 0x4000 /* 32 bit displacement */ 273 #define Disp32S 0x8000 /* 32 bit signed displacement */ 274 #define Disp64 0x10000 /* 64 bit displacement */ 275 /* specials */ 276 #define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */ 277 #define ShiftCount 0x40000 /* register to hold shift cound = cl */ 278 #define Control 0x80000 /* Control register */ 279 #define Debug 0x100000 /* Debug register */ 280 #define Test 0x200000 /* Test register */ 281 #define FloatReg 0x400000 /* Float register */ 282 #define FloatAcc 0x800000 /* Float stack top %st(0) */ 283 #define SReg2 0x1000000 /* 2 bit segment register */ 284 #define SReg3 0x2000000 /* 3 bit segment register */ 285 #define Acc 0x4000000 /* Accumulator %al or %ax or %eax */ 286 #define JumpAbsolute 0x8000000 287 #define RegMMX 0x10000000 /* MMX register */ 288 #define RegXMM 0x20000000 /* XMM registers in PIII */ 289 #define EsSeg 0x40000000 /* String insn operand with fixed es segment */ 290 291 /* InvMem is for instructions with a modrm byte that only allow a 292 general register encoding in the i.tm.mode and i.tm.regmem fields, 293 eg. control reg moves. They really ought to support a memory form, 294 but don't, so we add an InvMem flag to the register operand to 295 indicate that it should be encoded in the i.tm.regmem field. */ 296 #define InvMem 0x80000000 297 298 #define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */ 299 #define WordReg (Reg16|Reg32|Reg64) 300 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) 301 #define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */ 302 #define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */ 303 #define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */ 304 #define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */ 305 /* The following aliases are defined because the opcode table 306 carefully specifies the allowed memory types for each instruction. 307 At the moment we can only tell a memory reference size by the 308 instruction suffix, so there's not much point in defining Mem8, 309 Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use 310 the suffix directly to check memory operands. */ 311 #define LLongMem AnyMem /* 64 bits (or more) */ 312 #define LongMem AnyMem /* 32 bit memory ref */ 313 #define ShortMem AnyMem /* 16 bit memory ref */ 314 #define WordMem AnyMem /* 16 or 32 bit memory ref */ 315 #define ByteMem AnyMem /* 8 bit memory ref */ 316 } 317 template; 318 319 /* 320 'templates' is for grouping together 'template' structures for opcodes 321 of the same name. This is only used for storing the insns in the grand 322 ole hash table of insns. 323 The templates themselves start at START and range up to (but not including) 324 END. 325 */ 326 typedef struct 327 { 328 const template *start; 329 const template *end; 330 } 331 templates; 332 333 /* these are for register name --> number & type hash lookup */ 334 typedef struct 335 { 336 char *reg_name; 337 unsigned int reg_type; 338 unsigned int reg_flags; 339 #define RegRex 0x1 /* Extended register. */ 340 #define RegRex64 0x2 /* Extended 8 bit register. */ 341 unsigned int reg_num; 342 } 343 reg_entry; 344 345 typedef struct 346 { 347 char *seg_name; 348 unsigned int seg_prefix; 349 } 350 seg_entry; 351 352 /* 386 operand encoding bytes: see 386 book for details of this. */ 353 typedef struct 354 { 355 unsigned int regmem; /* codes register or memory operand */ 356 unsigned int reg; /* codes register operand (or extended opcode) */ 357 unsigned int mode; /* how to interpret regmem & reg */ 358 } 359 modrm_byte; 360 361 /* x86-64 extension prefix. */ 362 typedef int rex_byte; 363 #define REX_OPCODE 0x40 364 365 /* Indicates 64 bit operand size. */ 366 #define REX_MODE64 8 367 /* High extension to reg field of modrm byte. */ 368 #define REX_EXTX 4 369 /* High extension to SIB index field. */ 370 #define REX_EXTY 2 371 /* High extension to base field of modrm or SIB, or reg field of opcode. */ 372 #define REX_EXTZ 1 373 374 /* 386 opcode byte to code indirect addressing. */ 375 typedef struct 376 { 377 unsigned base; 378 unsigned index; 379 unsigned scale; 380 } 381 sib_byte; 382 383 /* x86 arch names and features */ 384 typedef struct 385 { 386 const char *name; /* arch name */ 387 unsigned int flags; /* cpu feature flags */ 388 } 389 arch_entry; 390 391 /* The name of the global offset table generated by the compiler. Allow 392 this to be overridden if need be. */ 393 #ifndef GLOBAL_OFFSET_TABLE_NAME 394 #define GLOBAL_OFFSET_TABLE_NAME \ 395 (this_format->dfl_leading_underscore \ 396 ? "__GLOBAL_OFFSET_TABLE_" \ 397 : "_GLOBAL_OFFSET_TABLE_") 398 #endif 399 400 #ifndef LEX_AT 401 #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES) 402 extern void x86_cons PARAMS ((expressionS *, int)); 403 404 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP) 405 extern void x86_cons_fix_new 406 PARAMS ((fragS *, unsigned int, unsigned int, expressionS *)); 407 #endif 408 409 #ifdef TE_PE 410 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_pe_cons_fix_new(FRAG, OFF, LEN, EXP) 411 extern void x86_pe_cons_fix_new 412 PARAMS ((fragS *, unsigned int, unsigned int, expressionS *)); 413 #endif 414 415 #define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */ 416 417 #define NO_RELOC BFD_RELOC_NONE 418 419 void i386_validate_fix PARAMS ((struct fix *)); 420 #define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX) 421 422 #define tc_fix_adjustable(X) tc_i386_fix_adjustable(X) 423 extern int tc_i386_fix_adjustable PARAMS ((struct fix *)); 424 425 /* Values passed to md_apply_fix don't include the symbol value. */ 426 #define MD_APPLY_SYM_VALUE(FIX) 0 427 428 /* ELF wants external syms kept, as does PE COFF. */ 429 #if defined (TE_PE) && defined (STRICT_PE_FORMAT) 430 #define EXTERN_FORCE_RELOC \ 431 (OUTPUT_FLAVOR == bfd_target_elf_flavour \ 432 || OUTPUT_FLAVOR == bfd_target_coff_flavour) 433 #else 434 #define EXTERN_FORCE_RELOC \ 435 (OUTPUT_FLAVOR == bfd_target_elf_flavour) 436 #endif 437 438 /* This expression evaluates to true if the relocation is for a local 439 object for which we still want to do the relocation at runtime. 440 False if we are willing to perform this relocation while building 441 the .o file. GOTOFF does not need to be checked here because it is 442 not pcrel. I am not sure if some of the others are ever used with 443 pcrel, but it is easier to be safe than sorry. */ 444 445 #define TC_FORCE_RELOCATION_LOCAL(FIX) \ 446 (!(FIX)->fx_pcrel \ 447 || (FIX)->fx_plt \ 448 || (FIX)->fx_r_type == BFD_RELOC_386_PLT32 \ 449 || (FIX)->fx_r_type == BFD_RELOC_386_GOT32 \ 450 || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC \ 451 || TC_FORCE_RELOCATION (FIX)) 452 453 #define md_operand(x) 454 455 extern const struct relax_type md_relax_table[]; 456 #define TC_GENERIC_RELAX_TABLE md_relax_table 457 458 extern int optimize_align_code; 459 460 #define md_do_align(n, fill, len, max, around) \ 461 if ((n) \ 462 && !need_pass_2 \ 463 && optimize_align_code \ 464 && (!(fill) \ 465 || ((char)*(fill) == (char)0x90 && (len) == 1)) \ 466 && subseg_text_p (now_seg)) \ 467 { \ 468 frag_align_code ((n), (max)); \ 469 goto around; \ 470 } 471 472 #define MAX_MEM_FOR_RS_ALIGN_CODE 15 473 474 extern void i386_align_code PARAMS ((fragS *, int)); 475 476 #define HANDLE_ALIGN(fragP) \ 477 if (fragP->fr_type == rs_align_code) \ 478 i386_align_code (fragP, (fragP->fr_next->fr_address \ 479 - fragP->fr_address \ 480 - fragP->fr_fix)); 481 482 void i386_print_statistics PARAMS ((FILE *)); 483 #define tc_print_statistics i386_print_statistics 484 485 #define md_number_to_chars number_to_chars_littleendian 486 487 #ifdef SCO_ELF 488 #define tc_init_after_args() sco_id () 489 extern void sco_id PARAMS ((void)); 490 #endif 491 492 /* We want .cfi_* pseudo-ops for generating unwind info. */ 493 #define TARGET_USE_CFIPOP 1 494 495 extern unsigned int x86_dwarf2_return_column; 496 #define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column 497 498 extern int x86_cie_data_alignment; 499 #define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment 500 501 #define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum 502 extern int tc_x86_regname_to_dw2regnum PARAMS ((const char *regname)); 503 504 #define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions 505 extern void tc_x86_frame_initial_instructions PARAMS ((void)); 506 507 #define md_elf_section_type(str,len) i386_elf_section_type (str, len) 508 extern int i386_elf_section_type PARAMS ((const char *, size_t len)); 509 510 #ifdef TE_PE 511 512 #define O_secrel O_md1 513 514 #define TC_DWARF2_EMIT_OFFSET tc_pe_dwarf2_emit_offset 515 void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int); 516 517 #endif /* TE_PE */ 518 519 #endif /* TC_I386 */ 520