1 /* 2 * Copyright (c) 2007 Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 */ 35 36 #define MAX_OHCI 5 37 #define CROMSIZE 0x400 38 39 struct fwohci_softc { 40 uint32_t locator; 41 uint32_t devid; 42 uint32_t base_addr; 43 uint32_t bus_id; 44 uint32_t handle; 45 int32_t state; 46 struct crom_src_buf *crom_src_buf; 47 struct crom_src *crom_src; 48 struct crom_chunk *crom_root; 49 struct fw_eui64 eui; 50 int speed; 51 int maxrec; 52 uint32_t *config_rom; 53 char config_rom_buf[CROMSIZE*2]; /* double size for alignment */ 54 }; 55 56 int fwohci_init(struct fwohci_softc *, int); 57 void fwohci_ibr(struct fwohci_softc *); 58 void fwohci_poll(struct fwohci_softc *); 59 60 #define FWOHCI_STATE_DEAD (-1) 61 #define FWOHCI_STATE_INIT 0 62 #define FWOHCI_STATE_ENABLED 1 63 #define FWOHCI_STATE_BUSRESET 2 64 #define FWOHCI_STATE_NORMAL 3 65 66 #define OREAD(f, o) (*(volatile uint32_t *)((f)->handle + (o))) 67 #define OWRITE(f, o, v) (*(volatile uint32_t *)((f)->handle + (o)) = (v)) 68 69 #define OHCI_VERSION 0x00 70 #define OHCI_ATRETRY 0x08 71 #define OHCI_CROMHDR 0x18 72 #define OHCI_BUS_ID 0x1c 73 #define OHCI_BUS_OPT 0x20 74 #define OHCI_BUSIRMC (1U << 31) 75 #define OHCI_BUSCMC (1 << 30) 76 #define OHCI_BUSISC (1 << 29) 77 #define OHCI_BUSBMC (1 << 28) 78 #define OHCI_BUSPMC (1 << 27) 79 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 80 OHCI_BUSBMC | OHCI_BUSPMC 81 82 #define OHCI_EUID_HI 0x24 83 #define OHCI_EUID_LO 0x28 84 85 #define OHCI_CROMPTR 0x34 86 #define OHCI_HCCCTL 0x50 87 #define OHCI_HCCCTLCLR 0x54 88 #define OHCI_AREQHI 0x100 89 #define OHCI_AREQHICLR 0x104 90 #define OHCI_AREQLO 0x108 91 #define OHCI_AREQLOCLR 0x10c 92 #define OHCI_PREQHI 0x110 93 #define OHCI_PREQHICLR 0x114 94 #define OHCI_PREQLO 0x118 95 #define OHCI_PREQLOCLR 0x11c 96 #define OHCI_PREQUPPER 0x120 97 98 #define OHCI_SID_BUF 0x64 99 #define OHCI_SID_CNT 0x68 100 #define OHCI_SID_ERR (1U << 31) 101 #define OHCI_SID_CNT_MASK 0xffc 102 103 #define OHCI_IT_STAT 0x90 104 #define OHCI_IT_STATCLR 0x94 105 #define OHCI_IT_MASK 0x98 106 #define OHCI_IT_MASKCLR 0x9c 107 108 #define OHCI_IR_STAT 0xa0 109 #define OHCI_IR_STATCLR 0xa4 110 #define OHCI_IR_MASK 0xa8 111 #define OHCI_IR_MASKCLR 0xac 112 113 #define OHCI_LNKCTL 0xe0 114 #define OHCI_LNKCTLCLR 0xe4 115 116 #define OHCI_PHYACCESS 0xec 117 #define OHCI_CYCLETIMER 0xf0 118 119 #define OHCI_DMACTL(off) (off) 120 #define OHCI_DMACTLCLR(off) (off + 4) 121 #define OHCI_DMACMD(off) (off + 0xc) 122 #define OHCI_DMAMATCH(off) (off + 0x10) 123 124 #define OHCI_ATQOFF 0x180 125 #define OHCI_ATQCTL OHCI_ATQOFF 126 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 127 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 128 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 129 130 #define OHCI_ATSOFF 0x1a0 131 #define OHCI_ATSCTL OHCI_ATSOFF 132 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 133 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 134 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 135 136 #define OHCI_ARQOFF 0x1c0 137 #define OHCI_ARQCTL OHCI_ARQOFF 138 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 139 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 140 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 141 142 #define OHCI_ARSOFF 0x1e0 143 #define OHCI_ARSCTL OHCI_ARSOFF 144 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 145 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 146 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 147 148 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 149 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 150 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 151 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 152 153 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 154 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 155 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 156 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 157 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 158