1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #ifndef __BXE_H__
30 #define __BXE_H__
31
32 #include <sys/cdefs.h>
33 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
36 #include <sys/lock.h>
37 #include <sys/mutex.h>
38 #include <sys/sx.h>
39 #include <sys/module.h>
40 #include <sys/endian.h>
41 #include <sys/types.h>
42 #include <sys/malloc.h>
43 #include <sys/kobj.h>
44 #include <sys/bus.h>
45 #include <sys/rman.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/smp.h>
50 #include <sys/bitstring.h>
51 #include <sys/limits.h>
52 #include <sys/queue.h>
53 #include <sys/taskqueue.h>
54 #include <contrib/zlib/zlib.h>
55
56 #include <net/debugnet.h>
57 #include <net/if.h>
58 #include <net/if_types.h>
59 #include <net/if_arp.h>
60 #include <net/ethernet.h>
61 #include <net/if_dl.h>
62 #include <net/if_var.h>
63 #include <net/if_media.h>
64 #include <net/if_vlan_var.h>
65 #include <net/bpf.h>
66
67 #include <netinet/in.h>
68 #include <netinet/ip.h>
69 #include <netinet/ip6.h>
70 #include <netinet/tcp.h>
71 #include <netinet/udp.h>
72
73 #include <dev/pci/pcireg.h>
74 #include <dev/pci/pcivar.h>
75
76 #include <machine/atomic.h>
77 #include <machine/resource.h>
78 #include <machine/endian.h>
79 #include <machine/bus.h>
80 #include <machine/in_cksum.h>
81
82 #include "device_if.h"
83 #include "bus_if.h"
84 #include "pci_if.h"
85
86 #if _BYTE_ORDER == _LITTLE_ENDIAN
87 #ifndef LITTLE_ENDIAN
88 #define LITTLE_ENDIAN
89 #endif
90 #ifndef __LITTLE_ENDIAN
91 #define __LITTLE_ENDIAN
92 #endif
93 #undef BIG_ENDIAN
94 #undef __BIG_ENDIAN
95 #else /* _BIG_ENDIAN */
96 #ifndef BIG_ENDIAN
97 #define BIG_ENDIAN
98 #endif
99 #ifndef __BIG_ENDIAN
100 #define __BIG_ENDIAN
101 #endif
102 #undef LITTLE_ENDIAN
103 #undef __LITTLE_ENDIAN
104 #endif
105
106 #include "ecore_mfw_req.h"
107 #include "ecore_fw_defs.h"
108 #include "ecore_hsi.h"
109 #include "ecore_reg.h"
110 #include "bxe_dcb.h"
111 #include "bxe_stats.h"
112
113 #include "bxe_elink.h"
114
115 #define VF_MAC_CREDIT_CNT 0
116 #define VF_VLAN_CREDIT_CNT (0)
117
118 #ifndef ARRAY_SIZE
119 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
120 #endif
121 #ifndef ARRSIZE
122 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
123 #endif
124 #ifndef DIV_ROUND_UP
125 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
126 #endif
127 #ifndef roundup
128 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
129 #endif
130
131 #include "ecore_sp.h"
132
133 #define BRCM_VENDORID 0x14e4
134 #define QLOGIC_VENDORID 0x1077
135 #define PCI_ANY_ID (uint16_t)(~0U)
136
137 struct bxe_device_type
138 {
139 uint16_t bxe_vid;
140 uint16_t bxe_did;
141 uint16_t bxe_svid;
142 uint16_t bxe_sdid;
143 char *bxe_name;
144 };
145
146 #define BCM_PAGE_SHIFT 12
147 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
148 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
149 #define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
150
151 #if BCM_PAGE_SIZE != 4096
152 #error Page sizes other than 4KB are unsupported!
153 #endif
154
155 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
156 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))
157 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))
158 #else
159 #define U64_LO(addr) ((uint32_t)(addr))
160 #define U64_HI(addr) (0)
161 #endif
162 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))
163
164 #define SET_FLAG(value, mask, flag) \
165 do { \
166 (value) &= ~(mask); \
167 (value) |= ((flag) << (mask##_SHIFT)); \
168 } while (0)
169
170 #define GET_FLAG(value, mask) \
171 (((value) & (mask)) >> (mask##_SHIFT))
172
173 #define GET_FIELD(value, fname) \
174 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
175
176 #define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */
177 #define BXE_TSO_MAX_SEGMENTS 32
178 #define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header))
179 #define BXE_TSO_MAX_SEG_SIZE 4096
180
181 /* dropless fc FW/HW related params */
182 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512)
183 #define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \
184 ETH_MAX_AGGREGATION_QUEUES_E1 : \
185 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
186 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))
187 #define FW_PREFETCH_CNT 16
188 #define DROPLESS_FC_HEADROOM 100
189
190 /******************/
191 /* RX SGE defines */
192 /******************/
193
194 #define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */
195 #define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
196 #define RX_SGE_NEXT_PAGE_DESC_CNT 2
197 #define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT)
198 #define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1)
199 #define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES)
200 #define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)
201 #define RX_SGE_MAX (RX_SGE_TOTAL - 1)
202 #define RX_SGE(x) ((x) & RX_SGE_MAX)
203
204 #define RX_SGE_NEXT(x) \
205 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \
206 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1)
207
208 #define RX_SGE_MASK_ELEM_SZ 64
209 #define RX_SGE_MASK_ELEM_SHIFT 6
210 #define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1)
211
212 /*
213 * Creates a bitmask of all ones in less significant bits.
214 * idx - index of the most significant bit in the created mask.
215 */
216 #define RX_SGE_ONES_MASK(idx) \
217 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
218 #define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0))
219
220 /* Number of uint64_t elements in SGE mask array. */
221 #define RX_SGE_MASK_LEN \
222 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ)
223 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
224 #define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
225
226 /*
227 * dropless fc calculations for SGEs
228 * Number of required SGEs is the sum of two:
229 * 1. Number of possible opened aggregations (next packet for
230 * these aggregations will probably consume SGE immidiatelly)
231 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
232 * after placement on BD for new TPA aggregation)
233 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page
234 */
235 #define NUM_SGE_REQ(sc) \
236 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2)
237 #define NUM_SGE_PG_REQ(sc) \
238 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE)
239 #define SGE_TH_LO(sc) \
240 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT)
241 #define SGE_TH_HI(sc) \
242 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM)
243
244 #define PAGES_PER_SGE_SHIFT 0
245 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
246 #define SGE_PAGE_SIZE BCM_PAGE_SIZE
247 #define SGE_PAGE_SHIFT BCM_PAGE_SHIFT
248 #define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr)
249 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
250 #define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff)
251
252 /*****************/
253 /* TX BD defines */
254 /*****************/
255
256 #define TX_BD_NUM_PAGES 16 /* must be a power of 2 */
257 #define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
258 #define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1)
259 #define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES)
260 #define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES)
261 #define TX_BD_MAX (TX_BD_TOTAL - 1)
262
263 #define TX_BD_NEXT(x) \
264 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \
265 ((x) + 2) : ((x) + 1))
266 #define TX_BD(x) ((x) & TX_BD_MAX)
267 #define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8)
268 #define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE)
269
270 /*
271 * Trigger pending transmits when the number of available BDs is greater
272 * than 1/8 of the total number of usable BDs.
273 */
274 #define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8)
275 #define BXE_TX_TIMEOUT 5
276
277 /*****************/
278 /* RX BD defines */
279 /*****************/
280
281 #define RX_BD_NUM_PAGES 8 /* power of 2 */
282 #define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
283 #define RX_BD_NEXT_PAGE_DESC_CNT 2
284 #define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT)
285 #define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1)
286 #define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES)
287 #define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES)
288 #define RX_BD_MAX (RX_BD_TOTAL - 1)
289
290 #define RX_BD_NEXT(x) \
291 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \
292 ((x) + 3) : ((x) + 1))
293 #define RX_BD(x) ((x) & RX_BD_MAX)
294 #define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
295 #define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)
296
297 /*
298 * dropless fc calculations for BDs
299 * Number of BDs should be as number of buffers in BRB:
300 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT
301 * "next" elements on each page
302 */
303 #define NUM_BD_REQ(sc) \
304 BRB_SIZE(sc)
305 #define NUM_BD_PG_REQ(sc) \
306 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE)
307 #define BD_TH_LO(sc) \
308 (NUM_BD_REQ(sc) + \
309 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
310 FW_DROP_LEVEL(sc))
311 #define BD_TH_HI(sc) \
312 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)
313 #define MIN_RX_AVAIL(sc) \
314 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
315 #define MIN_RX_SIZE_TPA_HW(sc) \
316 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \
317 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
318 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
319 #define MIN_RX_SIZE_TPA(sc) \
320 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc)))
321 #define MIN_RX_SIZE_NONTPA(sc) \
322 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc)))
323
324 /***************/
325 /* RCQ defines */
326 /***************/
327
328 /*
329 * As long as CQE is X times bigger than BD entry we have to allocate X times
330 * more pages for CQ ring in order to keep it balanced with BD ring
331 */
332 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / \
333 sizeof(struct eth_rx_bd))
334 #define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */
335 #define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
336 #define RCQ_NEXT_PAGE_DESC_CNT 1
337 #define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT)
338 #define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES)
339 #define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES)
340 #define RCQ_MAX (RCQ_TOTAL - 1)
341
342 #define RCQ_NEXT(x) \
343 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \
344 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1))
345 #define RCQ(x) ((x) & RCQ_MAX)
346 #define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7)
347 #define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE)
348
349 /*
350 * dropless fc calculations for RCQs
351 * Number of RCQs should be as number of buffers in BRB:
352 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT
353 * "next" elements on each page
354 */
355 #define NUM_RCQ_REQ(sc) \
356 BRB_SIZE(sc)
357 #define NUM_RCQ_PG_REQ(sc) \
358 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE)
359 #define RCQ_TH_LO(sc) \
360 (NUM_RCQ_REQ(sc) + \
361 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \
362 FW_DROP_LEVEL(sc))
363 #define RCQ_TH_HI(sc) \
364 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)
365
366 /* This is needed for determening of last_max */
367 #define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b))
368
369 #define __SGE_MASK_SET_BIT(el, bit) \
370 do { \
371 (el) = ((el) | ((uint64_t)0x1 << (bit))); \
372 } while (0)
373
374 #define __SGE_MASK_CLEAR_BIT(el, bit) \
375 do { \
376 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \
377 } while (0)
378
379 #define SGE_MASK_SET_BIT(fp, idx) \
380 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
381 ((idx) & RX_SGE_MASK_ELEM_MASK))
382
383 #define SGE_MASK_CLEAR_BIT(fp, idx) \
384 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
385 ((idx) & RX_SGE_MASK_ELEM_MASK))
386
387 /* Load / Unload modes */
388 #define LOAD_NORMAL 0
389 #define LOAD_OPEN 1
390 #define LOAD_DIAG 2
391 #define LOAD_LOOPBACK_EXT 3
392 #define UNLOAD_NORMAL 0
393 #define UNLOAD_CLOSE 1
394 #define UNLOAD_RECOVERY 2
395
396 /* Some constants... */
397 //#define MAX_PATH_NUM 2
398 //#define E2_MAX_NUM_OF_VFS 64
399 //#define E1H_FUNC_MAX 8
400 //#define E2_FUNC_MAX 4 /* per path */
401 #define MAX_VNIC_NUM 4
402 #define MAX_FUNC_NUM 8 /* common to all chips */
403 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */
404 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */
405 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */
406
407 #define ILT_NUM_PAGE_ENTRIES 3072
408 /*
409 * 57710/11 we use whole table since we have 8 functions.
410 * 57712 we have only 4 functions, but use same size per func, so only half
411 * of the table is used.
412 */
413 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8)
414 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
415 /*
416 * the phys address is shifted right 12 bits and has an added
417 * 1=valid bit added to the 53rd bit
418 * then since this is a wide register(TM)
419 * we split it into two 32 bit writes
420 */
421 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
422 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
423
424 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
425 #define ETH_HLEN 14
426 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
427 #define ETH_MIN_PACKET_SIZE 60
428 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */
429 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
430 /* TCP with Timestamp Option (32) + IPv6 (40) */
431 #define ETH_MAX_TPA_HEADER_SIZE 72
432
433 /* max supported alignment is 256 (8 shift) */
434 //#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8)
435 #define BXE_RX_ALIGN_SHIFT 8
436 /* FW uses 2 cache lines alignment for start packet and size */
437 #define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT)
438 #define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT)
439
440 #define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */
441 #define BXE_SET_ERROR_BIT(sc, error) \
442 { \
443 (sc)->error_status |= (error); \
444 }
445
446 struct bxe_bar {
447 struct resource *resource;
448 int rid;
449 bus_space_tag_t tag;
450 bus_space_handle_t handle;
451 vm_offset_t kva;
452 };
453
454 struct bxe_intr {
455 struct resource *resource;
456 int rid;
457 void *tag;
458 };
459
460 /* Used to manage DMA allocations. */
461 struct bxe_dma {
462 struct bxe_softc *sc;
463 bus_addr_t paddr;
464 void *vaddr;
465 bus_dma_tag_t tag;
466 bus_dmamap_t map;
467 bus_dma_segment_t seg;
468 bus_size_t size;
469 int nseg;
470 char msg[32];
471 };
472
473 /* attn group wiring */
474 #define MAX_DYNAMIC_ATTN_GRPS 8
475
476 struct attn_route {
477 uint32_t sig[5];
478 };
479
480 struct iro {
481 uint32_t base;
482 uint16_t m1;
483 uint16_t m2;
484 uint16_t m3;
485 uint16_t size;
486 };
487
488 union bxe_host_hc_status_block {
489 /* pointer to fp status block e2 */
490 struct host_hc_status_block_e2 *e2_sb;
491 /* pointer to fp status block e1x */
492 struct host_hc_status_block_e1x *e1x_sb;
493 };
494
495 union bxe_db_prod {
496 struct doorbell_set_prod data;
497 uint32_t raw;
498 };
499
500 struct bxe_sw_tx_bd {
501 struct mbuf *m;
502 bus_dmamap_t m_map;
503 uint16_t first_bd;
504 uint8_t flags;
505 /* set on the first BD descriptor when there is a split BD */
506 #define BXE_TSO_SPLIT_BD (1 << 0)
507 };
508
509 struct bxe_sw_rx_bd {
510 struct mbuf *m;
511 bus_dmamap_t m_map;
512 };
513
514 struct bxe_sw_tpa_info {
515 struct bxe_sw_rx_bd bd;
516 bus_dma_segment_t seg;
517 uint8_t state;
518 #define BXE_TPA_STATE_START 1
519 #define BXE_TPA_STATE_STOP 2
520 uint8_t placement_offset;
521 uint16_t parsing_flags;
522 uint16_t vlan_tag;
523 uint16_t len_on_bd;
524 };
525
526 /*
527 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN
528 * instances of the fastpath structure when using multiple queues.
529 */
530 struct bxe_fastpath {
531 /* pointer back to parent structure */
532 struct bxe_softc *sc;
533
534 struct mtx tx_mtx;
535 char tx_mtx_name[32];
536 struct mtx rx_mtx;
537 char rx_mtx_name[32];
538
539 #define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx)
540 #define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx)
541 #define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED)
542 #define BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx)
543
544 #define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx)
545 #define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx)
546 #define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED)
547
548 /* status block */
549 struct bxe_dma sb_dma;
550 union bxe_host_hc_status_block status_block;
551
552 /* transmit chain (tx bds) */
553 struct bxe_dma tx_dma;
554 union eth_tx_bd_types *tx_chain;
555
556 /* receive chain (rx bds) */
557 struct bxe_dma rx_dma;
558 struct eth_rx_bd *rx_chain;
559
560 /* receive completion queue chain (rcq bds) */
561 struct bxe_dma rcq_dma;
562 union eth_rx_cqe *rcq_chain;
563
564 /* receive scatter/gather entry chain (for TPA) */
565 struct bxe_dma rx_sge_dma;
566 struct eth_rx_sge *rx_sge_chain;
567
568 /* tx mbufs */
569 bus_dma_tag_t tx_mbuf_tag;
570 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL];
571
572 /* rx mbufs */
573 bus_dma_tag_t rx_mbuf_tag;
574 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL];
575 bus_dmamap_t rx_mbuf_spare_map;
576
577 /* rx sge mbufs */
578 bus_dma_tag_t rx_sge_mbuf_tag;
579 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL];
580 bus_dmamap_t rx_sge_mbuf_spare_map;
581
582 /* rx tpa mbufs (use the larger size for TPA queue length) */
583 int tpa_enable; /* disabled per fastpath upon error */
584 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
585 bus_dmamap_t rx_tpa_info_mbuf_spare_map;
586 uint64_t rx_tpa_queue_used;
587
588 uint16_t *sb_index_values;
589 uint16_t *sb_running_index;
590 uint32_t ustorm_rx_prods_offset;
591
592 uint8_t igu_sb_id; /* status block number in HW */
593 uint8_t fw_sb_id; /* status block number in FW */
594
595 uint32_t rx_buf_size;
596 int mbuf_alloc_size;
597
598 int state;
599 #define BXE_FP_STATE_CLOSED 0x01
600 #define BXE_FP_STATE_IRQ 0x02
601 #define BXE_FP_STATE_OPENING 0x04
602 #define BXE_FP_STATE_OPEN 0x08
603 #define BXE_FP_STATE_HALTING 0x10
604 #define BXE_FP_STATE_HALTED 0x20
605
606 /* reference back to this fastpath queue number */
607 uint8_t index; /* this is also the 'cid' */
608 #define FP_IDX(fp) (fp->index)
609
610 /* interrupt taskqueue (fast) */
611 struct task tq_task;
612 struct taskqueue *tq;
613 char tq_name[32];
614
615 struct task tx_task;
616 struct timeout_task tx_timeout_task;
617
618 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */
619 uint8_t cl_id;
620 #define FP_CL_ID(fp) (fp->cl_id)
621 uint8_t cl_qzone_id;
622
623 uint16_t fp_hc_idx;
624
625 /* driver copy of the receive buffer descriptor prod/cons indices */
626 uint16_t rx_bd_prod;
627 uint16_t rx_bd_cons;
628
629 /* driver copy of the receive completion queue prod/cons indices */
630 uint16_t rx_cq_prod;
631 uint16_t rx_cq_cons;
632
633 union bxe_db_prod tx_db;
634
635 /* Transmit packet producer index (used in eth_tx_bd). */
636 uint16_t tx_pkt_prod;
637 uint16_t tx_pkt_cons;
638
639 /* Transmit buffer descriptor producer index. */
640 uint16_t tx_bd_prod;
641 uint16_t tx_bd_cons;
642
643 uint64_t sge_mask[RX_SGE_MASK_LEN];
644 uint16_t rx_sge_prod;
645
646 struct tstorm_per_queue_stats old_tclient;
647 struct ustorm_per_queue_stats old_uclient;
648 struct xstorm_per_queue_stats old_xclient;
649 struct bxe_eth_q_stats eth_q_stats;
650 struct bxe_eth_q_stats_old eth_q_stats_old;
651
652 /* Pointer to the receive consumer in the status block */
653 uint16_t *rx_cq_cons_sb;
654
655 /* Pointer to the transmit consumer in the status block */
656 uint16_t *tx_cons_sb;
657
658 /* transmit timeout until chip reset */
659 int watchdog_timer;
660
661 /* Free/used buffer descriptor counters. */
662 //uint16_t used_tx_bd;
663
664 /* Last maximal completed SGE */
665 uint16_t last_max_sge;
666
667 //uint16_t rx_sge_free_idx;
668
669 //uint8_t segs;
670
671 #define BXE_BR_SIZE 4096
672 struct buf_ring *tx_br;
673 }; /* struct bxe_fastpath */
674
675 /* sriov XXX */
676 #define BXE_MAX_NUM_OF_VFS 64
677 #define BXE_VF_CID_WND 0
678 #define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND)
679 #define BXE_CLIENTS_PER_VF 1
680 #define BXE_FIRST_VF_CID 256
681 #define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF)
682 #define BXE_VF_ID_INVALID 0xFF
683 #define IS_SRIOV(sc) 0
684
685 #define GET_NUM_VFS_PER_PATH(sc) 0
686 #define GET_NUM_VFS_PER_PF(sc) 0
687
688 /* maximum number of fast-path interrupt contexts */
689 #define FP_SB_MAX_E1x 16
690 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
691
692 union cdu_context {
693 struct eth_context eth;
694 char pad[1024];
695 };
696
697 /* CDU host DB constants */
698 #define CDU_ILT_PAGE_SZ_HW 2
699 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
700 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
701
702 #define CNIC_ISCSI_CID_MAX 256
703 #define CNIC_FCOE_CID_MAX 2048
704 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
705 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
706
707 #define QM_ILT_PAGE_SZ_HW 0
708 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
709 #define QM_CID_ROUND 1024
710
711 /* TM (timers) host DB constants */
712 #define TM_ILT_PAGE_SZ_HW 0
713 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
714 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
715 #define TM_CONN_NUM 1024
716 #define TM_ILT_SZ (8 * TM_CONN_NUM)
717 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
718
719 /* SRC (Searcher) host DB constants */
720 #define SRC_ILT_PAGE_SZ_HW 0
721 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
722 #define SRC_HASH_BITS 10
723 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
724 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
725 #define SRC_T2_SZ SRC_ILT_SZ
726 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
727
728 struct hw_context {
729 struct bxe_dma vcxt_dma;
730 union cdu_context *vcxt;
731 //bus_addr_t cxt_mapping;
732 size_t size;
733 };
734
735 #define SM_RX_ID 0
736 #define SM_TX_ID 1
737
738 /* defines for multiple tx priority indices */
739 #define FIRST_TX_ONLY_COS_INDEX 1
740 #define FIRST_TX_COS_INDEX 0
741
742 #define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc))
743
744 #define HC_INDEX_ETH_RX_CQ_CONS 1
745 #define HC_INDEX_OOO_TX_CQ_CONS 4
746 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
747 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
748 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
749 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
750
751 /* congestion management fairness mode */
752 #define CMNG_FNS_NONE 0
753 #define CMNG_FNS_MINMAX 1
754
755 /* CMNG constants, as derived from system spec calculations */
756 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
757 #define DEF_MIN_RATE 100
758 /* resolution of the rate shaping timer - 400 usec */
759 #define RS_PERIODIC_TIMEOUT_USEC 400
760 /* number of bytes in single QM arbitration cycle -
761 * coefficient for calculating the fairness timer */
762 #define QM_ARB_BYTES 160000
763 /* resolution of Min algorithm 1:100 */
764 #define MIN_RES 100
765 /* how many bytes above threshold for the minimal credit of Min algorithm*/
766 #define MIN_ABOVE_THRESH 32768
767 /* fairness algorithm integration time coefficient -
768 * for calculating the actual Tfair */
769 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
770 /* memory of fairness algorithm - 2 cycles */
771 #define FAIR_MEM 2
772
773 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */
774 #define HC_SEG_ACCESS_ATTN 4
775 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */
776
777 /*
778 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
779 * control by the number of fast-path status blocks supported by the
780 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
781 * status block represents an independent interrupts context that can
782 * serve a regular L2 networking queue. However special L2 queues such
783 * as the FCoE queue do not require a FP-SB and other components like
784 * the CNIC may consume FP-SB reducing the number of possible L2 queues
785 *
786 * If the maximum number of FP-SB available is X then:
787 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
788 * regular L2 queues is Y=X-1
789 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
790 * c. If the FCoE L2 queue is supported the actual number of L2 queues
791 * is Y+1
792 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
793 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
794 * FP interrupt context for the CNIC).
795 * e. The number of HW context (CID count) is always X or X+1 if FCoE
796 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
797 *
798 * So this is quite simple for now as no ULPs are supported yet. :-)
799 */
800 #define BXE_NUM_QUEUES(sc) ((sc)->num_queues)
801 #define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc)
802 #define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc)
803 #define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc)
804
805 #define FOR_EACH_QUEUE(sc, var) \
806 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++)
807
808 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \
809 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++)
810
811 #define FOR_EACH_ETH_QUEUE(sc, var) \
812 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++)
813
814 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \
815 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++)
816
817 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \
818 for ((var) = 0; (var) < (sc)->max_cos; (var)++)
819
820 #define FOR_EACH_CNIC_QUEUE(sc, var) \
821 for ((var) = BXE_NUM_ETH_QUEUES(sc); \
822 (var) < BXE_NUM_QUEUES(sc); \
823 (var)++)
824
825 enum {
826 OOO_IDX_OFFSET,
827 FCOE_IDX_OFFSET,
828 FWD_IDX_OFFSET,
829 };
830
831 #define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)
832 #define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)])
833 #define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var)
834 #define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])
835 #define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var)
836 #define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)
837
838 #define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)
839 #define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)])
840 #define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var)
841 #define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)])
842 #define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var)
843
844 #define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)
845 #define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)])
846 #define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var)
847 #define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)])
848 #define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var)
849 #define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX])
850
851 #define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc))
852 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc))
853 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))
854 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc))
855 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc))
856 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc))
857 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc))
858
859 enum {
860 BXE_PORT_QUERY_IDX,
861 BXE_PF_QUERY_IDX,
862 BXE_FCOE_QUERY_IDX,
863 BXE_FIRST_QUEUE_QUERY_IDX,
864 };
865
866 struct bxe_fw_stats_req {
867 struct stats_query_header hdr;
868 struct stats_query_entry query[FP_SB_MAX_E1x +
869 BXE_FIRST_QUEUE_QUERY_IDX];
870 };
871
872 struct bxe_fw_stats_data {
873 struct stats_counter storm_counters;
874 struct per_port_stats port;
875 struct per_pf_stats pf;
876 //struct fcoe_statistics_params fcoe;
877 struct per_queue_stats queue_stats[1];
878 };
879
880 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
881 #define BXE_IGU_STAS_MSG_VF_CNT 64
882 #define BXE_IGU_STAS_MSG_PF_CNT 4
883
884 #define MAX_DMAE_C 8
885
886 /*
887 * For the main interface up/down code paths, a not-so-fine-grained CORE
888 * mutex lock is used. Inside this code are various calls to kernel routines
889 * that can cause a sleep to occur. Namely memory allocations and taskqueue
890 * handling. If using an MTX lock we are *not* allowed to sleep but we can
891 * with an SX lock. This define forces the CORE lock to use and SX lock.
892 * Undefine this and an MTX lock will be used instead. Note that the IOCTL
893 * path can cause problems since it's called by a non-sleepable thread. To
894 * alleviate a potential sleep, any IOCTL processing that results in the
895 * chip/interface being started/stopped/reinitialized, the actual work is
896 * offloaded to a taskqueue.
897 */
898 #define BXE_CORE_LOCK_SX
899
900 /*
901 * This is the slowpath data structure. It is mapped into non-paged memory
902 * so that the hardware can access it's contents directly and must be page
903 * aligned.
904 */
905 struct bxe_slowpath {
906
907 /* used by the DMAE command executer */
908 struct dmae_cmd dmae[MAX_DMAE_C];
909
910 /* statistics completion */
911 uint32_t stats_comp;
912
913 /* firmware defined statistics blocks */
914 union mac_stats mac_stats;
915 struct nig_stats nig_stats;
916 struct host_port_stats port_stats;
917 struct host_func_stats func_stats;
918 //struct host_func_stats func_stats_base;
919
920 /* DMAE completion value and data source/sink */
921 uint32_t wb_comp;
922 uint32_t wb_data[4];
923
924 union {
925 struct mac_configuration_cmd e1x;
926 struct eth_classify_rules_ramrod_data e2;
927 } mac_rdata;
928
929 union {
930 struct tstorm_eth_mac_filter_config e1x;
931 struct eth_filter_rules_ramrod_data e2;
932 } rx_mode_rdata;
933
934 struct eth_rss_update_ramrod_data rss_rdata;
935
936 union {
937 struct mac_configuration_cmd e1;
938 struct eth_multicast_rules_ramrod_data e2;
939 } mcast_rdata;
940
941 union {
942 struct function_start_data func_start;
943 struct flow_control_configuration pfc_config; /* for DCBX ramrod */
944 } func_rdata;
945
946 /* Queue State related ramrods */
947 union {
948 struct client_init_ramrod_data init_data;
949 struct client_update_ramrod_data update_data;
950 } q_rdata;
951
952 /*
953 * AFEX ramrod can not be a part of func_rdata union because these
954 * events might arrive in parallel to other events from func_rdata.
955 * If they were defined in the same union the data can get corrupted.
956 */
957 struct afex_vif_list_ramrod_data func_afex_rdata;
958
959 union drv_info_to_mcp drv_info_to_mcp;
960 }; /* struct bxe_slowpath */
961
962 /*
963 * Port specifc data structure.
964 */
965 struct bxe_port {
966 /*
967 * Port Management Function (for 57711E only).
968 * When this field is set the driver instance is
969 * responsible for managing port specifc
970 * configurations such as handling link attentions.
971 */
972 uint32_t pmf;
973
974 /* Ethernet maximum transmission unit. */
975 uint16_t ether_mtu;
976
977 uint32_t link_config[ELINK_LINK_CONFIG_SIZE];
978
979 uint32_t ext_phy_config;
980
981 /* Port feature config.*/
982 uint32_t config;
983
984 /* Defines the features supported by the PHY. */
985 uint32_t supported[ELINK_LINK_CONFIG_SIZE];
986
987 /* Defines the features advertised by the PHY. */
988 uint32_t advertising[ELINK_LINK_CONFIG_SIZE];
989 #define ADVERTISED_10baseT_Half (1 << 1)
990 #define ADVERTISED_10baseT_Full (1 << 2)
991 #define ADVERTISED_100baseT_Half (1 << 3)
992 #define ADVERTISED_100baseT_Full (1 << 4)
993 #define ADVERTISED_1000baseT_Half (1 << 5)
994 #define ADVERTISED_1000baseT_Full (1 << 6)
995 #define ADVERTISED_TP (1 << 7)
996 #define ADVERTISED_FIBRE (1 << 8)
997 #define ADVERTISED_Autoneg (1 << 9)
998 #define ADVERTISED_Asym_Pause (1 << 10)
999 #define ADVERTISED_Pause (1 << 11)
1000 #define ADVERTISED_2500baseX_Full (1 << 15)
1001 #define ADVERTISED_10000baseT_Full (1 << 16)
1002
1003 uint32_t phy_addr;
1004
1005 /* Used to synchronize phy accesses. */
1006 struct mtx phy_mtx;
1007 char phy_mtx_name[32];
1008
1009 #define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx)
1010 #define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx)
1011 #define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED)
1012
1013 /*
1014 * MCP scratchpad address for port specific statistics.
1015 * The device is responsible for writing statistcss
1016 * back to the MCP for use with management firmware such
1017 * as UMP/NC-SI.
1018 */
1019 uint32_t port_stx;
1020
1021 struct nig_stats old_nig_stats;
1022 }; /* struct bxe_port */
1023
1024 struct bxe_mf_info {
1025 uint32_t mf_config[E1HVN_MAX];
1026
1027 uint32_t vnics_per_port; /* 1, 2 or 4 */
1028 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */
1029 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */
1030
1031 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode)
1032 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)
1033 #define VNICS_PER_PATH(sc) \
1034 ((sc)->devinfo.mf_info.vnics_per_port * \
1035 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))
1036
1037 uint8_t min_bw[MAX_VNIC_NUM];
1038 uint8_t max_bw[MAX_VNIC_NUM];
1039
1040 uint16_t ext_id; /* vnic outer vlan or VIF ID */
1041 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096)
1042 #define INVALID_VIF_ID 0xFFFF
1043 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)
1044 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)
1045
1046 uint16_t default_vlan;
1047 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)
1048
1049 uint8_t niv_allowed_priorities;
1050 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)
1051
1052 uint8_t niv_default_cos;
1053 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)
1054
1055 uint8_t niv_mba_enabled;
1056
1057 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1058 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)
1059 int afex_def_vlan_tag;
1060 uint32_t pending_max;
1061
1062 uint16_t flags;
1063 #define MF_INFO_VALID_MAC 0x0001
1064
1065 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */
1066 #define IS_MF(sc) \
1067 (IS_MULTI_VNIC(sc) && \
1068 ((sc)->devinfo.mf_info.mf_mode != 0))
1069 #define IS_MF_SD(sc) \
1070 (IS_MULTI_VNIC(sc) && \
1071 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))
1072 #define IS_MF_SI(sc) \
1073 (IS_MULTI_VNIC(sc) && \
1074 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))
1075 #define IS_MF_AFEX(sc) \
1076 (IS_MULTI_VNIC(sc) && \
1077 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))
1078 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc)
1079 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc)
1080 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)
1081
1082 uint32_t mf_protos_supported;
1083 #define MF_PROTO_SUPPORT_ETHERNET 0x1
1084 #define MF_PROTO_SUPPORT_ISCSI 0x2
1085 #define MF_PROTO_SUPPORT_FCOE 0x4
1086 }; /* struct bxe_mf_info */
1087
1088 /* Device information data structure. */
1089 struct bxe_devinfo {
1090 /* PCIe info */
1091 uint16_t vendor_id;
1092 uint16_t device_id;
1093 uint16_t subvendor_id;
1094 uint16_t subdevice_id;
1095
1096 /*
1097 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB'
1098 * C = Chip Number (bits 16-31)
1099 * R = Chip Revision (bits 12-15)
1100 * M = Chip Metal (bits 4-11)
1101 * B = Chip Bond ID (bits 0-3)
1102 */
1103 uint32_t chip_id;
1104 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
1105 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
1106 /* device ids */
1107 #define CHIP_NUM_57710 0x164e
1108 #define CHIP_NUM_57711 0x164f
1109 #define CHIP_NUM_57711E 0x1650
1110 #define CHIP_NUM_57712 0x1662
1111 #define CHIP_NUM_57712_MF 0x1663
1112 #define CHIP_NUM_57712_VF 0x166f
1113 #define CHIP_NUM_57800 0x168a
1114 #define CHIP_NUM_57800_MF 0x16a5
1115 #define CHIP_NUM_57800_VF 0x16a9
1116 #define CHIP_NUM_57810 0x168e
1117 #define CHIP_NUM_57810_MF 0x16ae
1118 #define CHIP_NUM_57810_VF 0x16af
1119 #define CHIP_NUM_57811 0x163d
1120 #define CHIP_NUM_57811_MF 0x163e
1121 #define CHIP_NUM_57811_VF 0x163f
1122 #define CHIP_NUM_57840_OBS 0x168d
1123 #define CHIP_NUM_57840_OBS_MF 0x16ab
1124 #define CHIP_NUM_57840_4_10 0x16a1
1125 #define CHIP_NUM_57840_2_20 0x16a2
1126 #define CHIP_NUM_57840_MF 0x16a4
1127 #define CHIP_NUM_57840_VF 0x16ad
1128
1129 #define CHIP_REV_SHIFT 12
1130 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
1131 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK)
1132
1133 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
1134 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
1135 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT)
1136
1137 #define CHIP_REV_IS_SLOW(sc) \
1138 (CHIP_REV(sc) > 0x00005000)
1139 #define CHIP_REV_IS_FPGA(sc) \
1140 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))
1141 #define CHIP_REV_IS_EMUL(sc) \
1142 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))
1143 #define CHIP_REV_IS_ASIC(sc) \
1144 (!CHIP_REV_IS_SLOW(sc))
1145
1146 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
1147 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
1148
1149 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
1150 #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
1151 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
1152 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
1153 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
1154 (CHIP_IS_57711E(sc)))
1155 #define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \
1156 CHIP_IS_E1H((sc)))
1157
1158 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712)
1159 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)
1160 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)
1161 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \
1162 CHIP_IS_57712_MF(sc))
1163
1164 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800)
1165 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)
1166 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)
1167 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810)
1168 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)
1169 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)
1170 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811)
1171 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)
1172 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)
1173 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \
1174 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \
1175 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))
1176 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \
1177 (CHIP_NUM(sc) == CHIP_NUM_57840_MF))
1178 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)
1179
1180 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \
1181 CHIP_IS_57800_MF(sc) || \
1182 CHIP_IS_57800_VF(sc) || \
1183 CHIP_IS_57810(sc) || \
1184 CHIP_IS_57810_MF(sc) || \
1185 CHIP_IS_57810_VF(sc) || \
1186 CHIP_IS_57811(sc) || \
1187 CHIP_IS_57811_MF(sc) || \
1188 CHIP_IS_57811_VF(sc) || \
1189 CHIP_IS_57840(sc) || \
1190 CHIP_IS_57840_MF(sc) || \
1191 CHIP_IS_57840_VF(sc))
1192 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \
1193 (CHIP_REV(sc) == CHIP_REV_Ax))
1194 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \
1195 (CHIP_REV(sc) == CHIP_REV_Bx))
1196
1197 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc))
1198 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \
1199 CHIP_IS_E3(sc))
1200
1201 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \
1202 CHIP_IS_57712_MF(sc) || \
1203 CHIP_IS_E3(sc))
1204
1205 #define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \
1206 CHIP_IS_57800_VF(sc) || \
1207 CHIP_IS_57810_VF(sc) || \
1208 CHIP_IS_57840_VF(sc))
1209 #define IS_PF(sc) (!IS_VF(sc))
1210
1211 /*
1212 * This define is used in two main places:
1213 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher
1214 * to nic-only mode or to offload mode. Offload mode is configured if either
1215 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic
1216 * already registered for this port (which means that the user wants storage
1217 * services).
1218 * 2. During cnic-related load, to know if offload mode is already configured
1219 * in the HW or needs to be configrued. Since the transition from nic-mode to
1220 * offload-mode in HW causes traffic coruption, nic-mode is configured only
1221 * in ports on which storage services where never requested.
1222 */
1223 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
1224
1225 uint8_t chip_port_mode;
1226 #define CHIP_4_PORT_MODE 0x0
1227 #define CHIP_2_PORT_MODE 0x1
1228 #define CHIP_PORT_MODE_NONE 0x2
1229 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode)
1230 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)
1231
1232 uint8_t int_block;
1233 #define INT_BLOCK_HC 0
1234 #define INT_BLOCK_IGU 1
1235 #define INT_BLOCK_MODE_NORMAL 0
1236 #define INT_BLOCK_MODE_BW_COMP 2
1237 #define CHIP_INT_MODE_IS_NBC(sc) \
1238 (!CHIP_IS_E1x(sc) && \
1239 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))
1240 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))
1241
1242 uint32_t shmem_base;
1243 uint32_t shmem2_base;
1244 uint32_t bc_ver;
1245 char bc_ver_str[32];
1246 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */
1247 struct bxe_mf_info mf_info;
1248
1249 int flash_size;
1250 #define NVRAM_1MB_SIZE 0x20000
1251 #define NVRAM_TIMEOUT_COUNT 30000
1252 #define NVRAM_PAGE_SIZE 256
1253
1254 /* PCIe capability information */
1255 uint32_t pcie_cap_flags;
1256 #define BXE_PM_CAPABLE_FLAG 0x00000001
1257 #define BXE_PCIE_CAPABLE_FLAG 0x00000002
1258 #define BXE_MSI_CAPABLE_FLAG 0x00000004
1259 #define BXE_MSIX_CAPABLE_FLAG 0x00000008
1260 uint16_t pcie_pm_cap_reg;
1261 uint16_t pcie_pcie_cap_reg;
1262 //uint16_t pcie_devctl;
1263 uint16_t pcie_link_width;
1264 uint16_t pcie_link_speed;
1265 uint16_t pcie_msi_cap_reg;
1266 uint16_t pcie_msix_cap_reg;
1267
1268 /* device configuration read from bootcode shared memory */
1269 uint32_t hw_config;
1270 uint32_t hw_config2;
1271 }; /* struct bxe_devinfo */
1272
1273 struct bxe_sp_objs {
1274 struct ecore_vlan_mac_obj mac_obj; /* MACs object */
1275 struct ecore_queue_sp_obj q_obj; /* Queue State object */
1276 }; /* struct bxe_sp_objs */
1277
1278 /*
1279 * Data that will be used to create a link report message. We will keep the
1280 * data used for the last link report in order to prevent reporting the same
1281 * link parameters twice.
1282 */
1283 struct bxe_link_report_data {
1284 uint16_t line_speed; /* Effective line speed */
1285 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */
1286 };
1287 enum {
1288 BXE_LINK_REPORT_FULL_DUPLEX,
1289 BXE_LINK_REPORT_LINK_DOWN,
1290 BXE_LINK_REPORT_RX_FC_ON,
1291 BXE_LINK_REPORT_TX_FC_ON
1292 };
1293
1294 /* Top level device private data structure. */
1295 struct bxe_softc {
1296 /*
1297 * First entry must be a pointer to the BSD ifnet struct which
1298 * has a first element of 'void *if_softc' (which is us). XXX
1299 */
1300 if_t ifp;
1301 struct ifmedia ifmedia; /* network interface media structure */
1302 int media;
1303
1304 volatile int state; /* device state */
1305 #define BXE_STATE_CLOSED 0x0000
1306 #define BXE_STATE_OPENING_WAITING_LOAD 0x1000
1307 #define BXE_STATE_OPENING_WAITING_PORT 0x2000
1308 #define BXE_STATE_OPEN 0x3000
1309 #define BXE_STATE_CLOSING_WAITING_HALT 0x4000
1310 #define BXE_STATE_CLOSING_WAITING_DELETE 0x5000
1311 #define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000
1312 #define BXE_STATE_DISABLED 0xD000
1313 #define BXE_STATE_DIAG 0xE000
1314 #define BXE_STATE_ERROR 0xF000
1315
1316 int flags;
1317 #define BXE_ONE_PORT_FLAG 0x00000001
1318 #define BXE_NO_ISCSI 0x00000002
1319 #define BXE_NO_FCOE 0x00000004
1320 #define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG)
1321 //#define BXE_NO_WOL_FLAG 0x00000008
1322 //#define BXE_USING_DAC_FLAG 0x00000010
1323 //#define BXE_USING_MSIX_FLAG 0x00000020
1324 //#define BXE_USING_MSI_FLAG 0x00000040
1325 //#define BXE_DISABLE_MSI_FLAG 0x00000080
1326 #define BXE_NO_MCP_FLAG 0x00000200
1327 #define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG)
1328 //#define BXE_SAFC_TX_FLAG 0x00000400
1329 #define BXE_MF_FUNC_DIS 0x00000800
1330 #define BXE_TX_SWITCHING 0x00001000
1331 #define BXE_NO_PULSE 0x00002000
1332
1333 unsigned long debug; /* per-instance debug logging config */
1334
1335 #define MAX_BARS 5
1336 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */
1337
1338 uint16_t doorbell_size;
1339
1340 /* periodic timer callout */
1341 #define PERIODIC_STOP 0
1342 #define PERIODIC_GO 1
1343 volatile unsigned long periodic_flags;
1344 struct callout periodic_callout;
1345
1346 /* chip start/stop/reset taskqueue */
1347 #define CHIP_TQ_NONE 0
1348 #define CHIP_TQ_START 1
1349 #define CHIP_TQ_STOP 2
1350 #define CHIP_TQ_REINIT 3
1351 volatile unsigned long chip_tq_flags;
1352 struct task chip_tq_task;
1353 struct taskqueue *chip_tq;
1354 char chip_tq_name[32];
1355
1356 struct timeout_task sp_err_timeout_task;
1357
1358 /* slowpath interrupt taskqueue */
1359 struct task sp_tq_task;
1360 struct taskqueue *sp_tq;
1361 char sp_tq_name[32];
1362
1363 struct bxe_fastpath fp[MAX_RSS_CHAINS];
1364 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS];
1365
1366 device_t dev; /* parent device handle */
1367 uint8_t unit; /* driver instance number */
1368
1369 int pcie_bus; /* PCIe bus number */
1370 int pcie_device; /* PCIe device/slot number */
1371 int pcie_func; /* PCIe function number */
1372
1373 uint8_t pfunc_rel; /* function relative */
1374 uint8_t pfunc_abs; /* function absolute */
1375 uint8_t path_id; /* function absolute */
1376 #define SC_PATH(sc) (sc->path_id)
1377 #define SC_PORT(sc) (sc->pfunc_rel & 1)
1378 #define SC_FUNC(sc) (sc->pfunc_rel)
1379 #define SC_ABS_FUNC(sc) (sc->pfunc_abs)
1380 #define SC_VN(sc) (sc->pfunc_rel >> 1)
1381 #define SC_L_ID(sc) (SC_VN(sc) << 2)
1382 #define PORT_ID(sc) SC_PORT(sc)
1383 #define PATH_ID(sc) SC_PATH(sc)
1384 #define VNIC_ID(sc) SC_VN(sc)
1385 #define FUNC_ID(sc) SC_FUNC(sc)
1386 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)
1387 #define SC_FW_MB_IDX_VN(sc, vn) \
1388 (SC_PORT(sc) + (vn) * \
1389 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))
1390 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))
1391
1392 int if_capen; /* enabled interface capabilities */
1393
1394 struct bxe_devinfo devinfo;
1395 char fw_ver_str[32];
1396 char mf_mode_str[32];
1397 char pci_link_str[32];
1398
1399 const struct iro *iro_array;
1400
1401 #ifdef BXE_CORE_LOCK_SX
1402 struct sx core_sx;
1403 char core_sx_name[32];
1404 #else
1405 struct mtx core_mtx;
1406 char core_mtx_name[32];
1407 #endif
1408 struct mtx sp_mtx;
1409 char sp_mtx_name[32];
1410 struct mtx dmae_mtx;
1411 char dmae_mtx_name[32];
1412 struct mtx fwmb_mtx;
1413 char fwmb_mtx_name[32];
1414 struct mtx print_mtx;
1415 char print_mtx_name[32];
1416 struct mtx stats_mtx;
1417 char stats_mtx_name[32];
1418 struct mtx mcast_mtx;
1419 char mcast_mtx_name[32];
1420
1421 #ifdef BXE_CORE_LOCK_SX
1422 #define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx)
1423 #define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx)
1424 #define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx)
1425 #define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED)
1426 #else
1427 #define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx)
1428 #define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx)
1429 #define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx)
1430 #define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED)
1431 #endif
1432
1433 #define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx)
1434 #define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx)
1435 #define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED)
1436
1437 #define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx)
1438 #define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx)
1439 #define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED)
1440
1441 #define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx)
1442 #define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx)
1443 #define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED)
1444
1445 #define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx)
1446 #define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx)
1447 #define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED)
1448
1449 #define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx)
1450 #define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx)
1451 #define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED)
1452
1453 #define BXE_MCAST_LOCK(sc) mtx_lock(&sc->mcast_mtx);
1454 #define BXE_MCAST_UNLOCK(sc) mtx_unlock(&sc->mcast_mtx);
1455 #define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED)
1456
1457 int dmae_ready;
1458 #define DMAE_READY(sc) (sc->dmae_ready)
1459
1460 struct ecore_credit_pool_obj vlans_pool;
1461 struct ecore_credit_pool_obj macs_pool;
1462 struct ecore_rx_mode_obj rx_mode_obj;
1463 struct ecore_mcast_obj mcast_obj;
1464 struct ecore_rss_config_obj rss_conf_obj;
1465 struct ecore_func_sp_obj func_obj;
1466
1467 uint16_t fw_seq;
1468 uint16_t fw_drv_pulse_wr_seq;
1469 uint32_t func_stx;
1470
1471 struct elink_params link_params;
1472 struct elink_vars link_vars;
1473 uint32_t link_cnt;
1474 struct bxe_link_report_data last_reported_link;
1475 char mac_addr_str[32];
1476
1477 int last_reported_link_state;
1478
1479 int tx_ring_size;
1480 int rx_ring_size;
1481 int wol;
1482
1483 int is_leader;
1484 int recovery_state;
1485 #define BXE_RECOVERY_DONE 1
1486 #define BXE_RECOVERY_INIT 2
1487 #define BXE_RECOVERY_WAIT 3
1488 #define BXE_RECOVERY_FAILED 4
1489 #define BXE_RECOVERY_NIC_LOADING 5
1490
1491 #define BXE_ERR_TXQ_STUCK 0x1 /* Tx queue stuck detected by driver. */
1492 #define BXE_ERR_MISC 0x2 /* MISC ERR */
1493 #define BXE_ERR_PARITY 0x4 /* Parity error detected. */
1494 #define BXE_ERR_STATS_TO 0x8 /* Statistics timeout detected. */
1495 #define BXE_ERR_MC_ASSERT 0x10 /* MC assert attention received. */
1496 #define BXE_ERR_PANIC 0x20 /* Driver asserted. */
1497 #define BXE_ERR_MCP_ASSERT 0x40 /* MCP assert attention received. No Recovery*/
1498 #define BXE_ERR_GLOBAL 0x80 /* PCIe/PXP/IGU/MISC/NIG device blocks error- needs PCIe/Fundamental reset */
1499 uint32_t error_status;
1500
1501 uint32_t rx_mode;
1502 #define BXE_RX_MODE_NONE 0
1503 #define BXE_RX_MODE_NORMAL 1
1504 #define BXE_RX_MODE_ALLMULTI 2
1505 #define BXE_RX_MODE_PROMISC 3
1506 #define BXE_MAX_MULTICAST 64
1507
1508 struct bxe_port port;
1509
1510 struct cmng_init cmng;
1511
1512 /* user configs */
1513 int num_queues;
1514 int max_rx_bufs;
1515 int hc_rx_ticks;
1516 int hc_tx_ticks;
1517 int rx_budget;
1518 int max_aggregation_size;
1519 int mrrs;
1520 int autogreeen;
1521 #define AUTO_GREEN_HW_DEFAULT 0
1522 #define AUTO_GREEN_FORCE_ON 1
1523 #define AUTO_GREEN_FORCE_OFF 2
1524 int interrupt_mode;
1525 #define INTR_MODE_INTX 0
1526 #define INTR_MODE_MSI 1
1527 #define INTR_MODE_MSIX 2
1528 int udp_rss;
1529
1530 /* interrupt allocations */
1531 struct bxe_intr intr[MAX_RSS_CHAINS+1];
1532 int intr_count;
1533 uint8_t igu_dsb_id;
1534 uint8_t igu_base_sb;
1535 uint8_t igu_sb_cnt;
1536 //uint8_t min_msix_vec_cnt;
1537 uint32_t igu_base_addr;
1538 //bus_addr_t def_status_blk_mapping;
1539 uint8_t base_fw_ndsb;
1540 #define DEF_SB_IGU_ID 16
1541 #define DEF_SB_ID HC_SP_SB_ID
1542
1543 /* parent bus DMA tag */
1544 bus_dma_tag_t parent_dma_tag;
1545
1546 /* default status block */
1547 struct bxe_dma def_sb_dma;
1548 struct host_sp_status_block *def_sb;
1549 uint16_t def_idx;
1550 uint16_t def_att_idx;
1551 uint32_t attn_state;
1552 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1553
1554 /* general SP events - stats query, cfc delete, etc */
1555 #define HC_SP_INDEX_ETH_DEF_CONS 3
1556 /* EQ completions */
1557 #define HC_SP_INDEX_EQ_CONS 7
1558 /* FCoE L2 connection completions */
1559 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
1560 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
1561 /* iSCSI L2 */
1562 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
1563 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
1564
1565 /* event queue */
1566 struct bxe_dma eq_dma;
1567 union event_ring_elem *eq;
1568 uint16_t eq_prod;
1569 uint16_t eq_cons;
1570 uint16_t *eq_cons_sb;
1571 #define NUM_EQ_PAGES 1 /* must be a power of 2 */
1572 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1573 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1574 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1575 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1576 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1577 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1578 #define NEXT_EQ_IDX(x) \
1579 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \
1580 ((x) + 2) : ((x) + 1))
1581 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1582 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1583
1584 /* slow path */
1585 struct bxe_dma sp_dma;
1586 struct bxe_slowpath *sp;
1587 unsigned long sp_state;
1588
1589 /* slow path queue */
1590 struct bxe_dma spq_dma;
1591 struct eth_spe *spq;
1592 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1593 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1594 #define MAX_SPQ_PENDING 8
1595
1596 uint16_t spq_prod_idx;
1597 struct eth_spe *spq_prod_bd;
1598 struct eth_spe *spq_last_bd;
1599 uint16_t *dsb_sp_prod;
1600 //uint16_t *spq_hw_con;
1601 //uint16_t spq_left;
1602
1603 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */
1604 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */
1605
1606 /* fw decompression buffer */
1607 struct bxe_dma gz_buf_dma;
1608 void *gz_buf;
1609 z_streamp gz_strm;
1610 uint32_t gz_outlen;
1611 #define GUNZIP_BUF(sc) (sc->gz_buf)
1612 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
1613 #define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr)
1614 #define FW_BUF_SIZE 0x40000
1615
1616 const struct raw_op *init_ops;
1617 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */
1618 const uint32_t *init_data; /* data blob, 32 bit granularity */
1619 uint32_t init_mode_flags;
1620 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)
1621 /* PRAM blobs - raw data */
1622 const uint8_t *tsem_int_table_data;
1623 const uint8_t *tsem_pram_data;
1624 const uint8_t *usem_int_table_data;
1625 const uint8_t *usem_pram_data;
1626 const uint8_t *xsem_int_table_data;
1627 const uint8_t *xsem_pram_data;
1628 const uint8_t *csem_int_table_data;
1629 const uint8_t *csem_pram_data;
1630 #define INIT_OPS(sc) (sc->init_ops)
1631 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)
1632 #define INIT_DATA(sc) (sc->init_data)
1633 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
1634 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)
1635 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
1636 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)
1637 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
1638 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)
1639 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
1640 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)
1641
1642 /* ILT
1643 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1644 * context size we need 8 ILT entries.
1645 */
1646 #define ILT_MAX_L2_LINES 8
1647 struct hw_context context[ILT_MAX_L2_LINES];
1648 struct ecore_ilt *ilt;
1649 #define ILT_MAX_LINES 256
1650
1651 /* max supported number of RSS queues: IGU SBs minus one for CNIC */
1652 #define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))
1653 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */
1654 #if 1
1655 #define BXE_L2_MAX_CID(sc) \
1656 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1657 #else
1658 #define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \
1659 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc))
1660 #endif
1661 #if 1
1662 #define BXE_L2_CID_COUNT(sc) \
1663 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1664 #else
1665 #define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \
1666 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc))
1667 #endif
1668 #define L2_ILT_LINES(sc) \
1669 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS))
1670
1671 int qm_cid_count;
1672
1673 uint8_t dropless_fc;
1674
1675 /* total number of FW statistics requests */
1676 uint8_t fw_stats_num;
1677 /*
1678 * This is a memory buffer that will contain both statistics ramrod
1679 * request and data.
1680 */
1681 struct bxe_dma fw_stats_dma;
1682 /*
1683 * FW statistics request shortcut (points at the beginning of fw_stats
1684 * buffer).
1685 */
1686 int fw_stats_req_size;
1687 struct bxe_fw_stats_req *fw_stats_req;
1688 bus_addr_t fw_stats_req_mapping;
1689 /*
1690 * FW statistics data shortcut (points at the beginning of fw_stats
1691 * buffer + fw_stats_req_size).
1692 */
1693 int fw_stats_data_size;
1694 struct bxe_fw_stats_data *fw_stats_data;
1695 bus_addr_t fw_stats_data_mapping;
1696
1697 /* tracking a pending STAT_QUERY ramrod */
1698 uint16_t stats_pending;
1699 /* number of completed statistics ramrods */
1700 uint16_t stats_comp;
1701 uint16_t stats_counter;
1702 uint8_t stats_init;
1703 int stats_state;
1704
1705 struct bxe_eth_stats eth_stats;
1706 struct host_func_stats func_stats;
1707 struct bxe_eth_stats_old eth_stats_old;
1708 struct bxe_net_stats_old net_stats_old;
1709 struct bxe_fw_port_stats_old fw_stats_old;
1710
1711 struct dmae_cmd stats_dmae; /* used by dmae command loader */
1712 int executer_idx;
1713
1714 int mtu;
1715
1716 /* LLDP params */
1717 struct bxe_config_lldp_params lldp_config_params;
1718 /* DCB support on/off */
1719 int dcb_state;
1720 #define BXE_DCB_STATE_OFF 0
1721 #define BXE_DCB_STATE_ON 1
1722 /* DCBX engine mode */
1723 int dcbx_enabled;
1724 #define BXE_DCBX_ENABLED_OFF 0
1725 #define BXE_DCBX_ENABLED_ON_NEG_OFF 1
1726 #define BXE_DCBX_ENABLED_ON_NEG_ON 2
1727 #define BXE_DCBX_ENABLED_INVALID -1
1728 uint8_t dcbx_mode_uset;
1729 struct bxe_config_dcbx_params dcbx_config_params;
1730 struct bxe_dcbx_port_params dcbx_port_params;
1731 int dcb_version;
1732
1733 uint8_t cnic_support;
1734 uint8_t cnic_enabled;
1735 uint8_t cnic_loaded;
1736 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */
1737 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */
1738 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */
1739
1740 /* multiple tx classes of service */
1741 uint8_t max_cos;
1742 #define BXE_MAX_PRIORITY 8
1743 /* priority to cos mapping */
1744 uint8_t prio_to_cos[BXE_MAX_PRIORITY];
1745
1746 int panic;
1747
1748 struct cdev *ioctl_dev;
1749
1750 void *grc_dump;
1751 unsigned int trigger_grcdump;
1752 unsigned int grcdump_done;
1753 unsigned int grcdump_started;
1754 int bxe_pause_param;
1755 void *eeprom;
1756 }; /* struct bxe_softc */
1757
1758 /* IOCTL sub-commands for edebug and firmware upgrade */
1759 #define BXE_IOC_RD_NVRAM 1
1760 #define BXE_IOC_WR_NVRAM 2
1761 #define BXE_IOC_STATS_SHOW_NUM 3
1762 #define BXE_IOC_STATS_SHOW_STR 4
1763 #define BXE_IOC_STATS_SHOW_CNT 5
1764
1765 struct bxe_nvram_data {
1766 uint32_t op; /* ioctl sub-command */
1767 uint32_t offset;
1768 uint32_t len;
1769 uint32_t value[1]; /* variable */
1770 };
1771
1772 union bxe_stats_show_data {
1773 uint32_t op; /* ioctl sub-command */
1774
1775 struct {
1776 uint32_t num; /* return number of stats */
1777 uint32_t len; /* length of each string item */
1778 } desc;
1779
1780 /* variable length... */
1781 char str[1]; /* holds names of desc.num stats, each desc.len in length */
1782
1783 /* variable length... */
1784 uint64_t stats[1]; /* holds all stats */
1785 };
1786
1787 /* function init flags */
1788 #define FUNC_FLG_RSS 0x0001
1789 #define FUNC_FLG_STATS 0x0002
1790 /* FUNC_FLG_UNMATCHED 0x0004 */
1791 #define FUNC_FLG_TPA 0x0008
1792 #define FUNC_FLG_SPQ 0x0010
1793 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1794
1795 struct bxe_func_init_params {
1796 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
1797 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
1798 uint16_t func_flgs;
1799 uint16_t func_id; /* abs function id */
1800 uint16_t pf_id;
1801 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */
1802 };
1803
1804 /* memory resources reside at BARs 0, 2, 4 */
1805 /* Run `pciconf -lb` to see mappings */
1806 #define BAR0 0
1807 #define BAR1 2
1808 #define BAR2 4
1809
1810 #ifdef BXE_REG_NO_INLINE
1811
1812 uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset);
1813 uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset);
1814 uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset);
1815
1816 void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val);
1817 void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val);
1818 void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val);
1819
1820 #define REG_RD8(sc, offset) bxe_reg_read8(sc, offset)
1821 #define REG_RD16(sc, offset) bxe_reg_read16(sc, offset)
1822 #define REG_RD32(sc, offset) bxe_reg_read32(sc, offset)
1823
1824 #define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val)
1825 #define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val)
1826 #define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val)
1827
1828 #else /* not BXE_REG_NO_INLINE */
1829
1830 #define REG_WR8(sc, offset, val) \
1831 bus_space_write_1(sc->bar[BAR0].tag, \
1832 sc->bar[BAR0].handle, \
1833 offset, val)
1834
1835 #define REG_WR16(sc, offset, val) \
1836 bus_space_write_2(sc->bar[BAR0].tag, \
1837 sc->bar[BAR0].handle, \
1838 offset, val)
1839
1840 #define REG_WR32(sc, offset, val) \
1841 bus_space_write_4(sc->bar[BAR0].tag, \
1842 sc->bar[BAR0].handle, \
1843 offset, val)
1844
1845 #define REG_RD8(sc, offset) \
1846 bus_space_read_1(sc->bar[BAR0].tag, \
1847 sc->bar[BAR0].handle, \
1848 offset)
1849
1850 #define REG_RD16(sc, offset) \
1851 bus_space_read_2(sc->bar[BAR0].tag, \
1852 sc->bar[BAR0].handle, \
1853 offset)
1854
1855 #define REG_RD32(sc, offset) \
1856 bus_space_read_4(sc->bar[BAR0].tag, \
1857 sc->bar[BAR0].handle, \
1858 offset)
1859
1860 #endif /* BXE_REG_NO_INLINE */
1861
1862 #define REG_RD(sc, offset) REG_RD32(sc, offset)
1863 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)
1864
1865 #define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset)
1866 #define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val)
1867
1868 #define BXE_SP(sc, var) (&(sc)->sp->var)
1869 #define BXE_SP_MAPPING(sc, var) \
1870 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var))
1871
1872 #define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var)
1873 #define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
1874
1875 #define REG_RD_DMAE(sc, offset, valp, len32) \
1876 do { \
1877 bxe_read_dmae(sc, offset, len32); \
1878 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \
1879 } while (0)
1880
1881 #define REG_WR_DMAE(sc, offset, valp, len32) \
1882 do { \
1883 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \
1884 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \
1885 } while (0)
1886
1887 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \
1888 REG_WR_DMAE(sc, offset, valp, len32)
1889
1890 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \
1891 REG_RD_DMAE(sc, offset, valp, len32)
1892
1893 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
1894 do { \
1895 /* if (le32_swap) { */ \
1896 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \
1897 /* } */ \
1898 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \
1899 ecore_write_big_buf_wb(sc, addr, len32); \
1900 } while (0)
1901
1902 #define BXE_DB_MIN_SHIFT 3 /* 8 bytes */
1903 #define BXE_DB_SHIFT 7 /* 128 bytes */
1904 #if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT)
1905 #error "Minimum DB doorbell stride is 8"
1906 #endif
1907 #define DPM_TRIGGER_TYPE 0x40
1908 #define DOORBELL(sc, cid, val) \
1909 do { \
1910 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \
1911 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \
1912 (uint32_t)val); \
1913 } while(0)
1914
1915 #define SHMEM_ADDR(sc, field) \
1916 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))
1917 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
1918 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field))
1919 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
1920
1921 #define SHMEM2_ADDR(sc, field) \
1922 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))
1923 #define SHMEM2_HAS(sc, field) \
1924 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
1925 offsetof(struct shmem2_region, field)))
1926 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
1927 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
1928
1929 #define MFCFG_ADDR(sc, field) \
1930 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))
1931 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
1932 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field))
1933 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
1934
1935 /* DMAE command defines */
1936
1937 #define DMAE_TIMEOUT -1
1938 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1939 #define DMAE_NOT_RDY -3
1940 #define DMAE_PCI_ERR_FLAG 0x80000000
1941
1942 #define DMAE_SRC_PCI 0
1943 #define DMAE_SRC_GRC 1
1944
1945 #define DMAE_DST_NONE 0
1946 #define DMAE_DST_PCI 1
1947 #define DMAE_DST_GRC 2
1948
1949 #define DMAE_COMP_PCI 0
1950 #define DMAE_COMP_GRC 1
1951
1952 #define DMAE_COMP_REGULAR 0
1953 #define DMAE_COM_SET_ERR 1
1954
1955 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_CMD_SRC_SHIFT)
1956 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_CMD_SRC_SHIFT)
1957 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_CMD_DST_SHIFT)
1958 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_CMD_DST_SHIFT)
1959
1960 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_CMD_C_DST_SHIFT)
1961 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_CMD_C_DST_SHIFT)
1962
1963 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_CMD_ENDIANITY_SHIFT)
1964 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_CMD_ENDIANITY_SHIFT)
1965 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_CMD_ENDIANITY_SHIFT)
1966 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_CMD_ENDIANITY_SHIFT)
1967
1968 #define DMAE_CMD_PORT_0 0
1969 #define DMAE_CMD_PORT_1 DMAE_CMD_PORT
1970
1971 #define DMAE_SRC_PF 0
1972 #define DMAE_SRC_VF 1
1973
1974 #define DMAE_DST_PF 0
1975 #define DMAE_DST_VF 1
1976
1977 #define DMAE_C_SRC 0
1978 #define DMAE_C_DST 1
1979
1980 #define DMAE_LEN32_RD_MAX 0x80
1981 #define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000)
1982
1983 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */
1984
1985 #define MAX_DMAE_C_PER_PORT 8
1986 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
1987 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
1988
1989 static const uint32_t dmae_reg_go_c[] = {
1990 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
1991 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
1992 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
1993 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
1994 };
1995
1996 #define ATTN_NIG_FOR_FUNC (1L << 8)
1997 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1998 #define GPIO_2_FUNC (1L << 10)
1999 #define GPIO_3_FUNC (1L << 11)
2000 #define GPIO_4_FUNC (1L << 12)
2001 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2002 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2003 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2004 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2005 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2006 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2007 #define ATTN_HARD_WIRED_MASK 0xff00
2008 #define ATTENTION_ID 4
2009
2010 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
2011 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
2012
2013 #define MAX_IGU_ATTN_ACK_TO 100
2014
2015 #define STORM_ASSERT_ARRAY_SIZE 50
2016
2017 #define BXE_PMF_LINK_ASSERT(sc) \
2018 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))
2019
2020 #define BXE_MC_ASSERT_BITS \
2021 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2022 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2023 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2024 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2025
2026 #define BXE_MCP_ASSERT \
2027 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2028
2029 #define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2030 #define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2031 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2032 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2033 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2034 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2035 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2036
2037 #define MULTI_MASK 0x7f
2038
2039 #define PFS_PER_PORT(sc) \
2040 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)
2041 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)
2042
2043 #define FIRST_ABS_FUNC_IN_PORT(sc) \
2044 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \
2045 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))
2046
2047 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \
2048 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \
2049 (i) < MAX_FUNC_NUM; \
2050 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))
2051
2052 #define BXE_SWCID_SHIFT 17
2053 #define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1)
2054
2055 #define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK)
2056 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
2057
2058 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
2059 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
2060 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
2061 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
2062 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
2063
2064 /* must be used on a CID before placing it on a HW ring */
2065 #define HW_CID(sc, x) \
2066 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x))
2067
2068 #define SPEED_10 10
2069 #define SPEED_100 100
2070 #define SPEED_1000 1000
2071 #define SPEED_2500 2500
2072 #define SPEED_10000 10000
2073
2074 #define PCI_PM_D0 1
2075 #define PCI_PM_D3hot 2
2076
2077 #ifndef DUPLEX_UNKNOWN
2078 #define DUPLEX_UNKNOWN (0xff)
2079 #endif
2080
2081 #ifndef SPEED_UNKNOWN
2082 #define SPEED_UNKNOWN (-1)
2083 #endif
2084
2085 /* Enable or disable autonegotiation. */
2086 #define AUTONEG_DISABLE 0x00
2087 #define AUTONEG_ENABLE 0x01
2088
2089 /* Which connector port. */
2090 #define PORT_TP 0x00
2091 #define PORT_AUI 0x01
2092 #define PORT_MII 0x02
2093 #define PORT_FIBRE 0x03
2094 #define PORT_BNC 0x04
2095 #define PORT_DA 0x05
2096 #define PORT_NONE 0xef
2097 #define PORT_OTHER 0xff
2098
2099 int bxe_test_bit(int nr, volatile unsigned long * addr);
2100 void bxe_set_bit(unsigned int nr, volatile unsigned long * addr);
2101 void bxe_clear_bit(int nr, volatile unsigned long * addr);
2102 int bxe_test_and_set_bit(int nr, volatile unsigned long * addr);
2103 int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr);
2104 int bxe_cmpxchg(volatile int *addr, int old, int new);
2105
2106 void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr,
2107 uint32_t val);
2108 uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr);
2109
2110
2111 int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size,
2112 struct bxe_dma *dma, const char *msg);
2113 void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma);
2114
2115 uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
2116 uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode);
2117 uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type,
2118 uint8_t dst_type, uint8_t with_comp,
2119 uint8_t comp_type);
2120 void bxe_post_dmae(struct bxe_softc *sc, struct dmae_cmd *dmae, int idx);
2121 void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32);
2122 void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr,
2123 uint32_t dst_addr, uint32_t len32);
2124 void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr,
2125 uint32_t addr, uint32_t len);
2126
2127 void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt,
2128 uint32_t cid);
2129 void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id,
2130 uint8_t sb_index, uint8_t disable,
2131 uint16_t usec);
2132
2133 int bxe_sp_post(struct bxe_softc *sc, int command, int cid,
2134 uint32_t data_hi, uint32_t data_lo, int cmd_type);
2135
2136 void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id,
2137 uint8_t segment, uint16_t index, uint8_t op,
2138 uint8_t update);
2139
2140 void ecore_init_e1_firmware(struct bxe_softc *sc);
2141 void ecore_init_e1h_firmware(struct bxe_softc *sc);
2142 void ecore_init_e2_firmware(struct bxe_softc *sc);
2143
2144 void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr,
2145 size_t size, uint32_t *data);
2146
2147 /*********************/
2148 /* LOGGING AND DEBUG */
2149 /*********************/
2150
2151 /* debug logging codepaths */
2152 #define DBG_LOAD 0x00000001 /* load and unload */
2153 #define DBG_INTR 0x00000002 /* interrupt handling */
2154 #define DBG_SP 0x00000004 /* slowpath handling */
2155 #define DBG_STATS 0x00000008 /* stats updates */
2156 #define DBG_TX 0x00000010 /* packet transmit */
2157 #define DBG_RX 0x00000020 /* packet receive */
2158 #define DBG_PHY 0x00000040 /* phy/link handling */
2159 #define DBG_IOCTL 0x00000080 /* ioctl handling */
2160 #define DBG_MBUF 0x00000100 /* dumping mbuf info */
2161 #define DBG_REGS 0x00000200 /* register access */
2162 #define DBG_LRO 0x00000400 /* lro processing */
2163 #define DBG_ASSERT 0x80000000 /* debug assert */
2164 #define DBG_ALL 0xFFFFFFFF /* flying monkeys */
2165
2166 #define DBASSERT(sc, exp, msg) \
2167 do { \
2168 if (__predict_false(sc->debug & DBG_ASSERT)) { \
2169 if (__predict_false(!(exp))) { \
2170 panic msg; \
2171 } \
2172 } \
2173 } while (0)
2174
2175 /* log a debug message */
2176 #define BLOGD(sc, codepath, format, args...) \
2177 do { \
2178 if (__predict_false(sc->debug & (codepath))) { \
2179 device_printf((sc)->dev, \
2180 "%s(%s:%d) " format, \
2181 __FUNCTION__, \
2182 __FILE__, \
2183 __LINE__, \
2184 ## args); \
2185 } \
2186 } while(0)
2187
2188 /* log a info message */
2189 #define BLOGI(sc, format, args...) \
2190 do { \
2191 if (__predict_false(sc->debug)) { \
2192 device_printf((sc)->dev, \
2193 "%s(%s:%d) " format, \
2194 __FUNCTION__, \
2195 __FILE__, \
2196 __LINE__, \
2197 ## args); \
2198 } else { \
2199 device_printf((sc)->dev, \
2200 format, \
2201 ## args); \
2202 } \
2203 } while(0)
2204
2205 /* log a warning message */
2206 #define BLOGW(sc, format, args...) \
2207 do { \
2208 if (__predict_false(sc->debug)) { \
2209 device_printf((sc)->dev, \
2210 "%s(%s:%d) WARNING: " format, \
2211 __FUNCTION__, \
2212 __FILE__, \
2213 __LINE__, \
2214 ## args); \
2215 } else { \
2216 device_printf((sc)->dev, \
2217 "WARNING: " format, \
2218 ## args); \
2219 } \
2220 } while(0)
2221
2222 /* log a error message */
2223 #define BLOGE(sc, format, args...) \
2224 do { \
2225 if (__predict_false(sc->debug)) { \
2226 device_printf((sc)->dev, \
2227 "%s(%s:%d) ERROR: " format, \
2228 __FUNCTION__, \
2229 __FILE__, \
2230 __LINE__, \
2231 ## args); \
2232 } else { \
2233 device_printf((sc)->dev, \
2234 "ERROR: " format, \
2235 ## args); \
2236 } \
2237 } while(0)
2238
2239 #ifdef ECORE_STOP_ON_ERROR
2240
2241 #define bxe_panic(sc, msg) \
2242 do { \
2243 panic msg; \
2244 } while (0)
2245
2246 #else
2247
2248 #define bxe_panic(sc, msg) \
2249 device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__);
2250
2251 #endif
2252
2253 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
2254 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)
2255
2256 void bxe_dump_mem(struct bxe_softc *sc, char *tag,
2257 uint8_t *mem, uint32_t len);
2258 void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag,
2259 struct mbuf *m, uint8_t contents);
2260
2261 #define BXE_SET_FLOWID(m) M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE)
2262 #define BXE_VALID_FLOWID(m) (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
2263
2264 /***********/
2265 /* INLINES */
2266 /***********/
2267
2268 static inline uint32_t
reg_poll(struct bxe_softc * sc,uint32_t reg,uint32_t expected,int ms,int wait)2269 reg_poll(struct bxe_softc *sc,
2270 uint32_t reg,
2271 uint32_t expected,
2272 int ms,
2273 int wait)
2274 {
2275 uint32_t val;
2276
2277 do {
2278 val = REG_RD(sc, reg);
2279 if (val == expected) {
2280 break;
2281 }
2282 ms -= wait;
2283 DELAY(wait * 1000);
2284 } while (ms > 0);
2285
2286 return (val);
2287 }
2288
2289 static inline void
bxe_update_fp_sb_idx(struct bxe_fastpath * fp)2290 bxe_update_fp_sb_idx(struct bxe_fastpath *fp)
2291 {
2292 mb(); /* status block is written to by the chip */
2293 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
2294 }
2295
2296 static inline void
bxe_igu_ack_sb_gen(struct bxe_softc * sc,uint8_t igu_sb_id,uint8_t segment,uint16_t index,uint8_t op,uint8_t update,uint32_t igu_addr)2297 bxe_igu_ack_sb_gen(struct bxe_softc *sc,
2298 uint8_t igu_sb_id,
2299 uint8_t segment,
2300 uint16_t index,
2301 uint8_t op,
2302 uint8_t update,
2303 uint32_t igu_addr)
2304 {
2305 struct igu_regular cmd_data = {0};
2306
2307 cmd_data.sb_id_and_flags =
2308 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
2309 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
2310 (update << IGU_REGULAR_BUPDATE_SHIFT) |
2311 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
2312
2313 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n",
2314 cmd_data.sb_id_and_flags, igu_addr);
2315 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
2316
2317 /* Make sure that ACK is written */
2318 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0,
2319 BUS_SPACE_BARRIER_WRITE);
2320 mb();
2321 }
2322
2323 static inline void
bxe_hc_ack_sb(struct bxe_softc * sc,uint8_t sb_id,uint8_t storm,uint16_t index,uint8_t op,uint8_t update)2324 bxe_hc_ack_sb(struct bxe_softc *sc,
2325 uint8_t sb_id,
2326 uint8_t storm,
2327 uint16_t index,
2328 uint8_t op,
2329 uint8_t update)
2330 {
2331 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 +
2332 COMMAND_REG_INT_ACK);
2333 struct igu_ack_register igu_ack;
2334
2335 igu_ack.status_block_index = index;
2336 igu_ack.sb_id_and_flags =
2337 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2338 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2339 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2340 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2341
2342 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack));
2343
2344 /* Make sure that ACK is written */
2345 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0,
2346 BUS_SPACE_BARRIER_WRITE);
2347 mb();
2348 }
2349
2350 static inline void
bxe_ack_sb(struct bxe_softc * sc,uint8_t igu_sb_id,uint8_t storm,uint16_t index,uint8_t op,uint8_t update)2351 bxe_ack_sb(struct bxe_softc *sc,
2352 uint8_t igu_sb_id,
2353 uint8_t storm,
2354 uint16_t index,
2355 uint8_t op,
2356 uint8_t update)
2357 {
2358 if (sc->devinfo.int_block == INT_BLOCK_HC)
2359 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
2360 else {
2361 uint8_t segment;
2362 if (CHIP_INT_MODE_IS_BC(sc)) {
2363 segment = storm;
2364 } else if (igu_sb_id != sc->igu_dsb_id) {
2365 segment = IGU_SEG_ACCESS_DEF;
2366 } else if (storm == ATTENTION_ID) {
2367 segment = IGU_SEG_ACCESS_ATTN;
2368 } else {
2369 segment = IGU_SEG_ACCESS_DEF;
2370 }
2371 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
2372 }
2373 }
2374
2375 static inline uint16_t
bxe_hc_ack_int(struct bxe_softc * sc)2376 bxe_hc_ack_int(struct bxe_softc *sc)
2377 {
2378 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 +
2379 COMMAND_REG_SIMD_MASK);
2380 uint32_t result = REG_RD(sc, hc_addr);
2381
2382 mb();
2383 return (result);
2384 }
2385
2386 static inline uint16_t
bxe_igu_ack_int(struct bxe_softc * sc)2387 bxe_igu_ack_int(struct bxe_softc *sc)
2388 {
2389 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
2390 uint32_t result = REG_RD(sc, igu_addr);
2391
2392 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n",
2393 result, igu_addr);
2394
2395 mb();
2396 return (result);
2397 }
2398
2399 static inline uint16_t
bxe_ack_int(struct bxe_softc * sc)2400 bxe_ack_int(struct bxe_softc *sc)
2401 {
2402 mb();
2403 if (sc->devinfo.int_block == INT_BLOCK_HC) {
2404 return (bxe_hc_ack_int(sc));
2405 } else {
2406 return (bxe_igu_ack_int(sc));
2407 }
2408 }
2409
2410 static inline int
func_by_vn(struct bxe_softc * sc,int vn)2411 func_by_vn(struct bxe_softc *sc,
2412 int vn)
2413 {
2414 return (2 * vn + SC_PORT(sc));
2415 }
2416
2417 /*
2418 * Statistics ID are global per chip/path, while Client IDs for E1x
2419 * are per port.
2420 */
2421 static inline uint8_t
bxe_stats_id(struct bxe_fastpath * fp)2422 bxe_stats_id(struct bxe_fastpath *fp)
2423 {
2424 struct bxe_softc *sc = fp->sc;
2425
2426 if (!CHIP_IS_E1x(sc)) {
2427 return (fp->cl_id);
2428 }
2429
2430 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x);
2431 }
2432
2433 #endif /* __BXE_H__ */
2434
2435