1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 37 #include "mpc.h" 38 #endif 39 40 #define MAX_CLOCK_SOURCES 7 41 42 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 43 uint32_t controller_id); 44 45 #include "grph_object_id.h" 46 #include "link_encoder.h" 47 #include "stream_encoder.h" 48 #include "clock_source.h" 49 #include "audio.h" 50 #include "dm_pp_smu.h" 51 52 53 /************ link *****************/ 54 struct link_init_data { 55 const struct dc *dc; 56 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 57 uint32_t connector_index; /* this will be mapped to the HPD pins */ 58 uint32_t link_index; /* this is mapped to DAL display_index 59 TODO: remove it when DC is complete. */ 60 }; 61 62 enum { 63 FREE_ACQUIRED_RESOURCE = 0, 64 KEEP_ACQUIRED_RESOURCE = 1, 65 }; 66 67 struct dc_link *link_create(const struct link_init_data *init_params); 68 void link_destroy(struct dc_link **link); 69 70 enum dc_status dc_link_validate_mode_timing( 71 const struct dc_stream_state *stream, 72 struct dc_link *link, 73 const struct dc_crtc_timing *timing); 74 75 void core_link_resume(struct dc_link *link); 76 77 void core_link_enable_stream( 78 struct dc_state *state, 79 struct pipe_ctx *pipe_ctx); 80 81 void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option); 82 83 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 84 /********** DAL Core*********************/ 85 #include "display_clock.h" 86 #include "transform.h" 87 #include "dpp.h" 88 89 struct resource_pool; 90 struct dc_state; 91 struct resource_context; 92 93 struct resource_funcs { 94 void (*destroy)(struct resource_pool **pool); 95 void (*link_init)(struct dc_link *link); 96 struct link_encoder *(*link_enc_create)( 97 const struct encoder_init_data *init); 98 99 bool (*validate_bandwidth)( 100 struct dc *dc, 101 struct dc_state *context); 102 103 enum dc_status (*validate_global)( 104 struct dc *dc, 105 struct dc_state *context); 106 107 struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 108 struct dc_state *context, 109 const struct resource_pool *pool, 110 struct dc_stream_state *stream); 111 112 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 113 114 enum dc_status (*add_stream_to_ctx)( 115 struct dc *dc, 116 struct dc_state *new_ctx, 117 struct dc_stream_state *dc_stream); 118 119 enum dc_status (*remove_stream_from_ctx)( 120 struct dc *dc, 121 struct dc_state *new_ctx, 122 struct dc_stream_state *stream); 123 }; 124 125 struct audio_support{ 126 bool dp_audio; 127 bool hdmi_audio_on_dongle; 128 bool hdmi_audio_native; 129 }; 130 131 #define NO_UNDERLAY_PIPE -1 132 133 struct resource_pool { 134 struct mem_input *mis[MAX_PIPES]; 135 struct hubp *hubps[MAX_PIPES]; 136 struct input_pixel_processor *ipps[MAX_PIPES]; 137 struct transform *transforms[MAX_PIPES]; 138 struct dpp *dpps[MAX_PIPES]; 139 struct output_pixel_processor *opps[MAX_PIPES]; 140 struct timing_generator *timing_generators[MAX_PIPES]; 141 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 142 struct aux_engine *engines[MAX_PIPES]; 143 struct hubbub *hubbub; 144 struct mpc *mpc; 145 struct pp_smu_funcs_rv *pp_smu; 146 struct pp_smu_display_requirement_rv pp_smu_req; 147 148 unsigned int pipe_count; 149 unsigned int underlay_pipe_index; 150 unsigned int stream_enc_count; 151 unsigned int ref_clock_inKhz; 152 unsigned int timing_generator_count; 153 154 /* 155 * reserved clock source for DP 156 */ 157 struct clock_source *dp_clock_source; 158 159 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 160 unsigned int clk_src_count; 161 162 struct audio *audios[MAX_AUDIOS]; 163 unsigned int audio_count; 164 struct audio_support audio_support; 165 166 struct dccg *dccg; 167 struct irq_service *irqs; 168 169 struct abm *abm; 170 struct dmcu *dmcu; 171 172 const struct resource_funcs *funcs; 173 const struct resource_caps *res_cap; 174 }; 175 176 struct dcn_fe_clocks { 177 int dppclk_khz; 178 }; 179 180 struct dcn_fe_bandwidth { 181 struct dcn_fe_clocks calc; 182 struct dcn_fe_clocks cur; 183 }; 184 185 struct stream_resource { 186 struct output_pixel_processor *opp; 187 struct timing_generator *tg; 188 struct stream_encoder *stream_enc; 189 struct audio *audio; 190 191 struct pixel_clk_params pix_clk_params; 192 struct encoder_info_frame encoder_info_frame; 193 194 struct abm *abm; 195 }; 196 197 struct plane_resource { 198 struct scaler_data scl_data; 199 struct hubp *hubp; 200 struct mem_input *mi; 201 struct input_pixel_processor *ipp; 202 struct transform *xfm; 203 struct dpp *dpp; 204 uint8_t mpcc_inst; 205 206 struct dcn_fe_bandwidth bw; 207 }; 208 209 struct pipe_ctx { 210 struct dc_plane_state *plane_state; 211 struct dc_stream_state *stream; 212 213 struct plane_resource plane_res; 214 struct stream_resource stream_res; 215 216 struct clock_source *clock_source; 217 218 struct pll_settings pll_settings; 219 220 uint8_t pipe_idx; 221 222 struct pipe_ctx *top_pipe; 223 struct pipe_ctx *bottom_pipe; 224 225 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 226 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 227 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 228 struct _vcs_dpi_display_rq_regs_st rq_regs; 229 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 230 #endif 231 }; 232 233 struct resource_context { 234 struct pipe_ctx pipe_ctx[MAX_PIPES]; 235 bool is_stream_enc_acquired[MAX_PIPES * 2]; 236 bool is_audio_acquired[MAX_PIPES]; 237 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 238 uint8_t dp_clock_source_ref_count; 239 }; 240 241 struct dce_bw_output { 242 bool cpuc_state_change_enable; 243 bool cpup_state_change_enable; 244 bool stutter_mode_enable; 245 bool nbp_state_change_enable; 246 bool all_displays_in_sync; 247 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 248 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 249 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 250 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 251 int sclk_khz; 252 int sclk_deep_sleep_khz; 253 int yclk_khz; 254 int dispclk_khz; 255 int blackout_recovery_time_us; 256 }; 257 258 struct dcn_bw_output { 259 struct dc_clocks clk; 260 struct dcn_watermark_set watermarks; 261 }; 262 263 union bw_context { 264 struct dcn_bw_output dcn; 265 struct dce_bw_output dce; 266 }; 267 268 struct dc_state { 269 struct dc_stream_state *streams[MAX_PIPES]; 270 struct dc_stream_status stream_status[MAX_PIPES]; 271 uint8_t stream_count; 272 273 struct resource_context res_ctx; 274 275 /* The output from BW and WM calculations. */ 276 union bw_context bw; 277 278 /* Note: these are big structures, do *not* put on stack! */ 279 struct dm_pp_display_configuration pp_display_cfg; 280 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 281 struct dcn_bw_internal_vars dcn_bw_vars; 282 #endif 283 284 struct dccg *dis_clk; 285 286 struct kref refcount; 287 }; 288 289 #endif /* _CORE_TYPES_H_ */ 290