1 /* $OpenBSD: ncrreg.h,v 1.2 2001/11/18 20:55:42 deraadt Exp $ */ 2 /* $NetBSD: ncrreg.h,v 1.14 1997/09/23 02:27:46 perry Exp $ */ 3 4 /************************************************************************** 5 ** 6 ** Id: ncrreg.h,v 1.11 1997/08/31 19:42:31 se Exp 7 ** 8 ** Device driver for the NCR 53C810 PCI-SCSI-Controller. 9 ** 10 ** FreeBSD / NetBSD / OpenBSD 11 ** 12 **------------------------------------------------------------------------- 13 ** 14 ** Written for 386bsd and FreeBSD by 15 ** wolf@cologne.de Wolfgang Stanglmeier 16 ** se@mi.Uni-Koeln.de Stefan Esser 17 ** 18 ** Ported to NetBSD by 19 ** mycroft@gnu.ai.mit.edu 20 ** 21 **------------------------------------------------------------------------- 22 ** 23 ** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 24 ** 25 ** Redistribution and use in source and binary forms, with or without 26 ** modification, are permitted provided that the following conditions 27 ** are met: 28 ** 1. Redistributions of source code must retain the above copyright 29 ** notice, this list of conditions and the following disclaimer. 30 ** 2. Redistributions in binary form must reproduce the above copyright 31 ** notice, this list of conditions and the following disclaimer in the 32 ** documentation and/or other materials provided with the distribution. 33 ** 3. The name of the author may not be used to endorse or promote products 34 ** derived from this software without specific prior written permission. 35 ** 36 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 37 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 38 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 39 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 40 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 41 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 42 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 43 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 44 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 45 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 46 ** 47 *************************************************************************** 48 */ 49 50 #ifndef __NCR_REG_H__ 51 #define __NCR_REG_H__ 52 53 /*========================================================== 54 ** 55 ** OS dependencies. 56 ** 57 **========================================================== 58 */ 59 60 #ifdef __OpenBSD__ 61 #define ISSCRIPTRAMMAPPED(np) (np->scriptmapped) 62 #else /*__OpenBSD__*/ 63 #define ISSCRIPTRAMMAPPED(np) (np->vaddr2) 64 #endif /*__OpenBSD__*/ 65 66 /*----------------------------------------------------------------- 67 ** 68 ** The ncr 53c810 register structure. 69 ** 70 **----------------------------------------------------------------- 71 */ 72 73 struct ncr_reg { 74 /*00*/ u_int8_t nc_scntl0; /* full arb., ena parity, par->ATN */ 75 76 /*01*/ u_int8_t nc_scntl1; /* no reset */ 77 #define ISCON 0x10 /* connected to scsi */ 78 #define CRST 0x08 /* force reset */ 79 80 /*02*/ u_int8_t nc_scntl2; /* no disconnect expected */ 81 #define SDU 0x80 /* cmd: disconnect will raise error */ 82 #define CHM 0x40 /* sta: chained mode */ 83 #define WSS 0x08 /* sta: wide scsi send [W]*/ 84 #define WSR 0x01 /* sta: wide scsi received [W]*/ 85 86 /*03*/ u_int8_t nc_scntl3; /* cnf system clock dependent */ 87 #define EWS 0x08 /* cmd: enable wide scsi [W]*/ 88 89 /*04*/ u_int8_t nc_scid; /* cnf host adapter scsi address */ 90 #define RRE 0x40 /* r/w:e enable response to resel. */ 91 #define SRE 0x20 /* r/w:e enable response to select */ 92 93 /*05*/ u_int8_t nc_sxfer; /* ### Sync speed and count */ 94 95 /*06*/ u_int8_t nc_sdid; /* ### Destination-ID */ 96 97 /*07*/ u_int8_t nc_gpreg; /* ??? IO-Pins */ 98 99 /*08*/ u_int8_t nc_sfbr; /* ### First byte in phase */ 100 101 /*09*/ u_int8_t nc_socl; 102 #define CREQ 0x80 /* r/w: SCSI-REQ */ 103 #define CACK 0x40 /* r/w: SCSI-ACK */ 104 #define CBSY 0x20 /* r/w: SCSI-BSY */ 105 #define CSEL 0x10 /* r/w: SCSI-SEL */ 106 #define CATN 0x08 /* r/w: SCSI-ATN */ 107 #define CMSG 0x04 /* r/w: SCSI-MSG */ 108 #define CC_D 0x02 /* r/w: SCSI-C_D */ 109 #define CI_O 0x01 /* r/w: SCSI-I_O */ 110 111 /*0a*/ u_int8_t nc_ssid; 112 113 /*0b*/ u_int8_t nc_sbcl; 114 115 /*0c*/ u_int8_t nc_dstat; 116 #define DFE 0x80 /* sta: dma fifo empty */ 117 #define MDPE 0x40 /* int: master data parity error */ 118 #define BF 0x20 /* int: script: bus fault */ 119 #define ABRT 0x10 /* int: script: command aborted */ 120 #define SSI 0x08 /* int: script: single step */ 121 #define SIR 0x04 /* int: script: interrupt instruct. */ 122 #define IID 0x01 /* int: script: illegal instruct. */ 123 124 /*0d*/ u_int8_t nc_sstat0; 125 #define ILF 0x80 /* sta: data in SIDL register lsb */ 126 #define ORF 0x40 /* sta: data in SODR register lsb */ 127 #define OLF 0x20 /* sta: data in SODL register lsb */ 128 #define AIP 0x10 /* sta: arbitration in progress */ 129 #define LOA 0x08 /* sta: arbitration lost */ 130 #define WOA 0x04 /* sta: arbitration won */ 131 #define IRST 0x02 /* sta: scsi reset signal */ 132 #define SDP 0x01 /* sta: scsi parity signal */ 133 134 /*0e*/ u_int8_t nc_sstat1; 135 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ 136 137 /*0f*/ u_int8_t nc_sstat2; 138 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ 139 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ 140 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ 141 #define LDSC 0x02 /* sta: disconnect & reconnect */ 142 143 /*10*/ u_int32_t nc_dsa; /* --> Base page */ 144 145 /*14*/ u_int8_t nc_istat; /* --> Main Command and status */ 146 #define CABRT 0x80 /* cmd: abort current operation */ 147 #define SRST 0x40 /* mod: reset chip */ 148 #define SIGP 0x20 /* r/w: message from host to ncr */ 149 #define SEM 0x10 /* r/w: message between host + ncr */ 150 #define CON 0x08 /* sta: connected to scsi */ 151 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ 152 #define SIP 0x02 /* sta: scsi-interrupt */ 153 #define DIP 0x01 /* sta: host/script interrupt */ 154 155 /*15*/ u_int8_t nc_15_; 156 /*16*/ u_int8_t nc_16_; 157 /*17*/ u_int8_t nc_17_; 158 159 /*18*/ u_int8_t nc_ctest0; 160 /*19*/ u_int8_t nc_ctest1; 161 162 /*1a*/ u_int8_t nc_ctest2; 163 #define CSIGP 0x40 164 165 /*1b*/ u_int8_t nc_ctest3; 166 #define FLF 0x08 /* cmd: flush dma fifo */ 167 #define CLF 0x04 /* cmd: clear dma fifo */ 168 #define FM 0x02 /* mod: fetch pin mode */ 169 #define WRIE 0x01 /* mod: write and invalidate enable */ 170 171 /*1c*/ u_int32_t nc_temp; /* ### Temporary stack */ 172 173 /*20*/ u_int8_t nc_dfifo; 174 /*21*/ u_int8_t nc_ctest4; 175 #define BDIS 0x80 /* mod: burst disable */ 176 #define MPEE 0x08 /* mod: master parity error enable */ 177 178 /*22*/ u_int8_t nc_ctest5; 179 #define DFS 0x20 /* mod: dma fifo size */ 180 /*23*/ u_int8_t nc_ctest6; 181 182 /*24*/ u_int32_t nc_dbc; /* ### Byte count and command */ 183 /*28*/ u_int32_t nc_dnad; /* ### Next command register */ 184 /*2c*/ u_int32_t nc_dsp; /* --> Script Pointer */ 185 /*30*/ u_int32_t nc_dsps; /* --> Script pointer save/opcode#2 */ 186 /*34*/ u_int32_t nc_scratcha; /* ??? Temporary register a */ 187 188 /*38*/ u_int8_t nc_dmode; 189 #define BL_2 0x80 /* mod: burst length shift value +2 */ 190 #define BL_1 0x40 /* mod: burst length shift value +1 */ 191 #define ERL 0x08 /* mod: enable read line */ 192 #define ERMP 0x04 /* mod: enable read multiple */ 193 #define BOF 0x02 /* mod: burst op code fetch */ 194 195 /*39*/ u_int8_t nc_dien; 196 /*3a*/ u_int8_t nc_dwt; 197 198 /*3b*/ u_int8_t nc_dcntl; /* --> Script execution control */ 199 #define CLSE 0x80 /* mod: cache line size enable */ 200 #define PFF 0x40 /* cmd: pre-fetch flush */ 201 #define PFEN 0x20 /* mod: pre-fetch enable */ 202 #define SSM 0x10 /* mod: single step mode */ 203 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ 204 #define STD 0x04 /* cmd: start dma mode */ 205 #define IRQD 0x02 /* mod: irq disable */ 206 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ 207 208 /*3c*/ u_int32_t nc_adder; 209 210 /*40*/ u_int16_t nc_sien; /* -->: interrupt enable */ 211 /*42*/ u_int16_t nc_sist; /* <--: interrupt status */ 212 #define STO 0x0400/* sta: timeout (select) */ 213 #define GEN 0x0200/* sta: timeout (general) */ 214 #define HTH 0x0100/* sta: timeout (handshake) */ 215 #define MA 0x80 /* sta: phase mismatch */ 216 #define CMP 0x40 /* sta: arbitration complete */ 217 #define SEL 0x20 /* sta: selected by another device */ 218 #define RSL 0x10 /* sta: reselected by another device*/ 219 #define SGE 0x08 /* sta: gross error (over/underflow)*/ 220 #define UDC 0x04 /* sta: unexpected disconnect */ 221 #define RST 0x02 /* sta: scsi bus reset detected */ 222 #define PAR 0x01 /* sta: scsi parity error */ 223 224 /*44*/ u_int8_t nc_slpar; 225 /*45*/ u_int8_t nc_swide; 226 /*46*/ u_int8_t nc_macntl; 227 /*47*/ u_int8_t nc_gpcntl; 228 /*48*/ u_int8_t nc_stime0; /* cmd: timeout for select&handshake*/ 229 /*49*/ u_int8_t nc_stime1; /* cmd: timeout user defined */ 230 /*4a*/ u_int16_t nc_respid; /* sta: Reselect-IDs */ 231 232 /*4c*/ u_int8_t nc_stest0; 233 234 /*4d*/ u_int8_t nc_stest1; 235 #define DBLEN 0x08 /* clock doubler running */ 236 #define DBLSEL 0x04 /* clock doubler selected */ 237 238 /*4e*/ u_int8_t nc_stest2; 239 #define ROF 0x40 /* reset scsi offset (after gross error!) */ 240 #define EXT 0x02 /* extended filtering */ 241 242 /*4f*/ u_int8_t nc_stest3; 243 #define TE 0x80 /* c: tolerAnt enable */ 244 #define HSC 0x20 /* c: Halt SCSI Clock */ 245 #define CSF 0x02 /* c: clear scsi fifo */ 246 247 /*50*/ u_int16_t nc_sidl; /* Lowlevel: latched from scsi data */ 248 /*52*/ u_int8_t nc_stest4; 249 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ 250 #define SMODE_HVD 0x40 /* High Voltage Differential */ 251 #define SMODE_SE 0x80 /* Single Ended */ 252 #define SMODE_LVD 0xc0 /* Low Voltage Differential */ 253 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ 254 255 /*53*/ u_int8_t nc_53_; 256 /*54*/ u_int16_t nc_sodl; /* Lowlevel: data out to scsi data */ 257 /*56*/ u_int16_t nc_56_; 258 /*58*/ u_int16_t nc_sbdl; /* Lowlevel: data from scsi data */ 259 /*5a*/ u_int16_t nc_5a_; 260 /*5c*/ u_int8_t nc_scr0; /* Working register B */ 261 /*5d*/ u_int8_t nc_scr1; /* */ 262 /*5e*/ u_int8_t nc_scr2; /* */ 263 /*5f*/ u_int8_t nc_scr3; /* */ 264 /*60*/ 265 }; 266 267 /*----------------------------------------------------------- 268 ** 269 ** Utility macros for the script. 270 ** 271 **----------------------------------------------------------- 272 */ 273 274 #define REGJ(p,r) (offsetof(struct ncr_reg, p ## r)) 275 #define REG(r) REGJ (nc_, r) 276 277 #ifndef TARGET_MODE 278 #define TARGET_MODE 0 279 #endif 280 281 typedef u_int32_t ncrcmd; 282 283 #if BYTE_ORDER == BIG_ENDIAN 284 #define SCR_BO(x) (((x) >> 24) | (((x) >> 8) & 0xff00) | \ 285 ((x) << 24) | (((x) & 0xff00) << 8)) 286 #else 287 #define SCR_BO(x) (x) 288 #endif 289 290 /*----------------------------------------------------------- 291 ** 292 ** SCSI phases 293 ** 294 **----------------------------------------------------------- 295 */ 296 297 #define SCR_DATA_OUT 0x00000000 298 #define SCR_DATA_IN 0x01000000 299 #define SCR_COMMAND 0x02000000 300 #define SCR_STATUS 0x03000000 301 #define SCR_ILG_OUT 0x04000000 302 #define SCR_ILG_IN 0x05000000 303 #define SCR_MSG_OUT 0x06000000 304 #define SCR_MSG_IN 0x07000000 305 306 /*----------------------------------------------------------- 307 ** 308 ** Data transfer via SCSI. 309 ** 310 **----------------------------------------------------------- 311 ** 312 ** MOVE_ABS (LEN) 313 ** <<start address>> 314 ** 315 ** MOVE_IND (LEN) 316 ** <<dnad_offset>> 317 ** 318 ** MOVE_TBL 319 ** <<dnad_offset>> 320 ** 321 **----------------------------------------------------------- 322 */ 323 324 #define SCR_MOVE_ABS(l) ((0x08000000 ^ (TARGET_MODE << 1ul)) | (l)) 325 #define SCR_MOVE_IND(l) ((0x28000000 ^ (TARGET_MODE << 1ul)) | (l)) 326 #define SCR_MOVE_TBL (0x18000000 ^ (TARGET_MODE << 1ul)) 327 328 struct scr_tblmove { 329 u_int32_t size; 330 u_int32_t addr; 331 }; 332 333 /*----------------------------------------------------------- 334 ** 335 ** Selection 336 ** 337 **----------------------------------------------------------- 338 ** 339 ** SEL_ABS | SCR_ID (0..7) [ | REL_JMP] 340 ** <<alternate_address>> 341 ** 342 ** SEL_TBL | << dnad_offset>> [ | REL_JMP] 343 ** <<alternate_address>> 344 ** 345 **----------------------------------------------------------- 346 */ 347 348 #define SCR_SEL_ABS 0x40000000 349 #define SCR_SEL_ABS_ATN 0x41000000 350 #define SCR_SEL_TBL 0x42000000 351 #define SCR_SEL_TBL_ATN 0x43000000 352 353 struct scr_tblsel { 354 u_int8_t sel_0; 355 u_int8_t sel_sxfer; 356 u_int8_t sel_id; 357 u_int8_t sel_scntl3; 358 }; 359 360 #define SCR_JMP_REL 0x04000000 361 #define SCR_ID(id) (((u_int32_t)(id)) << 16) 362 363 /*----------------------------------------------------------- 364 ** 365 ** Waiting for Disconnect or Reselect 366 ** 367 **----------------------------------------------------------- 368 ** 369 ** WAIT_DISC 370 ** dummy: <<alternate_address>> 371 ** 372 ** WAIT_RESEL 373 ** <<alternate_address>> 374 ** 375 **----------------------------------------------------------- 376 */ 377 378 #define SCR_WAIT_DISC 0x48000000 379 #define SCR_WAIT_RESEL 0x50000000 380 381 /*----------------------------------------------------------- 382 ** 383 ** Bit Set / Reset 384 ** 385 **----------------------------------------------------------- 386 ** 387 ** SET (flags {|.. }) 388 ** 389 ** CLR (flags {|.. }) 390 ** 391 **----------------------------------------------------------- 392 */ 393 394 #define SCR_SET(f) (0x58000000 | (f)) 395 #define SCR_CLR(f) (0x60000000 | (f)) 396 397 #define SCR_CARRY 0x00000400 398 #define SCR_TRG 0x00000200 399 #define SCR_ACK 0x00000040 400 #define SCR_ATN 0x00000008 401 402 403 /*----------------------------------------------------------- 404 ** 405 ** Memory to memory move 406 ** 407 **----------------------------------------------------------- 408 ** 409 ** COPY (bytecount) 410 ** << source_address >> 411 ** << destination_address >> 412 ** 413 ** SCR_COPY sets the NO FLUSH option by default. 414 ** SCR_COPY_F does not set this option. 415 ** 416 ** For chips which do not support this option, 417 ** ncr_copy_and_bind() will remove this bit. 418 **----------------------------------------------------------- 419 */ 420 421 #define SCR_NO_FLUSH 0x01000000 422 423 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) 424 #define SCR_COPY_F(n) (0xc0000000 | (n)) 425 426 427 /*----------------------------------------------------------- 428 ** 429 ** Register move and binary operations 430 ** 431 **----------------------------------------------------------- 432 ** 433 ** SFBR_REG (reg, op, data) reg = SFBR op data 434 ** << 0 >> 435 ** 436 ** REG_SFBR (reg, op, data) SFBR = reg op data 437 ** << 0 >> 438 ** 439 ** REG_REG (reg, op, data) reg = reg op data 440 ** << 0 >> 441 ** 442 **----------------------------------------------------------- 443 */ 444 445 #define SCR_REG_OFS(ofs) ((ofs) << 16ul) 446 447 #define SCR_SFBR_REG(reg,op,data) \ 448 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul)) 449 450 #define SCR_REG_SFBR(reg,op,data) \ 451 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul)) 452 453 #define SCR_REG_REG(reg,op,data) \ 454 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul)) 455 456 457 #define SCR_LOAD 0x00000000 458 #define SCR_SHL 0x01000000 459 #define SCR_OR 0x02000000 460 #define SCR_XOR 0x03000000 461 #define SCR_AND 0x04000000 462 #define SCR_SHR 0x05000000 463 #define SCR_ADD 0x06000000 464 #define SCR_ADDC 0x07000000 465 466 /*----------------------------------------------------------- 467 ** 468 ** FROM_REG (reg) reg = SFBR 469 ** << 0 >> 470 ** 471 ** TO_REG (reg) SFBR = reg 472 ** << 0 >> 473 ** 474 ** LOAD_REG (reg, data) reg = <data> 475 ** << 0 >> 476 ** 477 ** LOAD_SFBR(data) SFBR = <data> 478 ** << 0 >> 479 ** 480 **----------------------------------------------------------- 481 */ 482 483 #define SCR_FROM_REG(reg) \ 484 SCR_REG_SFBR(reg,SCR_OR,0) 485 486 #define SCR_TO_REG(reg) \ 487 SCR_SFBR_REG(reg,SCR_OR,0) 488 489 #define SCR_LOAD_REG(reg,data) \ 490 SCR_REG_REG(reg,SCR_LOAD,data) 491 492 #define SCR_LOAD_SFBR(data) \ 493 (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) 494 495 /*----------------------------------------------------------- 496 ** 497 ** Waiting for Disconnect or Reselect 498 ** 499 **----------------------------------------------------------- 500 ** 501 ** JUMP [ | IFTRUE/IFFALSE ( ... ) ] 502 ** <<address>> 503 ** 504 ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] 505 ** <<distance>> 506 ** 507 ** CALL [ | IFTRUE/IFFALSE ( ... ) ] 508 ** <<address>> 509 ** 510 ** CALLR [ | IFTRUE/IFFALSE ( ... ) ] 511 ** <<distance>> 512 ** 513 ** RETURN [ | IFTRUE/IFFALSE ( ... ) ] 514 ** <<dummy>> 515 ** 516 ** INT [ | IFTRUE/IFFALSE ( ... ) ] 517 ** <<ident>> 518 ** 519 ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] 520 ** <<ident>> 521 ** 522 ** Conditions: 523 ** WHEN (phase) 524 ** IF (phase) 525 ** CARRY 526 ** DATA (data, mask) 527 ** 528 **----------------------------------------------------------- 529 */ 530 531 #define SCR_NO_OP 0x80000000 532 #define SCR_JUMP 0x80080000 533 #define SCR_JUMPR 0x80880000 534 #define SCR_CALL 0x88080000 535 #define SCR_CALLR 0x88880000 536 #define SCR_RETURN 0x90080000 537 #define SCR_INT 0x98080000 538 #define SCR_INT_FLY 0x98180000 539 540 #define IFFALSE(arg) (0x00080000 | (arg)) 541 #define IFTRUE(arg) (0x00000000 | (arg)) 542 543 #define WHEN(phase) (0x00030000 | (phase)) 544 #define IF(phase) (0x00020000 | (phase)) 545 546 #define DATA(D) (0x00040000 | ((D) & 0xff)) 547 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) 548 549 #define CARRYSET (0x00200000) 550 551 /*----------------------------------------------------------- 552 ** 553 ** SCSI constants. 554 ** 555 **----------------------------------------------------------- 556 */ 557 558 /* 559 ** Messages 560 */ 561 #ifdef __OpenBSD__ 562 #include <scsi/scsi_message.h> 563 564 #define M_COMPLETE MSG_CMDCOMPLETE 565 #define M_EXTENDED MSG_EXTENDED 566 #define M_SAVE_DP MSG_SAVEDATAPOINTER 567 #define M_RESTORE_DP MSG_RESTOREPOINTERS 568 #define M_DISCONNECT MSG_DISCONNECT 569 #define M_ID_ERROR MSG_INITIATOR_DET_ERR 570 #define M_ABORT MSG_ABORT 571 #define M_REJECT MSG_MESSAGE_REJECT 572 #define M_NOOP MSG_NOOP 573 #define M_PARITY MSG_PARITY_ERROR 574 #define M_LCOMPLETE MSG_LINK_CMD_COMPLETE 575 #define M_FCOMPLETE MSG_LINK_CMD_COMPLETEF 576 #define M_RESET MSG_BUS_DEV_RESET 577 #define M_ABORT_TAG MSG_ABORT_TAG 578 #define M_CLEAR_QUEUE MSG_CLEAR_QUEUE 579 #define M_INIT_REC MSG_INIT_RECOVERY 580 #define M_REL_REC MSG_REL_RECOVERY 581 #define M_TERMINATE MSG_TERM_IO_PROC 582 #define M_SIMPLE_TAG MSG_SIMPLE_Q_TAG 583 #define M_HEAD_TAG MSG_HEAD_OF_Q_TAG 584 #define M_ORDERED_TAG MSG_ORDERED_Q_TAG 585 #define M_IGN_RESIDUE MSG_IGN_WIDE_RESIDUE 586 #define M_IDENTIFY MSG_IDENTIFY(0, 0) 587 588 /* #define M_X_MODIFY_DP (0x00) */ /* XXX what is this? */ 589 #define M_X_SYNC_REQ MSG_EXT_SDTR 590 #define M_X_WIDE_REQ MSG_EXT_WDTR 591 #else 592 #define M_COMPLETE (0x00) 593 #define M_EXTENDED (0x01) 594 #define M_SAVE_DP (0x02) 595 #define M_RESTORE_DP (0x03) 596 #define M_DISCONNECT (0x04) 597 #define M_ID_ERROR (0x05) 598 #define M_ABORT (0x06) 599 #define M_REJECT (0x07) 600 #define M_NOOP (0x08) 601 #define M_PARITY (0x09) 602 #define M_LCOMPLETE (0x0a) 603 #define M_FCOMPLETE (0x0b) 604 #define M_RESET (0x0c) 605 #define M_ABORT_TAG (0x0d) 606 #define M_CLEAR_QUEUE (0x0e) 607 #define M_INIT_REC (0x0f) 608 #define M_REL_REC (0x10) 609 #define M_TERMINATE (0x11) 610 #define M_SIMPLE_TAG (0x20) 611 #define M_HEAD_TAG (0x21) 612 #define M_ORDERED_TAG (0x22) 613 #define M_IGN_RESIDUE (0x23) 614 #define M_IDENTIFY (0x80) 615 616 #define M_X_MODIFY_DP (0x00) 617 #define M_X_SYNC_REQ (0x01) 618 #define M_X_WIDE_REQ (0x03) 619 #endif 620 621 622 /* 623 ** Status 624 */ 625 626 #define S_GOOD (0x00) 627 #define S_CHECK_COND (0x02) 628 #define S_COND_MET (0x04) 629 #define S_BUSY (0x08) 630 #define S_INT (0x10) 631 #define S_INT_COND_MET (0x14) 632 #define S_CONFLICT (0x18) 633 #define S_TERMINATED (0x20) 634 #define S_QUEUE_FULL (0x28) 635 #define S_ILLEGAL (0xff) 636 #define S_SENSE (0x80) 637 638 /* 639 ** Bits defining chip features. 640 ** For now only some of them are used, since we explicitly 641 ** deal with PCI device id and revision id. 642 */ 643 #define FE_LED0 (1<<0) 644 #define FE_WIDE (1<<1) 645 #define FE_ULTRA (1<<2) 646 #define FE_ULTRA2 (1<<3) 647 #define FE_DBLR (1<<4) 648 #define FE_QUAD (1<<5) 649 #define FE_ERL (1<<6) 650 #define FE_CLSE (1<<7) 651 #define FE_WRIE (1<<8) 652 #define FE_ERMP (1<<9) 653 #define FE_BOF (1<<10) 654 #define FE_DFS (1<<11) 655 #define FE_PFEN (1<<12) 656 #define FE_LDSTR (1<<13) 657 #define FE_RAM (1<<14) 658 #define FE_CLK80 (1<<15) 659 #define FE_DIFF (1<<16) 660 #define FE_BIOS (1<<17) 661 #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP) 662 #define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_ULTRA2|FE_DBLR|FE_QUAD|F_CLK80) 663 #define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM) 664 665 #endif /*__NCR_REG_H__*/ 666