1 /*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 *
29 */
30
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
33
34 #include <sys/kernel.h>
35 #include <sys/bus.h>
36 #include <sys/rman.h>
37 #include <sys/types.h>
38 #include <sys/lock.h>
39 #include <sys/malloc.h>
40 #include <sys/rwlock.h>
41 #include <sys/sx.h>
42 #include <vm/uma.h>
43
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <machine/bus.h>
47 #include <sys/socket.h>
48 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
50 #include <net/if.h>
51 #include <net/if_var.h>
52 #include <net/if_media.h>
53 #include <netinet/in.h>
54 #include <netinet/tcp_lro.h>
55
56 #include "offload.h"
57 #include "common/t4_msg.h"
58 #include "firmware/t4fw_interface.h"
59
60 #define KTR_CXGBE KTR_SPARE3
61 MALLOC_DECLARE(M_CXGBE);
62 #define CXGBE_UNIMPLEMENTED(s) \
63 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
64
65 #if defined(__i386__) || defined(__amd64__)
66 static __inline void
prefetch(void * x)67 prefetch(void *x)
68 {
69 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
70 }
71 #else
72 #define prefetch(x)
73 #endif
74
75 #ifndef SYSCTL_ADD_UQUAD
76 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
77 #define sysctl_handle_64 sysctl_handle_quad
78 #define CTLTYPE_U64 CTLTYPE_QUAD
79 #endif
80
81 #if (__FreeBSD_version >= 900030) || \
82 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
83 #define SBUF_DRAIN 1
84 #endif
85
86 #ifdef __amd64__
87 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
88 static __inline uint64_t
t4_bus_space_read_8(bus_space_tag_t tag,bus_space_handle_t handle,bus_size_t offset)89 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
90 bus_size_t offset)
91 {
92 KASSERT(tag == X86_BUS_SPACE_MEM,
93 ("%s: can only handle mem space", __func__));
94
95 return (*(volatile uint64_t *)(handle + offset));
96 }
97
98 static __inline void
t4_bus_space_write_8(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,uint64_t value)99 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
100 bus_size_t offset, uint64_t value)
101 {
102 KASSERT(tag == X86_BUS_SPACE_MEM,
103 ("%s: can only handle mem space", __func__));
104
105 *(volatile uint64_t *)(bsh + offset) = value;
106 }
107 #else
108 static __inline uint64_t
t4_bus_space_read_8(bus_space_tag_t tag,bus_space_handle_t handle,bus_size_t offset)109 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
110 bus_size_t offset)
111 {
112 return (uint64_t)bus_space_read_4(tag, handle, offset) +
113 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
114 }
115
116 static __inline void
t4_bus_space_write_8(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,uint64_t value)117 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
118 bus_size_t offset, uint64_t value)
119 {
120 bus_space_write_4(tag, bsh, offset, value);
121 bus_space_write_4(tag, bsh, offset + 4, value >> 32);
122 }
123 #endif
124
125 struct adapter;
126 typedef struct adapter adapter_t;
127
128 enum {
129 /*
130 * All ingress queues use this entry size. Note that the firmware event
131 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
132 * be at least 64.
133 */
134 IQ_ESIZE = 64,
135
136 /* Default queue sizes for all kinds of ingress queues */
137 FW_IQ_QSIZE = 256,
138 RX_IQ_QSIZE = 1024,
139
140 /* All egress queues use this entry size */
141 EQ_ESIZE = 64,
142
143 /* Default queue sizes for all kinds of egress queues */
144 CTRL_EQ_QSIZE = 128,
145 TX_EQ_QSIZE = 1024,
146
147 #if MJUMPAGESIZE != MCLBYTES
148 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
149 #else
150 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
151 #endif
152 CL_METADATA_SIZE = CACHE_LINE_SIZE,
153
154 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
155 TX_SGL_SEGS = 39,
156 TX_SGL_SEGS_TSO = 38,
157 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
158 };
159
160 enum {
161 /* adapter intr_type */
162 INTR_INTX = (1 << 0),
163 INTR_MSI = (1 << 1),
164 INTR_MSIX = (1 << 2)
165 };
166
167 enum {
168 XGMAC_MTU = (1 << 0),
169 XGMAC_PROMISC = (1 << 1),
170 XGMAC_ALLMULTI = (1 << 2),
171 XGMAC_VLANEX = (1 << 3),
172 XGMAC_UCADDR = (1 << 4),
173 XGMAC_MCADDRS = (1 << 5),
174
175 XGMAC_ALL = 0xffff
176 };
177
178 enum {
179 /* flags understood by begin_synchronized_op */
180 HOLD_LOCK = (1 << 0),
181 SLEEP_OK = (1 << 1),
182 INTR_OK = (1 << 2),
183
184 /* flags understood by end_synchronized_op */
185 LOCK_HELD = HOLD_LOCK,
186 };
187
188 enum {
189 /* adapter flags */
190 FULL_INIT_DONE = (1 << 0),
191 FW_OK = (1 << 1),
192 /* INTR_DIRECT = (1 << 2), No longer used. */
193 MASTER_PF = (1 << 3),
194 ADAP_SYSCTL_CTX = (1 << 4),
195 /* TOM_INIT_DONE= (1 << 5), No longer used */
196 BUF_PACKING_OK = (1 << 6),
197
198 CXGBE_BUSY = (1 << 9),
199
200 /* port flags */
201 HAS_TRACEQ = (1 << 3),
202
203 /* VI flags */
204 DOOMED = (1 << 0),
205 VI_INIT_DONE = (1 << 1),
206 VI_SYSCTL_CTX = (1 << 2),
207 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */
208 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */
209 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ),
210 VI_NETMAP = (1 << 6),
211
212 /* adapter debug_flags */
213 DF_DUMP_MBOX = (1 << 0),
214 };
215
216 #define IS_DOOMED(vi) ((vi)->flags & DOOMED)
217 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0)
218 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
219 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
220 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
221
222 struct vi_info {
223 device_t dev;
224 struct port_info *pi;
225
226 struct ifnet *ifp;
227 struct ifmedia media;
228
229 unsigned long flags;
230 int if_flags;
231
232 uint16_t *rss;
233 uint16_t viid;
234 int16_t xact_addr_filt;/* index of exact MAC address filter */
235 uint16_t rss_size; /* size of VI's RSS table slice */
236 uint16_t rss_base; /* start of VI's RSS table slice */
237
238 eventhandler_tag vlan_c;
239
240 int nintr;
241 int first_intr;
242
243 /* These need to be int as they are used in sysctl */
244 int ntxq; /* # of tx queues */
245 int first_txq; /* index of first tx queue */
246 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
247 int nrxq; /* # of rx queues */
248 int first_rxq; /* index of first rx queue */
249 #ifdef TCP_OFFLOAD
250 int nofldtxq; /* # of offload tx queues */
251 int first_ofld_txq; /* index of first offload tx queue */
252 int nofldrxq; /* # of offload rx queues */
253 int first_ofld_rxq; /* index of first offload rx queue */
254 #endif
255 int tmr_idx;
256 int pktc_idx;
257 int qsize_rxq;
258 int qsize_txq;
259
260 struct timeval last_refreshed;
261 struct fw_vi_stats_vf stats;
262
263 struct callout tick;
264 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
265
266 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
267 };
268
269 struct port_info {
270 device_t dev;
271 struct adapter *adapter;
272
273 struct vi_info *vi;
274 int nvi;
275 int up_vis;
276 int uld_vis;
277
278 struct mtx pi_lock;
279 char lockname[16];
280 unsigned long flags;
281
282 uint8_t lport; /* associated offload logical port */
283 int8_t mdio_addr;
284 uint8_t port_type;
285 uint8_t mod_type;
286 uint8_t port_id;
287 uint8_t tx_chan;
288 uint8_t rx_chan_map; /* rx MPS channel bitmap */
289
290 int linkdnrc;
291 struct link_config link_cfg;
292
293 struct timeval last_refreshed;
294 struct port_stats stats;
295 u_int tnl_cong_drops;
296 u_int tx_parse_error;
297
298 struct callout tick;
299 };
300
301 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
302
303 /* Where the cluster came from, how it has been carved up. */
304 struct cluster_layout {
305 int8_t zidx;
306 int8_t hwidx;
307 uint16_t region1; /* mbufs laid out within this region */
308 /* region2 is the DMA region */
309 uint16_t region3; /* cluster_metadata within this region */
310 };
311
312 struct cluster_metadata {
313 u_int refcount;
314 #ifdef INVARIANTS
315 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
316 #endif
317 };
318
319 struct fl_sdesc {
320 caddr_t cl;
321 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
322 struct cluster_layout cll;
323 };
324
325 struct tx_desc {
326 __be64 flit[8];
327 };
328
329 struct tx_sdesc {
330 struct mbuf *m; /* m_nextpkt linked chain of frames */
331 uint8_t desc_used; /* # of hardware descriptors used by the WR */
332 };
333
334
335 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
336 struct iq_desc {
337 struct rss_header rss;
338 uint8_t cpl[IQ_PAD];
339 struct rsp_ctrl rsp;
340 };
341 #undef IQ_PAD
342 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
343
344 enum {
345 /* iq flags */
346 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
347 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
348 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
349 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
350
351 /* iq state */
352 IQS_DISABLED = 0,
353 IQS_BUSY = 1,
354 IQS_IDLE = 2,
355 };
356
357 /*
358 * Ingress Queue: T4 is producer, driver is consumer.
359 */
360 struct sge_iq {
361 uint32_t flags;
362 volatile int state;
363 struct adapter *adapter;
364 struct iq_desc *desc; /* KVA of descriptor ring */
365 int8_t intr_pktc_idx; /* packet count threshold index */
366 uint8_t gen; /* generation bit */
367 uint8_t intr_params; /* interrupt holdoff parameters */
368 uint8_t intr_next; /* XXX: holdoff for next interrupt */
369 uint16_t qsize; /* size (# of entries) of the queue */
370 uint16_t sidx; /* index of the entry with the status page */
371 uint16_t cidx; /* consumer index */
372 uint16_t cntxt_id; /* SGE context id for the iq */
373 uint16_t abs_id; /* absolute SGE id for the iq */
374
375 STAILQ_ENTRY(sge_iq) link;
376
377 bus_dma_tag_t desc_tag;
378 bus_dmamap_t desc_map;
379 bus_addr_t ba; /* bus address of descriptor ring */
380 };
381
382 enum {
383 EQ_CTRL = 1,
384 EQ_ETH = 2,
385 EQ_OFLD = 3,
386
387 /* eq flags */
388 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
389 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
390 EQ_ENABLED = (1 << 3), /* open for business */
391 };
392
393 /* Listed in order of preference. Update t4_sysctls too if you change these */
394 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
395
396 /*
397 * Egress Queue: driver is producer, T4 is consumer.
398 *
399 * Note: A free list is an egress queue (driver produces the buffers and T4
400 * consumes them) but it's special enough to have its own struct (see sge_fl).
401 */
402 struct sge_eq {
403 unsigned int flags; /* MUST be first */
404 unsigned int cntxt_id; /* SGE context id for the eq */
405 struct mtx eq_lock;
406
407 struct tx_desc *desc; /* KVA of descriptor ring */
408 uint16_t doorbells;
409 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
410 u_int udb_qid; /* relative qid within the doorbell page */
411 uint16_t sidx; /* index of the entry with the status page */
412 uint16_t cidx; /* consumer idx (desc idx) */
413 uint16_t pidx; /* producer idx (desc idx) */
414 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
415 uint16_t dbidx; /* pidx of the most recent doorbell */
416 uint16_t iqid; /* iq that gets egr_update for the eq */
417 uint8_t tx_chan; /* tx channel used by the eq */
418 volatile u_int equiq; /* EQUIQ outstanding */
419
420 bus_dma_tag_t desc_tag;
421 bus_dmamap_t desc_map;
422 bus_addr_t ba; /* bus address of descriptor ring */
423 char lockname[16];
424 };
425
426 struct sw_zone_info {
427 uma_zone_t zone; /* zone that this cluster comes from */
428 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
429 int type; /* EXT_xxx type of the cluster */
430 int8_t head_hwidx;
431 int8_t tail_hwidx;
432 };
433
434 struct hw_buf_info {
435 int8_t zidx; /* backpointer to zone; -ve means unused */
436 int8_t next; /* next hwidx for this zone; -1 means no more */
437 int size;
438 };
439
440 enum {
441 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
442 FL_DOOMED = (1 << 1), /* about to be destroyed */
443 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
444 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
445 };
446
447 #define FL_RUNNING_LOW(fl) \
448 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
449 #define FL_NOT_RUNNING_LOW(fl) \
450 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
451
452 struct sge_fl {
453 struct mtx fl_lock;
454 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
455 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
456 struct cluster_layout cll_def; /* default refill zone, layout */
457 uint16_t lowat; /* # of buffers <= this means fl needs help */
458 int flags;
459 uint16_t buf_boundary;
460
461 /* The 16b idx all deal with hw descriptors */
462 uint16_t dbidx; /* hw pidx after last doorbell */
463 uint16_t sidx; /* index of status page */
464 volatile uint16_t hw_cidx;
465
466 /* The 32b idx are all buffer idx, not hardware descriptor idx */
467 uint32_t cidx; /* consumer index */
468 uint32_t pidx; /* producer index */
469
470 uint32_t dbval;
471 u_int rx_offset; /* offset in fl buf (when buffer packing) */
472 volatile uint32_t *udb;
473
474 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
475 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
476 uint64_t cl_allocated; /* # of clusters allocated */
477 uint64_t cl_recycled; /* # of clusters recycled */
478 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
479
480 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
481 struct mbuf *m0;
482 struct mbuf **pnext;
483 u_int remaining;
484
485 uint16_t qsize; /* # of hw descriptors (status page included) */
486 uint16_t cntxt_id; /* SGE context id for the freelist */
487 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
488 bus_dma_tag_t desc_tag;
489 bus_dmamap_t desc_map;
490 char lockname[16];
491 bus_addr_t ba; /* bus address of descriptor ring */
492 struct cluster_layout cll_alt; /* alternate refill zone, layout */
493 };
494
495 struct mp_ring;
496
497 /* txq: SGE egress queue + what's needed for Ethernet NIC */
498 struct sge_txq {
499 struct sge_eq eq; /* MUST be first */
500
501 struct ifnet *ifp; /* the interface this txq belongs to */
502 struct mp_ring *r; /* tx software ring */
503 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
504 struct sglist *gl;
505 __be32 cpl_ctrl0; /* for convenience */
506
507 struct task tx_reclaim_task;
508 /* stats for common events first */
509
510 uint64_t txcsum; /* # of times hardware assisted with checksum */
511 uint64_t tso_wrs; /* # of TSO work requests */
512 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
513 uint64_t imm_wrs; /* # of work requests with immediate data */
514 uint64_t sgl_wrs; /* # of work requests with direct SGL */
515 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
516 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
517 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
518 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
519 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
520
521 /* stats for not-that-common events */
522 } __aligned(CACHE_LINE_SIZE);
523
524 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
525 struct sge_rxq {
526 struct sge_iq iq; /* MUST be first */
527 struct sge_fl fl; /* MUST follow iq */
528
529 struct ifnet *ifp; /* the interface this rxq belongs to */
530 #if defined(INET) || defined(INET6)
531 struct lro_ctrl lro; /* LRO state */
532 #endif
533
534 /* stats for common events first */
535
536 uint64_t rxcsum; /* # of times hardware assisted with checksum */
537 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
538
539 /* stats for not-that-common events */
540
541 } __aligned(CACHE_LINE_SIZE);
542
543 static inline struct sge_rxq *
iq_to_rxq(struct sge_iq * iq)544 iq_to_rxq(struct sge_iq *iq)
545 {
546
547 return (__containerof(iq, struct sge_rxq, iq));
548 }
549
550
551 #ifdef TCP_OFFLOAD
552 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
553 struct sge_ofld_rxq {
554 struct sge_iq iq; /* MUST be first */
555 struct sge_fl fl; /* MUST follow iq */
556 } __aligned(CACHE_LINE_SIZE);
557
558 static inline struct sge_ofld_rxq *
iq_to_ofld_rxq(struct sge_iq * iq)559 iq_to_ofld_rxq(struct sge_iq *iq)
560 {
561
562 return (__containerof(iq, struct sge_ofld_rxq, iq));
563 }
564 #endif
565
566 struct wrqe {
567 STAILQ_ENTRY(wrqe) link;
568 struct sge_wrq *wrq;
569 int wr_len;
570 char wr[] __aligned(16);
571 };
572
573 struct wrq_cookie {
574 TAILQ_ENTRY(wrq_cookie) link;
575 int ndesc;
576 int pidx;
577 };
578
579 /*
580 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
581 * and offload tx queues are of this type.
582 */
583 struct sge_wrq {
584 struct sge_eq eq; /* MUST be first */
585
586 struct adapter *adapter;
587 struct task wrq_tx_task;
588
589 /* Tx desc reserved but WR not "committed" yet. */
590 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
591
592 /* List of WRs ready to go out as soon as descriptors are available. */
593 STAILQ_HEAD(, wrqe) wr_list;
594 u_int nwr_pending;
595 u_int ndesc_needed;
596
597 /* stats for common events first */
598
599 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
600 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
601 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
602
603 /* stats for not-that-common events */
604
605 /*
606 * Scratch space for work requests that wrap around after reaching the
607 * status page, and some infomation about the last WR that used it.
608 */
609 uint16_t ss_pidx;
610 uint16_t ss_len;
611 uint8_t ss[SGE_MAX_WR_LEN];
612
613 } __aligned(CACHE_LINE_SIZE);
614
615
616 #ifdef DEV_NETMAP
617 struct sge_nm_rxq {
618 struct vi_info *vi;
619
620 struct iq_desc *iq_desc;
621 uint16_t iq_abs_id;
622 uint16_t iq_cntxt_id;
623 uint16_t iq_cidx;
624 uint16_t iq_sidx;
625 uint8_t iq_gen;
626
627 __be64 *fl_desc;
628 uint16_t fl_cntxt_id;
629 uint32_t fl_cidx;
630 uint32_t fl_pidx;
631 uint32_t fl_sidx;
632 uint32_t fl_db_val;
633 u_int fl_hwidx:4;
634
635 u_int nid; /* netmap ring # for this queue */
636
637 /* infrequently used items after this */
638
639 bus_dma_tag_t iq_desc_tag;
640 bus_dmamap_t iq_desc_map;
641 bus_addr_t iq_ba;
642 int intr_idx;
643
644 bus_dma_tag_t fl_desc_tag;
645 bus_dmamap_t fl_desc_map;
646 bus_addr_t fl_ba;
647 } __aligned(CACHE_LINE_SIZE);
648
649 struct sge_nm_txq {
650 struct tx_desc *desc;
651 uint16_t cidx;
652 uint16_t pidx;
653 uint16_t sidx;
654 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
655 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
656 uint16_t dbidx; /* pidx of the most recent doorbell */
657 uint16_t doorbells;
658 volatile uint32_t *udb;
659 u_int udb_qid;
660 u_int cntxt_id;
661 __be32 cpl_ctrl0; /* for convenience */
662 u_int nid; /* netmap ring # for this queue */
663
664 /* infrequently used items after this */
665
666 bus_dma_tag_t desc_tag;
667 bus_dmamap_t desc_map;
668 bus_addr_t ba;
669 int iqidx;
670 } __aligned(CACHE_LINE_SIZE);
671 #endif
672
673 struct sge {
674 int timer_val[SGE_NTIMERS];
675 int counter_val[SGE_NCOUNTERS];
676 int fl_starve_threshold;
677 int fl_starve_threshold2;
678 int eq_s_qpp;
679 int iq_s_qpp;
680
681 int nrxq; /* total # of Ethernet rx queues */
682 int ntxq; /* total # of Ethernet tx tx queues */
683 #ifdef TCP_OFFLOAD
684 int nofldrxq; /* total # of TOE rx queues */
685 int nofldtxq; /* total # of TOE tx queues */
686 #endif
687 #ifdef DEV_NETMAP
688 int nnmrxq; /* total # of netmap rx queues */
689 int nnmtxq; /* total # of netmap tx queues */
690 #endif
691 int niq; /* total # of ingress queues */
692 int neq; /* total # of egress queues */
693
694 struct sge_iq fwq; /* Firmware event queue */
695 struct sge_wrq mgmtq; /* Management queue (control queue) */
696 struct sge_wrq *ctrlq; /* Control queues */
697 struct sge_txq *txq; /* NIC tx queues */
698 struct sge_rxq *rxq; /* NIC rx queues */
699 #ifdef TCP_OFFLOAD
700 struct sge_wrq *ofld_txq; /* TOE tx queues */
701 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
702 #endif
703 #ifdef DEV_NETMAP
704 struct sge_nm_txq *nm_txq; /* netmap tx queues */
705 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
706 #endif
707
708 uint16_t iq_start;
709 int eq_start;
710 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
711 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
712
713 int pad_boundary;
714 int pack_boundary;
715 int8_t safe_hwidx1; /* may not have room for metadata */
716 int8_t safe_hwidx2; /* with room for metadata and maybe more */
717 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
718 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
719 };
720
721 struct rss_header;
722 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
723 struct mbuf *);
724 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
725 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
726
727 struct adapter {
728 SLIST_ENTRY(adapter) link;
729 device_t dev;
730 struct cdev *cdev;
731
732 /* PCIe register resources */
733 int regs_rid;
734 struct resource *regs_res;
735 int msix_rid;
736 struct resource *msix_res;
737 bus_space_handle_t bh;
738 bus_space_tag_t bt;
739 bus_size_t mmio_len;
740 int udbs_rid;
741 struct resource *udbs_res;
742 volatile uint8_t *udbs_base;
743
744 unsigned int pf;
745 unsigned int mbox;
746
747 /* Interrupt information */
748 int intr_type;
749 int intr_count;
750 struct irq {
751 struct resource *res;
752 int rid;
753 void *tag;
754 } *irq;
755
756 bus_dma_tag_t dmat; /* Parent DMA tag */
757
758 struct sge sge;
759 int lro_timeout;
760
761 struct taskqueue *tq[NCHAN]; /* General purpose taskqueues */
762 struct port_info *port[MAX_NPORTS];
763 uint8_t chan_map[NCHAN];
764
765 #ifdef TCP_OFFLOAD
766 void *tom_softc; /* (struct tom_data *) */
767 struct tom_tunables tt;
768 void *iwarp_softc; /* (struct c4iw_dev *) */
769 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
770 #endif
771 struct l2t_data *l2t; /* L2 table */
772 struct tid_info tids;
773
774 uint16_t doorbells;
775 #ifdef TCP_OFFLOAD
776 int offload_map; /* ports with IFCAP_TOE enabled */
777 int active_ulds; /* ULDs activated on this adapter */
778 #endif
779 int flags;
780 int debug_flags;
781
782 char ifp_lockname[16];
783 struct mtx ifp_lock;
784 struct ifnet *ifp; /* tracer ifp */
785 struct ifmedia media;
786 int traceq; /* iq used by all tracers, -1 if none */
787 int tracer_valid; /* bitmap of valid tracers */
788 int tracer_enabled; /* bitmap of enabled tracers */
789
790 char fw_version[32];
791 char cfg_file[32];
792 u_int cfcsum;
793 struct adapter_params params;
794 struct t4_virt_res vres;
795
796 uint16_t linkcaps;
797 uint16_t niccaps;
798 uint16_t toecaps;
799 uint16_t rdmacaps;
800 uint16_t iscsicaps;
801 uint16_t fcoecaps;
802
803 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
804
805 struct mtx sc_lock;
806 char lockname[16];
807
808 /* Starving free lists */
809 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
810 TAILQ_HEAD(, sge_fl) sfl;
811 struct callout sfl_callout;
812
813 struct mtx regwin_lock; /* for indirect reads and memory windows */
814
815 an_handler_t an_handler __aligned(CACHE_LINE_SIZE);
816 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */
817 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
818
819 #ifdef INVARIANTS
820 const char *last_op;
821 const void *last_op_thr;
822 int last_op_flags;
823 #endif
824
825 int sc_do_rxcopy;
826 };
827
828 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
829 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
830 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
831 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
832
833 #define ASSERT_SYNCHRONIZED_OP(sc) \
834 KASSERT(IS_BUSY(sc) && \
835 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
836 ("%s: operation not synchronized.", __func__))
837
838 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
839 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
840 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
841 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
842
843 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
844 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
845 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
846 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
847 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
848
849 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
850 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
851 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
852 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
853
854 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
855 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
856 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
857 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
858 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
859
860 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
861 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
862 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
863 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
864 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
865
866 #define CH_DUMP_MBOX(sc, mbox, data_reg) \
867 do { \
868 if (sc->debug_flags & DF_DUMP_MBOX) { \
869 log(LOG_NOTICE, \
870 "%s mbox %u: %016llx %016llx %016llx %016llx " \
871 "%016llx %016llx %016llx %016llx\n", \
872 device_get_nameunit(sc->dev), mbox, \
873 (unsigned long long)t4_read_reg64(sc, data_reg), \
874 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \
875 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \
876 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \
877 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \
878 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \
879 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \
880 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \
881 } \
882 } while (0)
883
884 #define for_each_txq(vi, iter, q) \
885 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \
886 iter < vi->ntxq; ++iter, ++q)
887 #define for_each_rxq(vi, iter, q) \
888 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
889 iter < vi->nrxq; ++iter, ++q)
890 #define for_each_ofld_txq(vi, iter, q) \
891 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
892 iter < vi->nofldtxq; ++iter, ++q)
893 #define for_each_ofld_rxq(vi, iter, q) \
894 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
895 iter < vi->nofldrxq; ++iter, ++q)
896 #define for_each_nm_txq(vi, iter, q) \
897 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_txq], iter = 0; \
898 iter < vi->ntxq; ++iter, ++q)
899 #define for_each_nm_rxq(vi, iter, q) \
900 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_rxq], iter = 0; \
901 iter < vi->nrxq; ++iter, ++q)
902 #define for_each_vi(_pi, _iter, _vi) \
903 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
904 ++(_iter), ++(_vi))
905
906 #define IDXINCR(idx, incr, wrap) do { \
907 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
908 } while (0)
909 #define IDXDIFF(head, tail, wrap) \
910 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
911
912 /* One for errors, one for firmware events */
913 #define T4_EXTRA_INTR 2
914
915 static inline uint32_t
t4_read_reg(struct adapter * sc,uint32_t reg)916 t4_read_reg(struct adapter *sc, uint32_t reg)
917 {
918
919 return bus_space_read_4(sc->bt, sc->bh, reg);
920 }
921
922 static inline void
t4_write_reg(struct adapter * sc,uint32_t reg,uint32_t val)923 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
924 {
925
926 bus_space_write_4(sc->bt, sc->bh, reg, val);
927 }
928
929 static inline uint64_t
t4_read_reg64(struct adapter * sc,uint32_t reg)930 t4_read_reg64(struct adapter *sc, uint32_t reg)
931 {
932
933 return t4_bus_space_read_8(sc->bt, sc->bh, reg);
934 }
935
936 static inline void
t4_write_reg64(struct adapter * sc,uint32_t reg,uint64_t val)937 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
938 {
939
940 t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
941 }
942
943 static inline void
t4_os_pci_read_cfg1(struct adapter * sc,int reg,uint8_t * val)944 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
945 {
946
947 *val = pci_read_config(sc->dev, reg, 1);
948 }
949
950 static inline void
t4_os_pci_write_cfg1(struct adapter * sc,int reg,uint8_t val)951 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
952 {
953
954 pci_write_config(sc->dev, reg, val, 1);
955 }
956
957 static inline void
t4_os_pci_read_cfg2(struct adapter * sc,int reg,uint16_t * val)958 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
959 {
960
961 *val = pci_read_config(sc->dev, reg, 2);
962 }
963
964 static inline void
t4_os_pci_write_cfg2(struct adapter * sc,int reg,uint16_t val)965 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
966 {
967
968 pci_write_config(sc->dev, reg, val, 2);
969 }
970
971 static inline void
t4_os_pci_read_cfg4(struct adapter * sc,int reg,uint32_t * val)972 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
973 {
974
975 *val = pci_read_config(sc->dev, reg, 4);
976 }
977
978 static inline void
t4_os_pci_write_cfg4(struct adapter * sc,int reg,uint32_t val)979 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
980 {
981
982 pci_write_config(sc->dev, reg, val, 4);
983 }
984
985 static inline struct port_info *
adap2pinfo(struct adapter * sc,int idx)986 adap2pinfo(struct adapter *sc, int idx)
987 {
988
989 return (sc->port[idx]);
990 }
991
992 static inline void
t4_os_set_hw_addr(struct adapter * sc,int idx,uint8_t hw_addr[])993 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
994 {
995
996 bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN);
997 }
998
999 static inline bool
is_10G_port(const struct port_info * pi)1000 is_10G_port(const struct port_info *pi)
1001 {
1002
1003 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
1004 }
1005
1006 static inline bool
is_40G_port(const struct port_info * pi)1007 is_40G_port(const struct port_info *pi)
1008 {
1009
1010 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
1011 }
1012
1013 static inline int
tx_resume_threshold(struct sge_eq * eq)1014 tx_resume_threshold(struct sge_eq *eq)
1015 {
1016
1017 /* not quite the same as qsize / 4, but this will do. */
1018 return (eq->sidx / 4);
1019 }
1020
1021 /* t4_main.c */
1022 int t4_os_find_pci_capability(struct adapter *, int);
1023 int t4_os_pci_save_state(struct adapter *);
1024 int t4_os_pci_restore_state(struct adapter *);
1025 void t4_os_portmod_changed(const struct adapter *, int);
1026 void t4_os_link_changed(struct adapter *, int, int, int);
1027 void t4_iterate(void (*)(struct adapter *, void *), void *);
1028 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
1029 int t4_register_an_handler(struct adapter *, an_handler_t);
1030 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
1031 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1032 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1033 void doom_vi(struct adapter *, struct vi_info *);
1034 void end_synchronized_op(struct adapter *, int);
1035 int update_mac_settings(struct ifnet *, int);
1036 int adapter_full_init(struct adapter *);
1037 int adapter_full_uninit(struct adapter *);
1038 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1039 int vi_full_init(struct vi_info *);
1040 int vi_full_uninit(struct vi_info *);
1041 void vi_sysctls(struct vi_info *);
1042 void vi_tick(void *);
1043
1044 #ifdef DEV_NETMAP
1045 /* t4_netmap.c */
1046 int create_netmap_ifnet(struct port_info *);
1047 int destroy_netmap_ifnet(struct port_info *);
1048 void t4_nm_intr(void *);
1049 #endif
1050
1051 /* t4_sge.c */
1052 void t4_sge_modload(void);
1053 void t4_sge_modunload(void);
1054 uint64_t t4_sge_extfree_refs(void);
1055 void t4_init_sge_cpl_handlers(struct adapter *);
1056 void t4_tweak_chip_settings(struct adapter *);
1057 int t4_read_chip_settings(struct adapter *);
1058 int t4_create_dma_tag(struct adapter *);
1059 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1060 struct sysctl_oid_list *);
1061 int t4_destroy_dma_tag(struct adapter *);
1062 int t4_setup_adapter_queues(struct adapter *);
1063 int t4_teardown_adapter_queues(struct adapter *);
1064 int t4_setup_vi_queues(struct vi_info *);
1065 int t4_teardown_vi_queues(struct vi_info *);
1066 void t4_intr_all(void *);
1067 void t4_intr(void *);
1068 void t4_intr_err(void *);
1069 void t4_intr_evt(void *);
1070 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1071 void t4_update_fl_bufsize(struct ifnet *);
1072 int parse_pkt(struct mbuf **);
1073 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1074 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1075 int tnl_cong(struct port_info *, int);
1076
1077 /* t4_tracer.c */
1078 struct t4_tracer;
1079 void t4_tracer_modload(void);
1080 void t4_tracer_modunload(void);
1081 void t4_tracer_port_detach(struct adapter *);
1082 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1083 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1084 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1085 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1086
1087 static inline struct wrqe *
alloc_wrqe(int wr_len,struct sge_wrq * wrq)1088 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1089 {
1090 int len = offsetof(struct wrqe, wr) + wr_len;
1091 struct wrqe *wr;
1092
1093 wr = malloc(len, M_CXGBE, M_NOWAIT);
1094 if (__predict_false(wr == NULL))
1095 return (NULL);
1096 wr->wr_len = wr_len;
1097 wr->wrq = wrq;
1098 return (wr);
1099 }
1100
1101 static inline void *
wrtod(struct wrqe * wr)1102 wrtod(struct wrqe *wr)
1103 {
1104 return (&wr->wr[0]);
1105 }
1106
1107 static inline void
free_wrqe(struct wrqe * wr)1108 free_wrqe(struct wrqe *wr)
1109 {
1110 free(wr, M_CXGBE);
1111 }
1112
1113 static inline void
t4_wrq_tx(struct adapter * sc,struct wrqe * wr)1114 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1115 {
1116 struct sge_wrq *wrq = wr->wrq;
1117
1118 TXQ_LOCK(wrq);
1119 t4_wrq_tx_locked(sc, wrq, wr);
1120 TXQ_UNLOCK(wrq);
1121 }
1122
1123 #endif
1124