1 /*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 *
29 */
30
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
33
34 #include <sys/kernel.h>
35 #include <sys/bus.h>
36 #include <sys/rman.h>
37 #include <sys/types.h>
38 #include <sys/malloc.h>
39 #include <dev/pci/pcivar.h>
40 #include <dev/pci/pcireg.h>
41 #include <machine/bus.h>
42 #include <sys/socket.h>
43 #include <sys/sysctl.h>
44 #include <net/ethernet.h>
45 #include <net/if.h>
46 #include <net/if_media.h>
47 #include <netinet/in.h>
48 #include <netinet/tcp_lro.h>
49
50 #include "offload.h"
51 #include "common/t4_msg.h"
52 #include "firmware/t4fw_interface.h"
53
54 #define KTR_CXGBE KTR_SPARE3
55 MALLOC_DECLARE(M_CXGBE);
56 #define CXGBE_UNIMPLEMENTED(s) \
57 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
58
59 #if defined(__i386__) || defined(__amd64__)
60 static __inline void
prefetch(void * x)61 prefetch(void *x)
62 {
63 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
64 }
65 #else
66 #define prefetch(x)
67 #endif
68
69 #ifndef SYSCTL_ADD_UQUAD
70 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
71 #define sysctl_handle_64 sysctl_handle_quad
72 #define CTLTYPE_U64 CTLTYPE_QUAD
73 #endif
74
75 #if (__FreeBSD_version >= 900030) || \
76 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
77 #define SBUF_DRAIN 1
78 #endif
79
80 #ifdef __amd64__
81 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
82 static __inline uint64_t
t4_bus_space_read_8(bus_space_tag_t tag,bus_space_handle_t handle,bus_size_t offset)83 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
84 bus_size_t offset)
85 {
86 KASSERT(tag == X86_BUS_SPACE_MEM,
87 ("%s: can only handle mem space", __func__));
88
89 return (*(volatile uint64_t *)(handle + offset));
90 }
91
92 static __inline void
t4_bus_space_write_8(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,uint64_t value)93 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
94 bus_size_t offset, uint64_t value)
95 {
96 KASSERT(tag == X86_BUS_SPACE_MEM,
97 ("%s: can only handle mem space", __func__));
98
99 *(volatile uint64_t *)(bsh + offset) = value;
100 }
101 #else
102 static __inline uint64_t
t4_bus_space_read_8(bus_space_tag_t tag,bus_space_handle_t handle,bus_size_t offset)103 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
104 bus_size_t offset)
105 {
106 return (uint64_t)bus_space_read_4(tag, handle, offset) +
107 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
108 }
109
110 static __inline void
t4_bus_space_write_8(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,uint64_t value)111 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
112 bus_size_t offset, uint64_t value)
113 {
114 bus_space_write_4(tag, bsh, offset, value);
115 bus_space_write_4(tag, bsh, offset + 4, value >> 32);
116 }
117 #endif
118
119 struct adapter;
120 typedef struct adapter adapter_t;
121
122 enum {
123 /*
124 * All ingress queues use this entry size. Note that the firmware event
125 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
126 * be at least 64.
127 */
128 IQ_ESIZE = 64,
129
130 /* Default queue sizes for all kinds of ingress queues */
131 FW_IQ_QSIZE = 256,
132 RX_IQ_QSIZE = 1024,
133
134 /* All egress queues use this entry size */
135 EQ_ESIZE = 64,
136
137 /* Default queue sizes for all kinds of egress queues */
138 CTRL_EQ_QSIZE = 128,
139 TX_EQ_QSIZE = 1024,
140
141 #if MJUMPAGESIZE != MCLBYTES
142 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
143 #else
144 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
145 #endif
146 CL_METADATA_SIZE = CACHE_LINE_SIZE,
147
148 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
149 TX_SGL_SEGS = 39,
150 TX_SGL_SEGS_TSO = 38,
151 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
152 };
153
154 enum {
155 /* adapter intr_type */
156 INTR_INTX = (1 << 0),
157 INTR_MSI = (1 << 1),
158 INTR_MSIX = (1 << 2)
159 };
160
161 enum {
162 XGMAC_MTU = (1 << 0),
163 XGMAC_PROMISC = (1 << 1),
164 XGMAC_ALLMULTI = (1 << 2),
165 XGMAC_VLANEX = (1 << 3),
166 XGMAC_UCADDR = (1 << 4),
167 XGMAC_MCADDRS = (1 << 5),
168
169 XGMAC_ALL = 0xffff
170 };
171
172 enum {
173 /* flags understood by begin_synchronized_op */
174 HOLD_LOCK = (1 << 0),
175 SLEEP_OK = (1 << 1),
176 INTR_OK = (1 << 2),
177
178 /* flags understood by end_synchronized_op */
179 LOCK_HELD = HOLD_LOCK,
180 };
181
182 enum {
183 /* adapter flags */
184 FULL_INIT_DONE = (1 << 0),
185 FW_OK = (1 << 1),
186 /* INTR_DIRECT = (1 << 2), No longer used. */
187 MASTER_PF = (1 << 3),
188 ADAP_SYSCTL_CTX = (1 << 4),
189 /* TOM_INIT_DONE= (1 << 5), No longer used */
190 BUF_PACKING_OK = (1 << 6),
191
192 CXGBE_BUSY = (1 << 9),
193
194 /* port flags */
195 DOOMED = (1 << 0),
196 PORT_INIT_DONE = (1 << 1),
197 PORT_SYSCTL_CTX = (1 << 2),
198 HAS_TRACEQ = (1 << 3),
199 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */
200 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */
201 INTR_NM_RXQ = (1 << 6), /* All netmap rxq's take interrupts */
202 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ | INTR_NM_RXQ),
203 };
204
205 #define IS_DOOMED(pi) ((pi)->flags & DOOMED)
206 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0)
207 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
208 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
209 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
210
211 struct port_info {
212 device_t dev;
213 struct adapter *adapter;
214
215 struct ifnet *ifp;
216 struct ifmedia media;
217
218 struct mtx pi_lock;
219 char lockname[16];
220 unsigned long flags;
221 int if_flags;
222
223 uint16_t *rss;
224 uint16_t viid;
225 int16_t xact_addr_filt;/* index of exact MAC address filter */
226 uint16_t rss_size; /* size of VI's RSS table slice */
227 uint8_t lport; /* associated offload logical port */
228 int8_t mdio_addr;
229 uint8_t port_type;
230 uint8_t mod_type;
231 uint8_t port_id;
232 uint8_t tx_chan;
233 uint8_t rx_chan_map; /* rx MPS channel bitmap */
234
235 /* These need to be int as they are used in sysctl */
236 int ntxq; /* # of tx queues */
237 int first_txq; /* index of first tx queue */
238 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
239 int nrxq; /* # of rx queues */
240 int first_rxq; /* index of first rx queue */
241 #ifdef TCP_OFFLOAD
242 int nofldtxq; /* # of offload tx queues */
243 int first_ofld_txq; /* index of first offload tx queue */
244 int nofldrxq; /* # of offload rx queues */
245 int first_ofld_rxq; /* index of first offload rx queue */
246 #endif
247 #ifdef DEV_NETMAP
248 int nnmtxq; /* # of netmap tx queues */
249 int first_nm_txq; /* index of first netmap tx queue */
250 int nnmrxq; /* # of netmap rx queues */
251 int first_nm_rxq; /* index of first netmap rx queue */
252
253 struct ifnet *nm_ifp;
254 struct ifmedia nm_media;
255 int nmif_flags;
256 uint16_t nm_viid;
257 int16_t nm_xact_addr_filt;
258 uint16_t nm_rss_size; /* size of netmap VI's RSS table slice */
259 #endif
260 int tmr_idx;
261 int pktc_idx;
262 int qsize_rxq;
263 int qsize_txq;
264
265 int linkdnrc;
266 struct link_config link_cfg;
267
268 struct timeval last_refreshed;
269 struct port_stats stats;
270 u_int tx_parse_error;
271
272 eventhandler_tag vlan_c;
273
274 struct callout tick;
275 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
276
277 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
278 };
279
280 /* Where the cluster came from, how it has been carved up. */
281 struct cluster_layout {
282 int8_t zidx;
283 int8_t hwidx;
284 uint16_t region1; /* mbufs laid out within this region */
285 /* region2 is the DMA region */
286 uint16_t region3; /* cluster_metadata within this region */
287 };
288
289 struct cluster_metadata {
290 u_int refcount;
291 #ifdef INVARIANTS
292 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
293 #endif
294 };
295
296 struct fl_sdesc {
297 caddr_t cl;
298 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
299 struct cluster_layout cll;
300 };
301
302 struct tx_desc {
303 __be64 flit[8];
304 };
305
306 struct tx_sdesc {
307 struct mbuf *m; /* m_nextpkt linked chain of frames */
308 uint8_t desc_used; /* # of hardware descriptors used by the WR */
309 };
310
311
312 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
313 struct iq_desc {
314 struct rss_header rss;
315 uint8_t cpl[IQ_PAD];
316 struct rsp_ctrl rsp;
317 };
318 #undef IQ_PAD
319 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
320
321 enum {
322 /* iq flags */
323 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
324 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
325 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
326 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
327
328 /* iq state */
329 IQS_DISABLED = 0,
330 IQS_BUSY = 1,
331 IQS_IDLE = 2,
332 };
333
334 /*
335 * Ingress Queue: T4 is producer, driver is consumer.
336 */
337 struct sge_iq {
338 uint32_t flags;
339 volatile int state;
340 struct adapter *adapter;
341 struct iq_desc *desc; /* KVA of descriptor ring */
342 int8_t intr_pktc_idx; /* packet count threshold index */
343 uint8_t gen; /* generation bit */
344 uint8_t intr_params; /* interrupt holdoff parameters */
345 uint8_t intr_next; /* XXX: holdoff for next interrupt */
346 uint16_t qsize; /* size (# of entries) of the queue */
347 uint16_t sidx; /* index of the entry with the status page */
348 uint16_t cidx; /* consumer index */
349 uint16_t cntxt_id; /* SGE context id for the iq */
350 uint16_t abs_id; /* absolute SGE id for the iq */
351
352 STAILQ_ENTRY(sge_iq) link;
353
354 bus_dma_tag_t desc_tag;
355 bus_dmamap_t desc_map;
356 bus_addr_t ba; /* bus address of descriptor ring */
357 };
358
359 enum {
360 EQ_CTRL = 1,
361 EQ_ETH = 2,
362 EQ_OFLD = 3,
363
364 /* eq flags */
365 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
366 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
367 EQ_ENABLED = (1 << 3), /* open for business */
368 };
369
370 /* Listed in order of preference. Update t4_sysctls too if you change these */
371 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
372
373 /*
374 * Egress Queue: driver is producer, T4 is consumer.
375 *
376 * Note: A free list is an egress queue (driver produces the buffers and T4
377 * consumes them) but it's special enough to have its own struct (see sge_fl).
378 */
379 struct sge_eq {
380 unsigned int flags; /* MUST be first */
381 unsigned int cntxt_id; /* SGE context id for the eq */
382 struct mtx eq_lock;
383
384 struct tx_desc *desc; /* KVA of descriptor ring */
385 uint16_t doorbells;
386 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
387 u_int udb_qid; /* relative qid within the doorbell page */
388 uint16_t sidx; /* index of the entry with the status page */
389 uint16_t cidx; /* consumer idx (desc idx) */
390 uint16_t pidx; /* producer idx (desc idx) */
391 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
392 uint16_t dbidx; /* pidx of the most recent doorbell */
393 uint16_t iqid; /* iq that gets egr_update for the eq */
394 uint8_t tx_chan; /* tx channel used by the eq */
395 volatile u_int equiq; /* EQUIQ outstanding */
396
397 bus_dma_tag_t desc_tag;
398 bus_dmamap_t desc_map;
399 bus_addr_t ba; /* bus address of descriptor ring */
400 char lockname[16];
401 };
402
403 struct sw_zone_info {
404 uma_zone_t zone; /* zone that this cluster comes from */
405 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
406 int type; /* EXT_xxx type of the cluster */
407 int8_t head_hwidx;
408 int8_t tail_hwidx;
409 };
410
411 struct hw_buf_info {
412 int8_t zidx; /* backpointer to zone; -ve means unused */
413 int8_t next; /* next hwidx for this zone; -1 means no more */
414 int size;
415 };
416
417 enum {
418 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
419 FL_DOOMED = (1 << 1), /* about to be destroyed */
420 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
421 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
422 };
423
424 #define FL_RUNNING_LOW(fl) \
425 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
426 #define FL_NOT_RUNNING_LOW(fl) \
427 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
428
429 struct sge_fl {
430 struct mtx fl_lock;
431 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
432 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
433 struct cluster_layout cll_def; /* default refill zone, layout */
434 uint16_t lowat; /* # of buffers <= this means fl needs help */
435 int flags;
436 uint16_t buf_boundary;
437
438 /* The 16b idx all deal with hw descriptors */
439 uint16_t dbidx; /* hw pidx after last doorbell */
440 uint16_t sidx; /* index of status page */
441 volatile uint16_t hw_cidx;
442
443 /* The 32b idx are all buffer idx, not hardware descriptor idx */
444 uint32_t cidx; /* consumer index */
445 uint32_t pidx; /* producer index */
446
447 uint32_t dbval;
448 u_int rx_offset; /* offset in fl buf (when buffer packing) */
449 volatile uint32_t *udb;
450
451 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
452 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
453 uint64_t cl_allocated; /* # of clusters allocated */
454 uint64_t cl_recycled; /* # of clusters recycled */
455 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
456
457 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
458 struct mbuf *m0;
459 struct mbuf **pnext;
460 u_int remaining;
461
462 uint16_t qsize; /* # of hw descriptors (status page included) */
463 uint16_t cntxt_id; /* SGE context id for the freelist */
464 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
465 bus_dma_tag_t desc_tag;
466 bus_dmamap_t desc_map;
467 char lockname[16];
468 bus_addr_t ba; /* bus address of descriptor ring */
469 struct cluster_layout cll_alt; /* alternate refill zone, layout */
470 };
471
472 struct mp_ring;
473
474 /* txq: SGE egress queue + what's needed for Ethernet NIC */
475 struct sge_txq {
476 struct sge_eq eq; /* MUST be first */
477
478 struct ifnet *ifp; /* the interface this txq belongs to */
479 struct mp_ring *r; /* tx software ring */
480 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
481 struct sglist *gl;
482 __be32 cpl_ctrl0; /* for convenience */
483
484 struct task tx_reclaim_task;
485 /* stats for common events first */
486
487 uint64_t txcsum; /* # of times hardware assisted with checksum */
488 uint64_t tso_wrs; /* # of TSO work requests */
489 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
490 uint64_t imm_wrs; /* # of work requests with immediate data */
491 uint64_t sgl_wrs; /* # of work requests with direct SGL */
492 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
493 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
494 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
495 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
496 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
497
498 /* stats for not-that-common events */
499 } __aligned(CACHE_LINE_SIZE);
500
501 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
502 struct sge_rxq {
503 struct sge_iq iq; /* MUST be first */
504 struct sge_fl fl; /* MUST follow iq */
505
506 struct ifnet *ifp; /* the interface this rxq belongs to */
507 #if defined(INET) || defined(INET6)
508 struct lro_ctrl lro; /* LRO state */
509 #endif
510
511 /* stats for common events first */
512
513 uint64_t rxcsum; /* # of times hardware assisted with checksum */
514 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
515
516 /* stats for not-that-common events */
517
518 } __aligned(CACHE_LINE_SIZE);
519
520 static inline struct sge_rxq *
iq_to_rxq(struct sge_iq * iq)521 iq_to_rxq(struct sge_iq *iq)
522 {
523
524 return (__containerof(iq, struct sge_rxq, iq));
525 }
526
527
528 #ifdef TCP_OFFLOAD
529 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
530 struct sge_ofld_rxq {
531 struct sge_iq iq; /* MUST be first */
532 struct sge_fl fl; /* MUST follow iq */
533 } __aligned(CACHE_LINE_SIZE);
534
535 static inline struct sge_ofld_rxq *
iq_to_ofld_rxq(struct sge_iq * iq)536 iq_to_ofld_rxq(struct sge_iq *iq)
537 {
538
539 return (__containerof(iq, struct sge_ofld_rxq, iq));
540 }
541 #endif
542
543 struct wrqe {
544 STAILQ_ENTRY(wrqe) link;
545 struct sge_wrq *wrq;
546 int wr_len;
547 char wr[] __aligned(16);
548 };
549
550 struct wrq_cookie {
551 TAILQ_ENTRY(wrq_cookie) link;
552 int ndesc;
553 int pidx;
554 };
555
556 /*
557 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
558 * and offload tx queues are of this type.
559 */
560 struct sge_wrq {
561 struct sge_eq eq; /* MUST be first */
562
563 struct adapter *adapter;
564 struct task wrq_tx_task;
565
566 /* Tx desc reserved but WR not "committed" yet. */
567 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
568
569 /* List of WRs ready to go out as soon as descriptors are available. */
570 STAILQ_HEAD(, wrqe) wr_list;
571 u_int nwr_pending;
572 u_int ndesc_needed;
573
574 /* stats for common events first */
575
576 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
577 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
578 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
579
580 /* stats for not-that-common events */
581
582 /*
583 * Scratch space for work requests that wrap around after reaching the
584 * status page, and some infomation about the last WR that used it.
585 */
586 uint16_t ss_pidx;
587 uint16_t ss_len;
588 uint8_t ss[SGE_MAX_WR_LEN];
589
590 } __aligned(CACHE_LINE_SIZE);
591
592
593 #ifdef DEV_NETMAP
594 struct sge_nm_rxq {
595 struct port_info *pi;
596
597 struct iq_desc *iq_desc;
598 uint16_t iq_abs_id;
599 uint16_t iq_cntxt_id;
600 uint16_t iq_cidx;
601 uint16_t iq_sidx;
602 uint8_t iq_gen;
603
604 __be64 *fl_desc;
605 uint16_t fl_cntxt_id;
606 uint32_t fl_cidx;
607 uint32_t fl_pidx;
608 uint32_t fl_sidx;
609 uint32_t fl_db_val;
610 u_int fl_hwidx:4;
611
612 u_int nid; /* netmap ring # for this queue */
613
614 /* infrequently used items after this */
615
616 bus_dma_tag_t iq_desc_tag;
617 bus_dmamap_t iq_desc_map;
618 bus_addr_t iq_ba;
619 int intr_idx;
620
621 bus_dma_tag_t fl_desc_tag;
622 bus_dmamap_t fl_desc_map;
623 bus_addr_t fl_ba;
624 } __aligned(CACHE_LINE_SIZE);
625
626 struct sge_nm_txq {
627 struct tx_desc *desc;
628 uint16_t cidx;
629 uint16_t pidx;
630 uint16_t sidx;
631 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
632 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
633 uint16_t dbidx; /* pidx of the most recent doorbell */
634 uint16_t doorbells;
635 volatile uint32_t *udb;
636 u_int udb_qid;
637 u_int cntxt_id;
638 __be32 cpl_ctrl0; /* for convenience */
639 u_int nid; /* netmap ring # for this queue */
640
641 /* infrequently used items after this */
642
643 bus_dma_tag_t desc_tag;
644 bus_dmamap_t desc_map;
645 bus_addr_t ba;
646 int iqidx;
647 } __aligned(CACHE_LINE_SIZE);
648 #endif
649
650 struct sge {
651 int timer_val[SGE_NTIMERS];
652 int counter_val[SGE_NCOUNTERS];
653 int fl_starve_threshold;
654 int fl_starve_threshold2;
655 int eq_s_qpp;
656 int iq_s_qpp;
657
658 int nrxq; /* total # of Ethernet rx queues */
659 int ntxq; /* total # of Ethernet tx tx queues */
660 #ifdef TCP_OFFLOAD
661 int nofldrxq; /* total # of TOE rx queues */
662 int nofldtxq; /* total # of TOE tx queues */
663 #endif
664 #ifdef DEV_NETMAP
665 int nnmrxq; /* total # of netmap rx queues */
666 int nnmtxq; /* total # of netmap tx queues */
667 #endif
668 int niq; /* total # of ingress queues */
669 int neq; /* total # of egress queues */
670
671 struct sge_iq fwq; /* Firmware event queue */
672 struct sge_wrq mgmtq; /* Management queue (control queue) */
673 struct sge_wrq *ctrlq; /* Control queues */
674 struct sge_txq *txq; /* NIC tx queues */
675 struct sge_rxq *rxq; /* NIC rx queues */
676 #ifdef TCP_OFFLOAD
677 struct sge_wrq *ofld_txq; /* TOE tx queues */
678 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
679 #endif
680 #ifdef DEV_NETMAP
681 struct sge_nm_txq *nm_txq; /* netmap tx queues */
682 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
683 #endif
684
685 uint16_t iq_start;
686 int eq_start;
687 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
688 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
689
690 int pad_boundary;
691 int pack_boundary;
692 int8_t safe_hwidx1; /* may not have room for metadata */
693 int8_t safe_hwidx2; /* with room for metadata and maybe more */
694 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
695 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
696 };
697
698 struct rss_header;
699 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
700 struct mbuf *);
701 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
702 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
703
704 struct adapter {
705 SLIST_ENTRY(adapter) link;
706 device_t dev;
707 struct cdev *cdev;
708
709 /* PCIe register resources */
710 int regs_rid;
711 struct resource *regs_res;
712 int msix_rid;
713 struct resource *msix_res;
714 bus_space_handle_t bh;
715 bus_space_tag_t bt;
716 bus_size_t mmio_len;
717 int udbs_rid;
718 struct resource *udbs_res;
719 volatile uint8_t *udbs_base;
720
721 unsigned int pf;
722 unsigned int mbox;
723
724 /* Interrupt information */
725 int intr_type;
726 int intr_count;
727 struct irq {
728 struct resource *res;
729 int rid;
730 void *tag;
731 } *irq;
732
733 bus_dma_tag_t dmat; /* Parent DMA tag */
734
735 struct sge sge;
736 int lro_timeout;
737
738 struct taskqueue *tq[NCHAN]; /* General purpose taskqueues */
739 struct port_info *port[MAX_NPORTS];
740 uint8_t chan_map[NCHAN];
741
742 #ifdef TCP_OFFLOAD
743 void *tom_softc; /* (struct tom_data *) */
744 struct tom_tunables tt;
745 void *iwarp_softc; /* (struct c4iw_dev *) */
746 void *iscsi_softc;
747 #endif
748 struct l2t_data *l2t; /* L2 table */
749 struct tid_info tids;
750
751 uint16_t doorbells;
752 int open_device_map;
753 #ifdef TCP_OFFLOAD
754 int offload_map; /* ports with IFCAP_TOE enabled */
755 int active_ulds; /* ULDs activated on this adapter */
756 #endif
757 int flags;
758
759 char ifp_lockname[16];
760 struct mtx ifp_lock;
761 struct ifnet *ifp; /* tracer ifp */
762 struct ifmedia media;
763 int traceq; /* iq used by all tracers, -1 if none */
764 int tracer_valid; /* bitmap of valid tracers */
765 int tracer_enabled; /* bitmap of enabled tracers */
766
767 char fw_version[32];
768 char cfg_file[32];
769 u_int cfcsum;
770 struct adapter_params params;
771 struct t4_virt_res vres;
772
773 uint16_t linkcaps;
774 uint16_t niccaps;
775 uint16_t toecaps;
776 uint16_t rdmacaps;
777 uint16_t iscsicaps;
778 uint16_t fcoecaps;
779
780 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
781
782 struct mtx sc_lock;
783 char lockname[16];
784
785 /* Starving free lists */
786 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
787 TAILQ_HEAD(, sge_fl) sfl;
788 struct callout sfl_callout;
789
790 struct mtx regwin_lock; /* for indirect reads and memory windows */
791
792 an_handler_t an_handler __aligned(CACHE_LINE_SIZE);
793 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */
794 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
795
796 #ifdef INVARIANTS
797 const char *last_op;
798 const void *last_op_thr;
799 #endif
800
801 int sc_do_rxcopy;
802 };
803
804 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
805 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
806 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
807 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
808
809 #define ASSERT_SYNCHRONIZED_OP(sc) \
810 KASSERT(IS_BUSY(sc) && \
811 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
812 ("%s: operation not synchronized.", __func__))
813
814 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
815 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
816 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
817 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
818
819 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
820 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
821 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
822 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
823 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
824
825 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
826 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
827 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
828 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
829
830 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
831 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
832 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
833 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
834 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
835
836 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
837 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
838 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
839 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
840 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
841
842 #define for_each_txq(pi, iter, q) \
843 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \
844 iter < pi->ntxq; ++iter, ++q)
845 #define for_each_rxq(pi, iter, q) \
846 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \
847 iter < pi->nrxq; ++iter, ++q)
848 #define for_each_ofld_txq(pi, iter, q) \
849 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \
850 iter < pi->nofldtxq; ++iter, ++q)
851 #define for_each_ofld_rxq(pi, iter, q) \
852 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \
853 iter < pi->nofldrxq; ++iter, ++q)
854 #define for_each_nm_txq(pi, iter, q) \
855 for (q = &pi->adapter->sge.nm_txq[pi->first_nm_txq], iter = 0; \
856 iter < pi->nnmtxq; ++iter, ++q)
857 #define for_each_nm_rxq(pi, iter, q) \
858 for (q = &pi->adapter->sge.nm_rxq[pi->first_nm_rxq], iter = 0; \
859 iter < pi->nnmrxq; ++iter, ++q)
860
861 #define IDXINCR(idx, incr, wrap) do { \
862 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
863 } while (0)
864 #define IDXDIFF(head, tail, wrap) \
865 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
866
867 /* One for errors, one for firmware events */
868 #define T4_EXTRA_INTR 2
869
870 static inline uint32_t
t4_read_reg(struct adapter * sc,uint32_t reg)871 t4_read_reg(struct adapter *sc, uint32_t reg)
872 {
873
874 return bus_space_read_4(sc->bt, sc->bh, reg);
875 }
876
877 static inline void
t4_write_reg(struct adapter * sc,uint32_t reg,uint32_t val)878 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
879 {
880
881 bus_space_write_4(sc->bt, sc->bh, reg, val);
882 }
883
884 static inline uint64_t
t4_read_reg64(struct adapter * sc,uint32_t reg)885 t4_read_reg64(struct adapter *sc, uint32_t reg)
886 {
887
888 return t4_bus_space_read_8(sc->bt, sc->bh, reg);
889 }
890
891 static inline void
t4_write_reg64(struct adapter * sc,uint32_t reg,uint64_t val)892 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
893 {
894
895 t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
896 }
897
898 static inline void
t4_os_pci_read_cfg1(struct adapter * sc,int reg,uint8_t * val)899 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
900 {
901
902 *val = pci_read_config(sc->dev, reg, 1);
903 }
904
905 static inline void
t4_os_pci_write_cfg1(struct adapter * sc,int reg,uint8_t val)906 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
907 {
908
909 pci_write_config(sc->dev, reg, val, 1);
910 }
911
912 static inline void
t4_os_pci_read_cfg2(struct adapter * sc,int reg,uint16_t * val)913 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
914 {
915
916 *val = pci_read_config(sc->dev, reg, 2);
917 }
918
919 static inline void
t4_os_pci_write_cfg2(struct adapter * sc,int reg,uint16_t val)920 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
921 {
922
923 pci_write_config(sc->dev, reg, val, 2);
924 }
925
926 static inline void
t4_os_pci_read_cfg4(struct adapter * sc,int reg,uint32_t * val)927 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
928 {
929
930 *val = pci_read_config(sc->dev, reg, 4);
931 }
932
933 static inline void
t4_os_pci_write_cfg4(struct adapter * sc,int reg,uint32_t val)934 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
935 {
936
937 pci_write_config(sc->dev, reg, val, 4);
938 }
939
940 static inline struct port_info *
adap2pinfo(struct adapter * sc,int idx)941 adap2pinfo(struct adapter *sc, int idx)
942 {
943
944 return (sc->port[idx]);
945 }
946
947 static inline void
t4_os_set_hw_addr(struct adapter * sc,int idx,uint8_t hw_addr[])948 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
949 {
950
951 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN);
952 }
953
954 static inline bool
is_10G_port(const struct port_info * pi)955 is_10G_port(const struct port_info *pi)
956 {
957
958 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
959 }
960
961 static inline bool
is_40G_port(const struct port_info * pi)962 is_40G_port(const struct port_info *pi)
963 {
964
965 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
966 }
967
968 static inline int
tx_resume_threshold(struct sge_eq * eq)969 tx_resume_threshold(struct sge_eq *eq)
970 {
971
972 /* not quite the same as qsize / 4, but this will do. */
973 return (eq->sidx / 4);
974 }
975
976 /* t4_main.c */
977 int t4_os_find_pci_capability(struct adapter *, int);
978 int t4_os_pci_save_state(struct adapter *);
979 int t4_os_pci_restore_state(struct adapter *);
980 void t4_os_portmod_changed(const struct adapter *, int);
981 void t4_os_link_changed(struct adapter *, int, int, int);
982 void t4_iterate(void (*)(struct adapter *, void *), void *);
983 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
984 int t4_register_an_handler(struct adapter *, an_handler_t);
985 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
986 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
987 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *);
988 void end_synchronized_op(struct adapter *, int);
989 int update_mac_settings(struct ifnet *, int);
990 int adapter_full_init(struct adapter *);
991 int adapter_full_uninit(struct adapter *);
992 int port_full_init(struct port_info *);
993 int port_full_uninit(struct port_info *);
994
995 #ifdef DEV_NETMAP
996 /* t4_netmap.c */
997 int create_netmap_ifnet(struct port_info *);
998 int destroy_netmap_ifnet(struct port_info *);
999 void t4_nm_intr(void *);
1000 #endif
1001
1002 /* t4_sge.c */
1003 void t4_sge_modload(void);
1004 void t4_sge_modunload(void);
1005 uint64_t t4_sge_extfree_refs(void);
1006 void t4_init_sge_cpl_handlers(struct adapter *);
1007 void t4_tweak_chip_settings(struct adapter *);
1008 int t4_read_chip_settings(struct adapter *);
1009 int t4_create_dma_tag(struct adapter *);
1010 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1011 struct sysctl_oid_list *);
1012 int t4_destroy_dma_tag(struct adapter *);
1013 int t4_setup_adapter_queues(struct adapter *);
1014 int t4_teardown_adapter_queues(struct adapter *);
1015 int t4_setup_port_queues(struct port_info *);
1016 int t4_teardown_port_queues(struct port_info *);
1017 void t4_intr_all(void *);
1018 void t4_intr(void *);
1019 void t4_intr_err(void *);
1020 void t4_intr_evt(void *);
1021 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1022 void t4_update_fl_bufsize(struct ifnet *);
1023 int parse_pkt(struct mbuf **);
1024 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1025 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1026 int tnl_cong(struct port_info *);
1027
1028 /* t4_tracer.c */
1029 struct t4_tracer;
1030 void t4_tracer_modload(void);
1031 void t4_tracer_modunload(void);
1032 void t4_tracer_port_detach(struct adapter *);
1033 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1034 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1035 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1036 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1037
1038 static inline struct wrqe *
alloc_wrqe(int wr_len,struct sge_wrq * wrq)1039 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1040 {
1041 int len = offsetof(struct wrqe, wr) + wr_len;
1042 struct wrqe *wr;
1043
1044 wr = malloc(len, M_CXGBE, M_NOWAIT);
1045 if (__predict_false(wr == NULL))
1046 return (NULL);
1047 wr->wr_len = wr_len;
1048 wr->wrq = wrq;
1049 return (wr);
1050 }
1051
1052 static inline void *
wrtod(struct wrqe * wr)1053 wrtod(struct wrqe *wr)
1054 {
1055 return (&wr->wr[0]);
1056 }
1057
1058 static inline void
free_wrqe(struct wrqe * wr)1059 free_wrqe(struct wrqe *wr)
1060 {
1061 free(wr, M_CXGBE);
1062 }
1063
1064 static inline void
t4_wrq_tx(struct adapter * sc,struct wrqe * wr)1065 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1066 {
1067 struct sge_wrq *wrq = wr->wrq;
1068
1069 TXQ_LOCK(wrq);
1070 t4_wrq_tx_locked(sc, wrq, wr);
1071 TXQ_UNLOCK(wrq);
1072 }
1073
1074 #endif
1075