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Searched defs:DstHi (Results 1 – 9 of 9) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/
DPPCExpandAtomicPseudoInsts.cpp106 Register DstHi = TRI->getSubReg(Dst, PPC::sub_gp8_x0); in expandMI() local
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp748 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi() local
DMipsSEFrameLowering.cpp269 Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC() local
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
DAArch64LegalizerInfo.cpp1419 auto DstHi = MRI.createGenericVirtualRegister(s64); in legalizeAtomicCmpxchg128() local
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonFrameLowering.cpp1945 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi); in expandLoadVec2() local
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp1947 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
2022 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
DAMDGPURegisterBankInfo.cpp1592 Register DstHi; in applyMappingMAD_64_32() local
DAMDGPUInstructionSelector.cpp364 Register DstHi = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() local
DSIISelLowering.cpp4285 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local