1 /*-
2 * Copyright (c) 2013-2015 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32 #ifndef __X86_IOMMU_INTEL_DMAR_H
33 #define __X86_IOMMU_INTEL_DMAR_H
34
35 /* Host or physical memory address, after translation. */
36 typedef uint64_t dmar_haddr_t;
37 /* Guest or bus address, before translation. */
38 typedef uint64_t dmar_gaddr_t;
39
40 struct dmar_qi_genseq {
41 u_int gen;
42 uint32_t seq;
43 };
44
45 struct dmar_map_entry {
46 dmar_gaddr_t start;
47 dmar_gaddr_t end;
48 dmar_gaddr_t free_after; /* Free space after the entry */
49 dmar_gaddr_t free_down; /* Max free space below the
50 current R/B tree node */
51 u_int flags;
52 TAILQ_ENTRY(dmar_map_entry) dmamap_link; /* Link for dmamap entries */
53 RB_ENTRY(dmar_map_entry) rb_entry; /* Links for domain entries */
54 TAILQ_ENTRY(dmar_map_entry) unroll_link; /* Link for unroll after
55 dmamap_load failure */
56 struct dmar_domain *domain;
57 struct dmar_qi_genseq gseq;
58 };
59
60 RB_HEAD(dmar_gas_entries_tree, dmar_map_entry);
61 RB_PROTOTYPE(dmar_gas_entries_tree, dmar_map_entry, rb_entry,
62 dmar_gas_cmp_entries);
63
64 #define DMAR_MAP_ENTRY_PLACE 0x0001 /* Fake entry */
65 #define DMAR_MAP_ENTRY_RMRR 0x0002 /* Permanent, not linked by
66 dmamap_link */
67 #define DMAR_MAP_ENTRY_MAP 0x0004 /* Busdma created, linked by
68 dmamap_link */
69 #define DMAR_MAP_ENTRY_UNMAPPED 0x0010 /* No backing pages */
70 #define DMAR_MAP_ENTRY_QI_NF 0x0020 /* qi task, do not free entry */
71 #define DMAR_MAP_ENTRY_READ 0x1000 /* Read permitted */
72 #define DMAR_MAP_ENTRY_WRITE 0x2000 /* Write permitted */
73 #define DMAR_MAP_ENTRY_SNOOP 0x4000 /* Snoop */
74 #define DMAR_MAP_ENTRY_TM 0x8000 /* Transient */
75
76 /*
77 * Locking annotations:
78 * (u) - Protected by dmar unit lock
79 * (d) - Protected by domain lock
80 * (c) - Immutable after initialization
81 */
82
83 /*
84 * The domain abstraction. Most non-constant members of the domain
85 * are locked by the owning dmar unit lock, not by the domain lock.
86 * Most important, dmar lock protects the contexts list.
87 *
88 * The domain lock protects the address map for the domain, and list
89 * of unload entries delayed.
90 *
91 * Page tables pages and pages content is protected by the vm object
92 * lock pgtbl_obj, which contains the page tables pages.
93 */
94 struct dmar_domain {
95 int domain; /* (c) DID, written in context entry */
96 int mgaw; /* (c) Real max address width */
97 int agaw; /* (c) Adjusted guest address width */
98 int pglvl; /* (c) The pagelevel */
99 int awlvl; /* (c) The pagelevel as the bitmask,
100 to set in context entry */
101 dmar_gaddr_t end; /* (c) Highest address + 1 in
102 the guest AS */
103 u_int ctx_cnt; /* (u) Number of contexts owned */
104 u_int refs; /* (u) Refs, including ctx */
105 struct dmar_unit *dmar; /* (c) */
106 struct mtx lock; /* (c) */
107 LIST_ENTRY(dmar_domain) link; /* (u) Member in the dmar list */
108 LIST_HEAD(, dmar_ctx) contexts; /* (u) */
109 vm_object_t pgtbl_obj; /* (c) Page table pages */
110 u_int flags; /* (u) */
111 u_int entries_cnt; /* (d) */
112 struct dmar_gas_entries_tree rb_root; /* (d) */
113 struct dmar_map_entries_tailq unload_entries; /* (d) Entries to
114 unload */
115 struct dmar_map_entry *first_place, *last_place; /* (d) */
116 struct task unload_task; /* (c) */
117 };
118
119 struct dmar_ctx {
120 struct bus_dma_tag_dmar ctx_tag; /* (c) Root tag */
121 uint16_t rid; /* (c) pci RID */
122 uint64_t last_fault_rec[2]; /* Last fault reported */
123 struct dmar_domain *domain; /* (c) */
124 LIST_ENTRY(dmar_ctx) link; /* (u) Member in the domain list */
125 u_int refs; /* (u) References from tags */
126 u_int flags; /* (u) */
127 u_long loads; /* atomic updates, for stat only */
128 u_long unloads; /* same */
129 };
130
131 #define DMAR_DOMAIN_GAS_INITED 0x0001
132 #define DMAR_DOMAIN_PGTBL_INITED 0x0002
133 #define DMAR_DOMAIN_IDMAP 0x0010 /* Domain uses identity
134 page table */
135 #define DMAR_DOMAIN_RMRR 0x0020 /* Domain contains RMRR entry,
136 cannot be turned off */
137
138 /* struct dmar_ctx flags */
139 #define DMAR_CTX_FAULTED 0x0001 /* Fault was reported,
140 last_fault_rec is valid */
141 #define DMAR_CTX_DISABLED 0x0002 /* Device is disabled, the
142 ephemeral reference is kept
143 to prevent context destruction */
144
145 #define DMAR_DOMAIN_PGLOCK(dom) VM_OBJECT_WLOCK((dom)->pgtbl_obj)
146 #define DMAR_DOMAIN_PGTRYLOCK(dom) VM_OBJECT_TRYWLOCK((dom)->pgtbl_obj)
147 #define DMAR_DOMAIN_PGUNLOCK(dom) VM_OBJECT_WUNLOCK((dom)->pgtbl_obj)
148 #define DMAR_DOMAIN_ASSERT_PGLOCKED(dom) \
149 VM_OBJECT_ASSERT_WLOCKED((dom)->pgtbl_obj)
150
151 #define DMAR_DOMAIN_LOCK(dom) mtx_lock(&(dom)->lock)
152 #define DMAR_DOMAIN_UNLOCK(dom) mtx_unlock(&(dom)->lock)
153 #define DMAR_DOMAIN_ASSERT_LOCKED(dom) mtx_assert(&(dom)->lock, MA_OWNED)
154
155 struct dmar_msi_data {
156 int irq;
157 int irq_rid;
158 struct resource *irq_res;
159 void *intr_handle;
160 int (*handler)(void *);
161 int msi_data_reg;
162 int msi_addr_reg;
163 int msi_uaddr_reg;
164 void (*enable_intr)(struct dmar_unit *);
165 void (*disable_intr)(struct dmar_unit *);
166 const char *name;
167 };
168
169 #define DMAR_INTR_FAULT 0
170 #define DMAR_INTR_QI 1
171 #define DMAR_INTR_TOTAL 2
172
173 struct dmar_unit {
174 device_t dev;
175 int unit;
176 uint16_t segment;
177 uint64_t base;
178
179 /* Resources */
180 int reg_rid;
181 struct resource *regs;
182
183 struct dmar_msi_data intrs[DMAR_INTR_TOTAL];
184
185 /* Hardware registers cache */
186 uint32_t hw_ver;
187 uint64_t hw_cap;
188 uint64_t hw_ecap;
189 uint32_t hw_gcmd;
190
191 /* Data for being a dmar */
192 struct mtx lock;
193 LIST_HEAD(, dmar_domain) domains;
194 struct unrhdr *domids;
195 vm_object_t ctx_obj;
196 u_int barrier_flags;
197
198 /* Fault handler data */
199 struct mtx fault_lock;
200 uint64_t *fault_log;
201 int fault_log_head;
202 int fault_log_tail;
203 int fault_log_size;
204 struct task fault_task;
205 struct taskqueue *fault_taskqueue;
206
207 /* QI */
208 int qi_enabled;
209 vm_offset_t inv_queue;
210 vm_size_t inv_queue_size;
211 uint32_t inv_queue_avail;
212 uint32_t inv_queue_tail;
213 volatile uint32_t inv_waitd_seq_hw; /* hw writes there on wait
214 descr completion */
215 uint64_t inv_waitd_seq_hw_phys;
216 uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */
217 u_int inv_waitd_gen; /* seq number generation AKA seq overflows */
218 u_int inv_seq_waiters; /* count of waiters for seq */
219 u_int inv_queue_full; /* informational counter */
220
221 /* IR */
222 int ir_enabled;
223 vm_paddr_t irt_phys;
224 dmar_irte_t *irt;
225 u_int irte_cnt;
226 vmem_t *irtids;
227
228 /* Delayed freeing of map entries queue processing */
229 struct dmar_map_entries_tailq tlb_flush_entries;
230 struct task qi_task;
231 struct taskqueue *qi_taskqueue;
232
233 /* Busdma delayed map load */
234 struct task dmamap_load_task;
235 TAILQ_HEAD(, bus_dmamap_dmar) delayed_maps;
236 struct taskqueue *delayed_taskqueue;
237
238 int dma_enabled;
239 };
240
241 #define DMAR_LOCK(dmar) mtx_lock(&(dmar)->lock)
242 #define DMAR_UNLOCK(dmar) mtx_unlock(&(dmar)->lock)
243 #define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->lock, MA_OWNED)
244
245 #define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock)
246 #define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock)
247 #define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED)
248
249 #define DMAR_IS_COHERENT(dmar) (((dmar)->hw_ecap & DMAR_ECAP_C) != 0)
250 #define DMAR_HAS_QI(dmar) (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0)
251 #define DMAR_X2APIC(dmar) \
252 (x2apic_mode && ((dmar)->hw_ecap & DMAR_ECAP_EIM) != 0)
253
254 /* Barrier ids */
255 #define DMAR_BARRIER_RMRR 0
256 #define DMAR_BARRIER_USEQ 1
257
258 struct dmar_unit *dmar_find(device_t dev);
259 struct dmar_unit *dmar_find_hpet(device_t dev, uint16_t *rid);
260 struct dmar_unit *dmar_find_ioapic(u_int apic_id, uint16_t *rid);
261
262 u_int dmar_nd2mask(u_int nd);
263 bool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl);
264 int domain_set_agaw(struct dmar_domain *domain, int mgaw);
265 int dmar_maxaddr2mgaw(struct dmar_unit *unit, dmar_gaddr_t maxaddr,
266 bool allow_less);
267 vm_pindex_t pglvl_max_pages(int pglvl);
268 int domain_is_sp_lvl(struct dmar_domain *domain, int lvl);
269 dmar_gaddr_t pglvl_page_size(int total_pglvl, int lvl);
270 dmar_gaddr_t domain_page_size(struct dmar_domain *domain, int lvl);
271 int calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size,
272 dmar_gaddr_t *isizep);
273 struct vm_page *dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags);
274 void dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags);
275 void *dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags,
276 struct sf_buf **sf);
277 void dmar_unmap_pgtbl(struct sf_buf *sf);
278 int dmar_load_root_entry_ptr(struct dmar_unit *unit);
279 int dmar_inv_ctx_glob(struct dmar_unit *unit);
280 int dmar_inv_iotlb_glob(struct dmar_unit *unit);
281 int dmar_flush_write_bufs(struct dmar_unit *unit);
282 void dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst);
283 void dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst);
284 void dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst);
285 int dmar_enable_translation(struct dmar_unit *unit);
286 int dmar_disable_translation(struct dmar_unit *unit);
287 int dmar_load_irt_ptr(struct dmar_unit *unit);
288 int dmar_enable_ir(struct dmar_unit *unit);
289 int dmar_disable_ir(struct dmar_unit *unit);
290 bool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id);
291 void dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id);
292
293 int dmar_fault_intr(void *arg);
294 void dmar_enable_fault_intr(struct dmar_unit *unit);
295 void dmar_disable_fault_intr(struct dmar_unit *unit);
296 int dmar_init_fault_log(struct dmar_unit *unit);
297 void dmar_fini_fault_log(struct dmar_unit *unit);
298
299 int dmar_qi_intr(void *arg);
300 void dmar_enable_qi_intr(struct dmar_unit *unit);
301 void dmar_disable_qi_intr(struct dmar_unit *unit);
302 int dmar_init_qi(struct dmar_unit *unit);
303 void dmar_fini_qi(struct dmar_unit *unit);
304 void dmar_qi_invalidate_locked(struct dmar_domain *domain, dmar_gaddr_t start,
305 dmar_gaddr_t size, struct dmar_qi_genseq *pseq);
306 void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit);
307 void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit);
308 void dmar_qi_invalidate_iec_glob(struct dmar_unit *unit);
309 void dmar_qi_invalidate_iec(struct dmar_unit *unit, u_int start, u_int cnt);
310
311 vm_object_t domain_get_idmap_pgtbl(struct dmar_domain *domain,
312 dmar_gaddr_t maxaddr);
313 void put_idmap_pgtbl(vm_object_t obj);
314 int domain_map_buf(struct dmar_domain *domain, dmar_gaddr_t base,
315 dmar_gaddr_t size, vm_page_t *ma, uint64_t pflags, int flags);
316 int domain_unmap_buf(struct dmar_domain *domain, dmar_gaddr_t base,
317 dmar_gaddr_t size, int flags);
318 void domain_flush_iotlb_sync(struct dmar_domain *domain, dmar_gaddr_t base,
319 dmar_gaddr_t size);
320 int domain_alloc_pgtbl(struct dmar_domain *domain);
321 void domain_free_pgtbl(struct dmar_domain *domain);
322
323 struct dmar_ctx *dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev,
324 bool rmrr);
325 struct dmar_ctx *dmar_get_ctx_for_dev(struct dmar_unit *dmar, device_t dev,
326 uint16_t rid, bool id_mapped, bool rmrr_init);
327 int dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx);
328 void dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx);
329 void dmar_free_ctx(struct dmar_ctx *ctx);
330 struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid);
331 void dmar_domain_unload_entry(struct dmar_map_entry *entry, bool free);
332 void dmar_domain_unload(struct dmar_domain *domain,
333 struct dmar_map_entries_tailq *entries, bool cansleep);
334 void dmar_domain_free_entry(struct dmar_map_entry *entry, bool free);
335
336 int dmar_init_busdma(struct dmar_unit *unit);
337 void dmar_fini_busdma(struct dmar_unit *unit);
338 device_t dmar_get_requester(device_t dev, uint16_t *rid);
339
340 void dmar_gas_init_domain(struct dmar_domain *domain);
341 void dmar_gas_fini_domain(struct dmar_domain *domain);
342 struct dmar_map_entry *dmar_gas_alloc_entry(struct dmar_domain *domain,
343 u_int flags);
344 void dmar_gas_free_entry(struct dmar_domain *domain,
345 struct dmar_map_entry *entry);
346 void dmar_gas_free_space(struct dmar_domain *domain,
347 struct dmar_map_entry *entry);
348 int dmar_gas_map(struct dmar_domain *domain,
349 const struct bus_dma_tag_common *common, dmar_gaddr_t size, int offset,
350 u_int eflags, u_int flags, vm_page_t *ma, struct dmar_map_entry **res);
351 void dmar_gas_free_region(struct dmar_domain *domain,
352 struct dmar_map_entry *entry);
353 int dmar_gas_map_region(struct dmar_domain *domain,
354 struct dmar_map_entry *entry, u_int eflags, u_int flags, vm_page_t *ma);
355 int dmar_gas_reserve_region(struct dmar_domain *domain, dmar_gaddr_t start,
356 dmar_gaddr_t end);
357
358 void dmar_dev_parse_rmrr(struct dmar_domain *domain, device_t dev,
359 struct dmar_map_entries_tailq *rmrr_entries);
360 int dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar);
361
362 void dmar_quirks_post_ident(struct dmar_unit *dmar);
363 void dmar_quirks_pre_use(struct dmar_unit *dmar);
364
365 int dmar_init_irt(struct dmar_unit *unit);
366 void dmar_fini_irt(struct dmar_unit *unit);
367
368 #define DMAR_GM_CANWAIT 0x0001
369 #define DMAR_GM_CANSPLIT 0x0002
370
371 #define DMAR_PGF_WAITOK 0x0001
372 #define DMAR_PGF_ZERO 0x0002
373 #define DMAR_PGF_ALLOC 0x0004
374 #define DMAR_PGF_NOALLOC 0x0008
375 #define DMAR_PGF_OBJL 0x0010
376
377 extern dmar_haddr_t dmar_high;
378 extern int haw;
379 extern int dmar_tbl_pagecnt;
380 extern int dmar_match_verbose;
381 extern int dmar_check_free;
382
383 static inline uint32_t
dmar_read4(const struct dmar_unit * unit,int reg)384 dmar_read4(const struct dmar_unit *unit, int reg)
385 {
386
387 return (bus_read_4(unit->regs, reg));
388 }
389
390 static inline uint64_t
dmar_read8(const struct dmar_unit * unit,int reg)391 dmar_read8(const struct dmar_unit *unit, int reg)
392 {
393 #ifdef __i386__
394 uint32_t high, low;
395
396 low = bus_read_4(unit->regs, reg);
397 high = bus_read_4(unit->regs, reg + 4);
398 return (low | ((uint64_t)high << 32));
399 #else
400 return (bus_read_8(unit->regs, reg));
401 #endif
402 }
403
404 static inline void
dmar_write4(const struct dmar_unit * unit,int reg,uint32_t val)405 dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val)
406 {
407
408 KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) ==
409 (unit->hw_gcmd & DMAR_GCMD_TE),
410 ("dmar%d clearing TE 0x%08x 0x%08x", unit->unit,
411 unit->hw_gcmd, val));
412 bus_write_4(unit->regs, reg, val);
413 }
414
415 static inline void
dmar_write8(const struct dmar_unit * unit,int reg,uint64_t val)416 dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val)
417 {
418
419 KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write"));
420 #ifdef __i386__
421 uint32_t high, low;
422
423 low = val;
424 high = val >> 32;
425 bus_write_4(unit->regs, reg, low);
426 bus_write_4(unit->regs, reg + 4, high);
427 #else
428 bus_write_8(unit->regs, reg, val);
429 #endif
430 }
431
432 /*
433 * dmar_pte_store and dmar_pte_clear ensure that on i386, 32bit writes
434 * are issued in the correct order. For store, the lower word,
435 * containing the P or R and W bits, is set only after the high word
436 * is written. For clear, the P bit is cleared first, then the high
437 * word is cleared.
438 *
439 * dmar_pte_update updates the pte. For amd64, the update is atomic.
440 * For i386, it first disables the entry by clearing the word
441 * containing the P bit, and then defer to dmar_pte_store. The locked
442 * cmpxchg8b is probably available on any machine having DMAR support,
443 * but interrupt translation table may be mapped uncached.
444 */
445 static inline void
dmar_pte_store1(volatile uint64_t * dst,uint64_t val)446 dmar_pte_store1(volatile uint64_t *dst, uint64_t val)
447 {
448 #ifdef __i386__
449 volatile uint32_t *p;
450 uint32_t hi, lo;
451
452 hi = val >> 32;
453 lo = val;
454 p = (volatile uint32_t *)dst;
455 *(p + 1) = hi;
456 *p = lo;
457 #else
458 *dst = val;
459 #endif
460 }
461
462 static inline void
dmar_pte_store(volatile uint64_t * dst,uint64_t val)463 dmar_pte_store(volatile uint64_t *dst, uint64_t val)
464 {
465
466 KASSERT(*dst == 0, ("used pte %p oldval %jx newval %jx",
467 dst, (uintmax_t)*dst, (uintmax_t)val));
468 dmar_pte_store1(dst, val);
469 }
470
471 static inline void
dmar_pte_update(volatile uint64_t * dst,uint64_t val)472 dmar_pte_update(volatile uint64_t *dst, uint64_t val)
473 {
474
475 #ifdef __i386__
476 volatile uint32_t *p;
477
478 p = (volatile uint32_t *)dst;
479 *p = 0;
480 #endif
481 dmar_pte_store1(dst, val);
482 }
483
484 static inline void
dmar_pte_clear(volatile uint64_t * dst)485 dmar_pte_clear(volatile uint64_t *dst)
486 {
487 #ifdef __i386__
488 volatile uint32_t *p;
489
490 p = (volatile uint32_t *)dst;
491 *p = 0;
492 *(p + 1) = 0;
493 #else
494 *dst = 0;
495 #endif
496 }
497
498 static inline bool
dmar_test_boundary(dmar_gaddr_t start,dmar_gaddr_t size,dmar_gaddr_t boundary)499 dmar_test_boundary(dmar_gaddr_t start, dmar_gaddr_t size,
500 dmar_gaddr_t boundary)
501 {
502
503 if (boundary == 0)
504 return (true);
505 return (start + size <= ((start + boundary) & ~(boundary - 1)));
506 }
507
508 #ifdef INVARIANTS
509 #define TD_PREP_PINNED_ASSERT \
510 int old_td_pinned; \
511 old_td_pinned = curthread->td_pinned
512 #define TD_PINNED_ASSERT \
513 KASSERT(curthread->td_pinned == old_td_pinned, \
514 ("pin count leak: %d %d %s:%d", curthread->td_pinned, \
515 old_td_pinned, __FILE__, __LINE__))
516 #else
517 #define TD_PREP_PINNED_ASSERT
518 #define TD_PINNED_ASSERT
519 #endif
520
521 #endif
522