1 /* $OpenBSD: dmavar.h,v 1.5 2003/06/05 12:27:02 deraadt Exp $ */ 2 /* $NetBSD: dmavar.h,v 1.11 1996/11/27 21:49:53 pk Exp $ */ 3 4 /* 5 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 struct dma_softc { 28 struct device sc_dev; /* us as a device */ 29 struct sbusdev sc_sd; /* sbus device */ 30 struct esp_softc *sc_esp; /* my scsi */ 31 struct le_softc *sc_le; /* my ethernet */ 32 struct dma_regs *sc_regs; /* the registers */ 33 int sc_active; /* DMA active ? */ 34 u_int sc_rev; /* revision */ 35 int sc_node; /* PROM node ID */ 36 int sc_burst; /* DVMA burst size in effect */ 37 caddr_t sc_dvmakaddr; /* DVMA cookies */ 38 caddr_t sc_dvmaaddr; /* */ 39 size_t sc_dmasize; 40 caddr_t *sc_dmaaddr; 41 size_t *sc_dmalen; 42 void (*reset)(struct dma_softc *); /* reset routine */ 43 void (*enintr)(struct dma_softc *); /* enable interrupts */ 44 int (*isintr)(struct dma_softc *); /* interrupt ? */ 45 int (*intr)(struct dma_softc *); /* interrupt ! */ 46 int (*setup)(struct dma_softc *, caddr_t *, size_t *, int, size_t *); 47 void (*go)(struct dma_softc *); 48 }; 49 50 #define DMACSR(sc) (sc->sc_regs->csr) 51 #define DMADDR(sc) (sc->sc_regs->addr) 52 #define DMACNT(sc) (sc->sc_regs->bcnt) 53 54 /* DMA engine functions */ 55 #define DMA_ENINTR(r) (((r)->enintr)(r)) 56 #define DMA_ISINTR(r) (((r)->isintr)(r)) 57 #define DMA_RESET(r) (((r)->reset)(r)) 58 #define DMA_INTR(r) (((r)->intr)(r)) 59 #define DMA_ISACTIVE(r) ((r)->sc_active) 60 #define DMA_SETUP(a, b, c, d, e) (((a)->setup)(a, b, c, d, e)) 61 #define DMA_GO(r) (((r)->go)(r)) 62