| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| HD | X86FlagsCopyLowering.cpp | 753 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg() local
783 unsigned &CondReg = CondRegs[Cond]; in rewriteSetCC() local
826 unsigned &CondReg = CondRegs[Cond]; in rewriteArithmetic() local
900 unsigned CondReg; in rewriteMI() local
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| HD | X86FastISel.cpp | 2111 Register CondReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
2312 Register CondReg = getRegForValue(Cond); in X86FastEmitPseudoSelect() local
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| HD | SIPreEmitPeephole.cpp | 90 const unsigned CondReg = TRI->getVCC(); in optimizeVccBranch() local
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| HD | SIOptimizeExecMaskingPreRA.cpp | 39 MCRegister CondReg; member in __anon1155d0030111::SIOptimizeExecMaskingPreRA
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| HD | SIInstrInfo.cpp | 3142 static void preserveCondRegFlags(MachineOperand &CondReg, in preserveCondRegFlags()
3197 MachineOperand &CondReg = CondBr->getOperand(1); in insertBranch() local
6281 Register CondReg; in emitLoadScalarOpsFromVGPRLoop() local
7138 Register CondReg = Inst.getOperand(1).getReg(); in moveToVALUImpl() local
7296 Register CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass()); in moveToVALUImpl() local
7555 Register CondReg = Cond.getReg(); in lowerSelect() local
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| HD | AMDGPURegisterBankInfo.cpp | 861 Register CondReg; in executeInWaterfallLoop() local
2364 Register CondReg = MI.getOperand(0).getReg(); in applyMappingImpl() local
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| HD | AMDGPUMachineCFGStructurizer.cpp | 1846 Register CondReg = Cond[0].getReg(); in ensureCondIsNotKilled() local
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| HD | AMDGPUISelDAGToDAG.cpp | 2484 Register CondReg = UseSCCBr ? AMDGPU::SCC : TRI->getVCC(); in SelectBRCOND() local
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| HD | AMDGPUInstructionSelector.cpp | 2829 Register CondReg = CondOp.getReg(); in selectG_BRCOND() local
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| HD | SIISelLowering.cpp | 4476 Register CondReg = MRI.createVirtualRegister(BoolRC); in emitLoadM0FromVGPRLoop() local
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| HD | WebAssemblyFastISel.cpp | 916 unsigned CondReg = in selectSelect() local
1321 unsigned CondReg = getRegForI1Value(Br->getCondition(), Br->getParent(), Not); in selectBr() local
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| HD | MipsFastISel.cpp | 961 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
1040 Register CondReg = getRegForValue(Cond); in selectSelect() local
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| HD | AArch64FastISel.cpp | 2476 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2490 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2716 Register CondReg = getRegForValue(Cond); in selectSelect() local
2765 Register CondReg = getRegForValue(Cond); in selectSelect() local
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| HD | ARMInstructionSelector.cpp | 776 auto CondReg = MIB.getReg(1); in selectSelect() local
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| HD | ARMFastISel.cpp | 1610 Register CondReg = getRegForValue(I->getOperand(0)); in SelectSelect() local
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| HD | RISCVInstructionSelector.cpp | 444 static void getOperandsForBranch(Register CondReg, MachineRegisterInfo &MRI, in getOperandsForBranch()
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| HD | X86InstructionSelector.cpp | 1493 const Register CondReg = I.getOperand(0).getReg(); in selectCondBranch() local
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| HD | PPCFastISel.cpp | 785 Register CondReg = createResultReg(&PPC::CRRCRegClass); in SelectBranch() local
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| HD | AArch64InstructionSelector.cpp | 1816 Register CondReg = I.getOperand(0).getReg(); in selectCompareBranch() local
3414 const Register CondReg = Sel.getCondReg(); in select() local
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| HD | LegalizerHelper.cpp | 6243 Register CondReg = MI.getOperand(1).getReg(); in narrowScalarSelect() local
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