1 /* $NetBSD: cpuconf.h,v 1.8 2003/09/06 08:55:42 rearnsha Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * 37 * $FreeBSD$ 38 * 39 */ 40 41 #ifndef _MACHINE_CPUCONF_H_ 42 #define _MACHINE_CPUCONF_H_ 43 44 /* 45 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 46 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE 47 * YOU ARE ADDING SUPPORT FOR. 48 */ 49 50 /* 51 * Step 1: Count the number of CPU types configured into the kernel. 52 */ 53 #define CPU_NTYPES (defined(CPU_ARM9) + \ 54 defined(CPU_ARM9E) + \ 55 defined(CPU_ARM1176) + \ 56 defined(CPU_XSCALE_80321) + \ 57 defined(CPU_XSCALE_PXA2X0) + \ 58 defined(CPU_FA526) + \ 59 defined(CPU_XSCALE_IXP425)) + \ 60 defined(CPU_CORTEXA) + \ 61 defined(CPU_KRAIT) + \ 62 defined(CPU_MV_PJ4B) 63 64 /* 65 * Step 2: Determine which ARM architecture versions are configured. 66 */ 67 #if defined(CPU_ARM9) || defined(CPU_FA526) 68 #define ARM_ARCH_4 1 69 #else 70 #define ARM_ARCH_4 0 71 #endif 72 73 #if (defined(CPU_ARM9E) || \ 74 defined(CPU_XSCALE_80321) || \ 75 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ 76 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)) 77 #define ARM_ARCH_5 1 78 #else 79 #define ARM_ARCH_5 0 80 #endif 81 82 #if !defined(ARM_ARCH_6) 83 #if defined(CPU_ARM1176) 84 #define ARM_ARCH_6 1 85 #else 86 #define ARM_ARCH_6 0 87 #endif 88 #endif 89 90 #if defined(CPU_CORTEXA) || defined(CPU_KRAIT) || defined(CPU_MV_PJ4B) 91 #define ARM_ARCH_7A 1 92 #else 93 #define ARM_ARCH_7A 0 94 #endif 95 96 #define ARM_NARCH (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 | ARM_ARCH_7A) 97 98 /* 99 * Compatibility for userland builds that have no CPUTYPE defined. Use the ARCH 100 * constants predefined by the compiler to define our old-school arch constants. 101 * This is a stopgap measure to tide us over until the conversion of all code 102 * to the newer ACLE constants defined by ARM (see acle-compat.h). 103 */ 104 #if ARM_NARCH == 0 105 #if defined(__ARM_ARCH_4T__) 106 #undef ARM_ARCH_4 107 #undef ARM_NARCH 108 #define ARM_ARCH_4 1 109 #define ARM_NARCH 1 110 #define CPU_ARM9 1 111 #elif defined(__ARM_ARCH_6ZK__) 112 #undef ARM_ARCH_6 113 #undef ARM_NARCH 114 #define ARM_ARCH_6 1 115 #define ARM_NARCH 1 116 #define CPU_ARM1176 1 117 #endif 118 #endif 119 120 #if ARM_NARCH == 0 && !defined(KLD_MODULE) && defined(_KERNEL) 121 #error ARM_NARCH is 0 122 #endif 123 124 #if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7A 125 /* 126 * We could support Thumb code on v4T, but the lack of clean interworking 127 * makes that hard. 128 */ 129 #define THUMB_CODE 130 #endif 131 132 /* 133 * Step 3: Define which MMU classes are configured: 134 * 135 * ARM_MMU_MEMC Prehistoric, external memory controller 136 * and MMU for ARMv2 CPUs. 137 * 138 * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARMv4 and v5. 139 * 140 * ARM_MMU_V6 ARMv6 MMU. 141 * 142 * ARM_MMU_V7 ARMv7 MMU. 143 * 144 * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 145 * MMU, but also has several extensions which 146 * require different PTE layout to use. 147 */ 148 #if (defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_FA526)) 149 #define ARM_MMU_GENERIC 1 150 #else 151 #define ARM_MMU_GENERIC 0 152 #endif 153 154 #if defined(CPU_ARM1176) 155 #define ARM_MMU_V6 1 156 #else 157 #define ARM_MMU_V6 0 158 #endif 159 160 #if defined(CPU_CORTEXA) || defined(CPU_KRAIT) || defined(CPU_MV_PJ4B) 161 #define ARM_MMU_V7 1 162 #else 163 #define ARM_MMU_V7 0 164 #endif 165 166 #if (defined(CPU_XSCALE_80321) || \ 167 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 168 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)) 169 #define ARM_MMU_XSCALE 1 170 #else 171 #define ARM_MMU_XSCALE 0 172 #endif 173 174 #define ARM_NMMUS (ARM_MMU_GENERIC + ARM_MMU_V6 + \ 175 ARM_MMU_V7 + ARM_MMU_XSCALE) 176 #if ARM_NMMUS == 0 && !defined(KLD_MODULE) && defined(_KERNEL) 177 #error ARM_NMMUS is 0 178 #endif 179 180 /* 181 * Step 4: Define features that may be present on a subset of CPUs 182 * 183 * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 184 */ 185 186 #if (defined(CPU_XSCALE_80321) || \ 187 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)) 188 #define ARM_XSCALE_PMU 1 189 #else 190 #define ARM_XSCALE_PMU 0 191 #endif 192 193 #if defined(CPU_XSCALE_81342) 194 #define CPU_XSCALE_CORE3 195 #endif 196 #endif /* _MACHINE_CPUCONF_H_ */ 197