1 /* $OpenBSD: cpuvar.h,v 1.9 2003/11/03 07:01:33 david Exp $ */ 2 /* $NetBSD: cpuvar.h,v 1.4 1997/07/06 21:14:25 pk Exp $ */ 3 4 /* 5 * Copyright (c) 1996 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE 31 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _SPARC_CPUVAR_H 41 #define _SPARC_CPUVAR_H 42 43 #include <sys/device.h> 44 45 #include <sparc/sparc/cache.h> /* for cacheinfo */ 46 47 /* 48 * CPU/MMU module information. 49 * There is one of these for each "mainline" CPU module we support. 50 * The information contained in the structure is used only during 51 * auto-configuration of the CPUs; some fields are copied into the 52 * per-cpu data structure (cpu_softc) for easy access during normal 53 * operation. 54 */ 55 struct cpu_softc; 56 struct module_info { 57 int cpu_type; 58 enum vactype vactype; 59 void (*cpu_match)(struct cpu_softc *, struct module_info *, int); 60 void (*getcacheinfo)(struct cpu_softc *sc, int node); 61 void (*hotfix)(struct cpu_softc *); 62 void (*mmu_enable)(void); 63 void (*cache_enable)(void); 64 int ncontext; /* max. # of contexts (we use) */ 65 66 void (*get_syncflt)(void); 67 int (*get_asyncflt)(u_int *, u_int *); 68 void (*cache_flush)(caddr_t, u_int); 69 void (*vcache_flush_page)(int); 70 void (*vcache_flush_segment)(int, int); 71 void (*vcache_flush_region)(int); 72 void (*vcache_flush_context)(void); 73 void (*pcache_flush_line)(int, int); 74 void (*pure_vcache_flush)(void); 75 void (*cache_flush_all)(void); 76 void (*memerr)(unsigned, u_int, u_int, struct trapframe *); 77 }; 78 79 80 /* 81 * The cpu_softc structure. This structure maintains information about one 82 * currently installed CPU (there may be several of these if the machine 83 * supports multiple CPUs, as on some Sun4m architectures). The information 84 * in this structure supersedes the old "cpumod", "mmumod", and similar 85 * fields. 86 */ 87 88 struct cpu_softc { 89 struct device dv; /* generic device info */ 90 91 int node; /* PROM node for this CPU */ 92 93 /* CPU information */ 94 char *cpu_name; /* CPU model */ 95 int cpu_impl; /* CPU implementation code */ 96 int cpu_vers; /* CPU version code */ 97 int mmu_impl; /* MMU implementation code */ 98 int mmu_vers; /* MMU version code */ 99 int master; /* 1 if this is bootup CPU */ 100 101 int mid; /* Module ID for MP systems */ 102 int mbus; /* 1 if CPU is on MBus */ 103 int mxcc; /* 1 if a MBus-level MXCC is present */ 104 105 caddr_t mailbox; /* VA of CPU's mailbox */ 106 107 108 int mmu_ncontext; /* Number of contexts supported */ 109 int mmu_nregion; /* Number of regions supported */ 110 int mmu_nsegment; /* [4/4c] Segments */ 111 int mmu_npmeg; /* [4/4c] Pmegs */ 112 int sun4_mmu3l; /* [4]: 3-level MMU present */ 113 #if defined(SUN4_MMU3L) 114 #define HASSUN4_MMU3L (cpuinfo.sun4_mmu3l) 115 #else 116 #define HASSUN4_MMU3L (0) 117 #endif 118 119 /* Context administration */ 120 int *ctx_tbl; /* [4m] SRMMU-edible context table */ 121 union ctxinfo *ctxinfo; 122 union ctxinfo *ctx_freelist; /* context free list */ 123 int ctx_kick; /* allocation rover when none free */ 124 int ctx_kickdir; /* ctx_kick roves both directions */ 125 126 /* MMU tables that map `cpuinfo'' on each CPU */ 127 int *L1_ptps; /* XXX */ 128 129 /* XXX - of these, we currently use only cpu_type */ 130 int arch; /* Architecture: CPU_SUN4x */ 131 int class; /* Class: SuperSPARC, microSPARC... */ 132 int classlvl; /* Iteration in class: 1, 2, etc. */ 133 int classsublvl; /* stepping in class (version) */ 134 int cpu_type; /* Type: see CPUTYP_xxx below */ 135 136 int hz; /* Clock speed */ 137 138 /* Cache information */ 139 struct cacheinfo cacheinfo; /* see cache.h */ 140 141 /* FPU information */ 142 int fpupresent; /* true if FPU is present */ 143 int fpuvers; /* FPU revision */ 144 145 /* various flags to workaround anomalies in chips */ 146 int flags; /* see CPUFLG_xxx, below */ 147 148 /* 149 * The following pointers point to processes that are somehow 150 * associated with this CPU--running on it, using its FPU, 151 * etc. 152 * 153 * XXXMP: much more needs to go here 154 */ 155 struct proc *fpproc; /* FPU owner */ 156 157 /* 158 * The following are function pointers to do interesting CPU-dependent 159 * things without having to do type-tests all the time 160 */ 161 162 /* bootup things: access to physical memory */ 163 u_int (*read_physmem)(u_int addr, int space); 164 void (*write_physmem)(u_int addr, u_int data); 165 void (*cache_tablewalks)(void); 166 void (*mmu_enable)(void); 167 void (*hotfix)(struct cpu_softc *); 168 169 /* locore defined: */ 170 void (*get_syncflt)(void); /* Not C-callable */ 171 int (*get_asyncflt)(u_int *, u_int *); 172 173 /* Synchronous Fault Status; temporary storage */ 174 struct { 175 int sfsr; 176 int sfva; 177 } syncfltdump; 178 179 /* Cache handling functions */ 180 void (*cache_enable)(void); 181 void (*cache_flush)(caddr_t, u_int); 182 void (*vcache_flush_page)(int); 183 void (*vcache_flush_segment)(int, int); 184 void (*vcache_flush_region)(int); 185 void (*vcache_flush_context)(void); 186 void (*pcache_flush_line)(int, int); 187 void (*pure_vcache_flush)(void); 188 void (*cache_flush_all)(void); 189 190 #ifdef SUN4M 191 /* hardware-assisted block operation routines */ 192 void (*hwbcopy)(const void *from, void *to, size_t len); 193 void (*hwbzero)(void *buf, size_t len); 194 195 /* routine to clear mbus-sbus buffers */ 196 void (*mbusflush)(void); 197 #endif 198 199 /* 200 * Memory error handler; parity errors, unhandled NMIs and other 201 * unrecoverable faults end up here. 202 */ 203 void (*memerr)(unsigned, u_int, u_int, struct trapframe *); 204 /* XXX: Add more here! */ 205 }; 206 207 /* 208 * CPU architectures 209 */ 210 #define CPUARCH_UNKNOWN 0 211 #define CPUARCH_SUN4 1 212 #define CPUARCH_SUN4C 2 213 #define CPUARCH_SUN4M 3 214 #define CPUARCH_SUN4D 4 215 #define CPUARCH_SUN4U 5 216 217 /* 218 * CPU classes 219 */ 220 #define CPUCLS_UNKNOWN 0 221 222 #if defined(SUN4) 223 #define CPUCLS_SUN4 1 224 #endif 225 226 #if defined(SUN4C) 227 #define CPUCLS_SUN4C 5 228 #endif 229 230 #if defined(SUN4M) 231 #define CPUCLS_MICROSPARC 10 /* MicroSPARC-II */ 232 #define CPUCLS_SUPERSPARC 11 /* Generic SuperSPARC */ 233 #define CPUCLS_HYPERSPARC 12 /* Ross HyperSPARC RT620 */ 234 #endif 235 236 /* 237 * CPU types. Each of these should uniquely identify one platform/type of 238 * system, i.e. "MBus-based 75 MHz SuperSPARC-II with ECache" is 239 * CPUTYP_SS2_MBUS_MXCC. The general form is 240 * CPUTYP_proctype_bustype_cachetype_etc_etc 241 * 242 * XXX: This is far from complete/comprehensive 243 * XXX: ADD SUN4, SUN4C TYPES 244 */ 245 #define CPUTYP_UNKNOWN 0 246 247 #define CPUTYP_4_100 1 /* Sun4/100 */ 248 #define CPUTYP_4_200 2 /* Sun4/200 */ 249 #define CPUTYP_4_300 3 /* Sun4/300 */ 250 #define CPUTYP_4_400 4 /* Sun4/400 */ 251 252 #define CPUTYP_SLC 10 /* SPARCstation SLC */ 253 #define CPUTYP_ELC 11 /* SPARCstation ELC */ 254 #define CPUTYP_IPX 12 /* SPARCstation IPX */ 255 #define CPUTYP_IPC 13 /* SPARCstation IPC */ 256 #define CPUTYP_1 14 /* SPARCstation 1 */ 257 #define CPUTYP_1P 15 /* SPARCstation 1+ */ 258 #define CPUTYP_2 16 /* SPARCstation 2 */ 259 260 /* We classify the Sun4m's by feature, not by model (XXX: do same for 4/4c) */ 261 #define CPUTYP_SS2_MBUS_MXCC 20 /* SuperSPARC-II, Mbus, MXCC (SS20) */ 262 #define CPUTYP_SS1_MBUS_MXCC 21 /* SuperSPARC-I, Mbus, MXCC (SS10) */ 263 #define CPUTYP_SS2_MBUS_NOMXCC 22 /* SuperSPARC-II, on MBus w/o MXCC */ 264 #define CPUTYP_SS1_MBUS_NOMXCC 23 /* SuperSPARC-I, on MBus w/o MXCC */ 265 #define CPUTYP_MS2 24 /* MicroSPARC-2 */ 266 #define CPUTYP_MS1 25 /* MicroSPARC-1 */ 267 #define CPUTYP_HS_MBUS 26 /* MBus-based HyperSPARC */ 268 #define CPUTYP_CYPRESS 27 /* MBus-based Cypress */ 269 270 /* 271 * CPU flags 272 */ 273 #define CPUFLG_CACHEPAGETABLES 0x1 /* caching pagetables OK on Sun4m */ 274 #define CPUFLG_CACHEIOMMUTABLES 0x2 /* caching IOMMU translations OK */ 275 #define CPUFLG_CACHEDVMA 0x4 /* DVMA goes through cache */ 276 #define CPUFLG_SUN4CACHEBUG 0x8 /* trap page can't be cached */ 277 #define CPUFLG_CACHE_MANDATORY 0x10 /* if cache is on, don't use 278 uncached access */ 279 280 /* 281 * Related function prototypes 282 */ 283 void getcpuinfo(struct cpu_softc *sc, int node); 284 void mmu_install_tables(struct cpu_softc *); 285 void pmap_alloc_cpu(struct cpu_softc *); 286 287 #define cpuinfo (*(struct cpu_softc *)CPUINFO_VA) 288 #endif /* _SPARC_CPUVAR_H */ 289