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Searched defs:BaseReg (Results 1 – 25 of 77) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/
HDARCOptAddrMode.cpp297 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
353 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses()
459 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
HDARCRegisterInfo.cpp46 unsigned BaseReg = FrameReg; in replaceFrameIndex() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86FixupLEAs.cpp458 Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg(); in checkRegUsage() local
507 Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg(); in optLEAALU() local
566 Register BaseReg = Base.getReg(); in optTwoAddrLEA() local
759 Register BaseReg = Base.getReg(); in processInstrForSlow3OpLEA() local
HDX86AsmPrinter.cpp376 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference() local
472 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference() local
HDX86InsertPrefetch.cpp85 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDThumb2SizeReduction.cpp497 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
527 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
535 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
548 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
HDThumbRegisterInfo.cpp126 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg()
254 Register BaseReg, int NumBytes, in emitThumbRegPlusImmediate()
521 void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
HDARMBaseRegisterInfo.cpp681 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in materializeFrameBaseRegister() local
693 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
722 Register BaseReg, in isFrameOffsetLegal()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
HDARMMCTargetDesc.h49 auto BaseReg = MI.getOperand(0).getReg(); in isLDMBaseRegInList() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64FalkorHWPFFix.cpp214 Register BaseReg; member
643 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
HDAArch64StorePairSuppress.cpp168 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
HDAArch64RegisterInfo.cpp806 Register BaseReg, in isFrameOffsetLegal()
828 Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass); in materializeFrameBaseRegister() local
840 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
HDAArch64LoadStoreOptimizer.cpp1299 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1694 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
2055 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn()
2106 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnForward() local
2184 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnBackward() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDLocalStackSlotAllocation.cpp291 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg()
364 Register BaseReg; in insertFrameReferenceRegisters() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVRegisterInfo.cpp649 Register BaseReg, in isFrameOffsetLegal()
676 Register BaseReg = MFI.createVirtualRegister(&RISCV::GPRRegClass); in materializeFrameBaseRegister() local
685 void RISCVRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDR600ISelDAGToDAG.cpp90 SDValue &BaseReg, in SelectGlobalValueVariableOffset()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
HDLoadStoreOpt.cpp87 Register BaseReg; in getPointerInfo() local
204 Register BaseReg; in instMayAlias() local
744 Register BaseReg; in mergeTruncStore() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonGenMemAbsolute.cpp143 unsigned BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
HDMipsNaClELFStreamer.cpp130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
HDX86IntelInstPrinter.cpp383 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference() local
HDX86ATTInstPrinter.cpp426 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference() local
HDX86MCTargetDesc.cpp665 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in evaluateMemoryOperandAddress() local
691 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in getMemoryOperandRelocationOffset() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
HDLanaiMemAluCombiner.cpp373 BaseReg = MBBIter->getOperand(1).getReg(); in combineMemAluInBasicBlock() local
/freebsd-13-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
HDStore.cpp296 const MemRegion *BaseReg = MRMgr.getCXXBaseObjectRegion( in evalDerivedToBase() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDPPCRegisterInfo.cpp1915 Register BaseReg = MRI.createVirtualRegister(RC); in materializeFrameBaseRegister() local
1924 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
1949 Register BaseReg, in isFrameOffsetLegal()

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