1 /*-
2 * Data structures and definitions for CAM Control Blocks (CCBs).
3 *
4 * SPDX-License-Identifier: BSD-2-Clause
5 *
6 * Copyright (c) 1997, 1998 Justin T. Gibbs.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification, immediately at the beginning of the file.
15 * 2. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #ifndef _CAM_CAM_CCB_H
32 #define _CAM_CAM_CCB_H 1
33
34 #include <sys/queue.h>
35 #include <sys/cdefs.h>
36 #include <sys/time.h>
37 #include <sys/limits.h>
38 #ifndef _KERNEL
39 #include <sys/callout.h>
40 #endif
41 #include <cam/cam_debug.h>
42 #include <cam/scsi/scsi_all.h>
43 #include <cam/ata/ata_all.h>
44 #include <cam/nvme/nvme_all.h>
45 #include <cam/mmc/mmc_all.h>
46
47 /* General allocation length definitions for CCB structures */
48 #define IOCDBLEN CAM_MAX_CDBLEN /* Space for CDB bytes/pointer */
49 #define VUHBALEN 14 /* Vendor Unique HBA length */
50 #define SIM_IDLEN 16 /* ASCII string len for SIM ID */
51 #define HBA_IDLEN 16 /* ASCII string len for HBA ID */
52 #define DEV_IDLEN 16 /* ASCII string len for device names */
53 #define CCB_PERIPH_PRIV_SIZE 2 /* size of peripheral private area */
54 #define CCB_SIM_PRIV_SIZE 2 /* size of sim private area */
55
56 /* Struct definitions for CAM control blocks */
57
58 /* Common CCB header */
59 /* CAM CCB flags */
60 typedef enum {
61 CAM_CDB_POINTER = 0x00000001,/* The CDB field is a pointer */
62 CAM_unused1 = 0x00000002,
63 CAM_unused2 = 0x00000004,
64 CAM_NEGOTIATE = 0x00000008,/*
65 * Perform transport negotiation
66 * with this command.
67 */
68 CAM_DATA_ISPHYS = 0x00000010,/* Data type with physical addrs */
69 CAM_DIS_AUTOSENSE = 0x00000020,/* Disable autosense feature */
70 CAM_DIR_BOTH = 0x00000000,/* Data direction (00:IN/OUT) */
71 CAM_DIR_IN = 0x00000040,/* Data direction (01:DATA IN) */
72 CAM_DIR_OUT = 0x00000080,/* Data direction (10:DATA OUT) */
73 CAM_DIR_NONE = 0x000000C0,/* Data direction (11:no data) */
74 CAM_DIR_MASK = 0x000000C0,/* Data direction Mask */
75 CAM_DATA_VADDR = 0x00000000,/* Data type (000:Virtual) */
76 CAM_DATA_PADDR = 0x00000010,/* Data type (001:Physical) */
77 CAM_DATA_SG = 0x00040000,/* Data type (010:sglist) */
78 CAM_DATA_SG_PADDR = 0x00040010,/* Data type (011:sglist phys) */
79 CAM_DATA_BIO = 0x00200000,/* Data type (100:bio) */
80 CAM_DATA_MASK = 0x00240010,/* Data type mask */
81 CAM_unused3 = 0x00000100,
82 CAM_unused4 = 0x00000200,
83 CAM_DEV_QFRZDIS = 0x00000400,/* Disable DEV Q freezing */
84 CAM_DEV_QFREEZE = 0x00000800,/* Freeze DEV Q on execution */
85 CAM_HIGH_POWER = 0x00001000,/* Command takes a lot of power */
86 CAM_SENSE_PTR = 0x00002000,/* Sense data is a pointer */
87 CAM_SENSE_PHYS = 0x00004000,/* Sense pointer is physical addr*/
88 CAM_TAG_ACTION_VALID = 0x00008000,/* Use the tag action in this ccb*/
89 CAM_PASS_ERR_RECOVER = 0x00010000,/* Pass driver does err. recovery*/
90 CAM_DIS_DISCONNECT = 0x00020000,/* Disable disconnect */
91 CAM_unused5 = 0x00080000,
92 CAM_unused6 = 0x00100000,
93 CAM_CDB_PHYS = 0x00400000,/* CDB poiner is physical */
94 CAM_unused7 = 0x00800000,
95
96 /* Phase cognizant mode flags */
97 CAM_unused8 = 0x01000000,
98 CAM_unused9 = 0x02000000,
99 CAM_unused10 = 0x04000000,
100 CAM_unused11 = 0x08000000,
101 CAM_unused12 = 0x10000000,
102 CAM_unused13 = 0x20000000,
103 CAM_unused14 = 0x40000000,
104
105 /* Host target Mode flags */
106 CAM_SEND_SENSE = 0x08000000,/* Send sense data with status */
107 CAM_unused15 = 0x10000000,
108 CAM_unused16 = 0x20000000,
109 CAM_SEND_STATUS = 0x40000000,/* Send status after data phase */
110
111 CAM_UNLOCKED = 0x80000000 /* Call callback without lock. */
112 } ccb_flags;
113
114 typedef enum {
115 CAM_USER_DATA_ADDR = 0x00000002,/* Userspace data pointers */
116 CAM_SG_FORMAT_IOVEC = 0x00000004,/* iovec instead of busdma S/G*/
117 CAM_UNMAPPED_BUF = 0x00000008 /* use unmapped I/O */
118 } ccb_xflags;
119
120 /* XPT Opcodes for xpt_action */
121 typedef enum {
122 /* Function code flags are bits greater than 0xff */
123 XPT_FC_QUEUED = 0x100,
124 /* Non-immediate function code */
125 XPT_FC_USER_CCB = 0x200,
126 XPT_FC_XPT_ONLY = 0x400,
127 /* Only for the transport layer device */
128 XPT_FC_DEV_QUEUED = 0x800 | XPT_FC_QUEUED,
129 /* Passes through the device queues */
130 /* Common function commands: 0x00->0x0F */
131 XPT_NOOP = 0x00,
132 /* Execute Nothing */
133 XPT_SCSI_IO = 0x01 | XPT_FC_DEV_QUEUED,
134 /* Execute the requested I/O operation */
135 XPT_GDEV_TYPE = 0x02,
136 /* Get type information for specified device */
137 XPT_GDEVLIST = 0x03,
138 /* Get a list of peripheral devices */
139 XPT_PATH_INQ = 0x04,
140 /* Path routing inquiry */
141 XPT_REL_SIMQ = 0x05,
142 /* Release a frozen device queue */
143 XPT_SASYNC_CB = 0x06,
144 /* Set Asynchronous Callback Parameters */
145 XPT_SDEV_TYPE = 0x07,
146 /* Set device type information */
147 XPT_SCAN_BUS = 0x08 | XPT_FC_QUEUED | XPT_FC_USER_CCB
148 | XPT_FC_XPT_ONLY,
149 /* (Re)Scan the SCSI Bus */
150 XPT_DEV_MATCH = 0x09 | XPT_FC_XPT_ONLY,
151 /* Get EDT entries matching the given pattern */
152 XPT_DEBUG = 0x0a,
153 /* Turn on debugging for a bus, target or lun */
154 XPT_PATH_STATS = 0x0b,
155 /* Path statistics (error counts, etc.) */
156 XPT_GDEV_STATS = 0x0c,
157 /* Device statistics (error counts, etc.) */
158 XPT_DEV_ADVINFO = 0x0e,
159 /* Get/Set Device advanced information */
160 XPT_ASYNC = 0x0f | XPT_FC_QUEUED | XPT_FC_USER_CCB
161 | XPT_FC_XPT_ONLY,
162 /* Asynchronous event */
163 /* SCSI Control Functions: 0x10->0x1F */
164 XPT_ABORT = 0x10,
165 /* Abort the specified CCB */
166 XPT_RESET_BUS = 0x11 | XPT_FC_XPT_ONLY,
167 /* Reset the specified SCSI bus */
168 XPT_RESET_DEV = 0x12 | XPT_FC_DEV_QUEUED,
169 /* Bus Device Reset the specified SCSI device */
170 XPT_TERM_IO = 0x13,
171 /* Terminate the I/O process */
172 XPT_SCAN_LUN = 0x14 | XPT_FC_QUEUED | XPT_FC_USER_CCB
173 | XPT_FC_XPT_ONLY,
174 /* Scan Logical Unit */
175 XPT_GET_TRAN_SETTINGS = 0x15,
176 /*
177 * Get default/user transfer settings
178 * for the target
179 */
180 XPT_SET_TRAN_SETTINGS = 0x16,
181 /*
182 * Set transfer rate/width
183 * negotiation settings
184 */
185 XPT_CALC_GEOMETRY = 0x17,
186 /*
187 * Calculate the geometry parameters for
188 * a device give the sector size and
189 * volume size.
190 */
191 XPT_ATA_IO = 0x18 | XPT_FC_DEV_QUEUED,
192 /* Execute the requested ATA I/O operation */
193
194 XPT_GET_SIM_KNOB_OLD = 0x18, /* Compat only */
195
196 XPT_SET_SIM_KNOB = 0x19,
197 /*
198 * Set SIM specific knob values.
199 */
200
201 XPT_GET_SIM_KNOB = 0x1a,
202 /*
203 * Get SIM specific knob values.
204 */
205
206 XPT_SMP_IO = 0x1b | XPT_FC_DEV_QUEUED,
207 /* Serial Management Protocol */
208
209 XPT_NVME_IO = 0x1c | XPT_FC_DEV_QUEUED,
210 /* Execute the requested NVMe I/O operation */
211
212 XPT_MMC_IO = 0x1d | XPT_FC_DEV_QUEUED,
213 /* Placeholder for MMC / SD / SDIO I/O stuff */
214
215 XPT_SCAN_TGT = 0x1e | XPT_FC_QUEUED | XPT_FC_USER_CCB
216 | XPT_FC_XPT_ONLY,
217 /* Scan Target */
218
219 XPT_NVME_ADMIN = 0x1f | XPT_FC_DEV_QUEUED,
220 /* Execute the requested NVMe Admin operation */
221
222 /* HBA engine commands 0x20->0x2F */
223 XPT_ENG_INQ = 0x20 | XPT_FC_XPT_ONLY,
224 /* HBA engine feature inquiry */
225 XPT_ENG_EXEC = 0x21 | XPT_FC_DEV_QUEUED,
226 /* HBA execute engine request */
227
228 /* Target mode commands: 0x30->0x3F */
229 XPT_EN_LUN = 0x30,
230 /* Enable LUN as a target */
231 XPT_TARGET_IO = 0x31 | XPT_FC_DEV_QUEUED,
232 /* Execute target I/O request */
233 XPT_ACCEPT_TARGET_IO = 0x32 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
234 /* Accept Host Target Mode CDB */
235 XPT_CONT_TARGET_IO = 0x33 | XPT_FC_DEV_QUEUED,
236 /* Continue Host Target I/O Connection */
237 XPT_IMMED_NOTIFY = 0x34 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
238 /* Notify Host Target driver of event (obsolete) */
239 XPT_NOTIFY_ACK = 0x35,
240 /* Acknowledgement of event (obsolete) */
241 XPT_IMMEDIATE_NOTIFY = 0x36 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
242 /* Notify Host Target driver of event */
243 XPT_NOTIFY_ACKNOWLEDGE = 0x37 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
244 /* Acknowledgement of event */
245 XPT_REPROBE_LUN = 0x38 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
246 /* Query device capacity and notify GEOM */
247
248 XPT_MMC_SET_TRAN_SETTINGS = 0x40 | XPT_FC_DEV_QUEUED,
249 XPT_MMC_GET_TRAN_SETTINGS = 0x41 | XPT_FC_DEV_QUEUED,
250
251 /* Vendor Unique codes: 0x80->0x8F */
252 XPT_VUNIQUE = 0x80
253 } xpt_opcode;
254
255 #define XPT_FC_GROUP_MASK 0xF0
256 #define XPT_FC_GROUP(op) ((op) & XPT_FC_GROUP_MASK)
257 #define XPT_FC_GROUP_COMMON 0x00
258 #define XPT_FC_GROUP_SCSI_CONTROL 0x10
259 #define XPT_FC_GROUP_HBA_ENGINE 0x20
260 #define XPT_FC_GROUP_TMODE 0x30
261 #define XPT_FC_GROUP_VENDOR_UNIQUE 0x80
262
263 #define XPT_FC_IS_DEV_QUEUED(ccb) \
264 (((ccb)->ccb_h.func_code & XPT_FC_DEV_QUEUED) == XPT_FC_DEV_QUEUED)
265 #define XPT_FC_IS_QUEUED(ccb) \
266 (((ccb)->ccb_h.func_code & XPT_FC_QUEUED) != 0)
267
268 typedef enum {
269 PROTO_UNKNOWN,
270 PROTO_UNSPECIFIED,
271 PROTO_SCSI, /* Small Computer System Interface */
272 PROTO_ATA, /* AT Attachment */
273 PROTO_ATAPI, /* AT Attachment Packetized Interface */
274 PROTO_SATAPM, /* SATA Port Multiplier */
275 PROTO_SEMB, /* SATA Enclosure Management Bridge */
276 PROTO_NVME, /* NVME */
277 PROTO_MMCSD, /* MMC, SD, SDIO */
278 } cam_proto;
279
280 typedef enum {
281 XPORT_UNKNOWN,
282 XPORT_UNSPECIFIED,
283 XPORT_SPI, /* SCSI Parallel Interface */
284 XPORT_FC, /* Fiber Channel */
285 XPORT_SSA, /* Serial Storage Architecture */
286 XPORT_USB, /* Universal Serial Bus */
287 XPORT_PPB, /* Parallel Port Bus */
288 XPORT_ATA, /* AT Attachment */
289 XPORT_SAS, /* Serial Attached SCSI */
290 XPORT_SATA, /* Serial AT Attachment */
291 XPORT_ISCSI, /* iSCSI */
292 XPORT_SRP, /* SCSI RDMA Protocol */
293 XPORT_NVME, /* NVMe over PCIe */
294 XPORT_MMCSD, /* MMC, SD, SDIO card */
295 } cam_xport;
296
297 #define XPORT_IS_NVME(t) ((t) == XPORT_NVME)
298 #define XPORT_IS_ATA(t) ((t) == XPORT_ATA || (t) == XPORT_SATA)
299 #define XPORT_IS_SCSI(t) ((t) != XPORT_UNKNOWN && \
300 (t) != XPORT_UNSPECIFIED && \
301 !XPORT_IS_ATA(t) && !XPORT_IS_NVME(t))
302 #define XPORT_DEVSTAT_TYPE(t) (XPORT_IS_ATA(t) ? DEVSTAT_TYPE_IF_IDE : \
303 XPORT_IS_SCSI(t) ? DEVSTAT_TYPE_IF_SCSI : \
304 DEVSTAT_TYPE_IF_OTHER)
305
306 #define PROTO_VERSION_UNKNOWN (UINT_MAX - 1)
307 #define PROTO_VERSION_UNSPECIFIED UINT_MAX
308 #define XPORT_VERSION_UNKNOWN (UINT_MAX - 1)
309 #define XPORT_VERSION_UNSPECIFIED UINT_MAX
310
311 typedef union {
312 LIST_ENTRY(ccb_hdr) le;
313 SLIST_ENTRY(ccb_hdr) sle;
314 TAILQ_ENTRY(ccb_hdr) tqe;
315 STAILQ_ENTRY(ccb_hdr) stqe;
316 } camq_entry;
317
318 typedef union {
319 void *ptr;
320 u_long field;
321 u_int8_t bytes[sizeof(uintptr_t)];
322 } ccb_priv_entry;
323
324 typedef union {
325 ccb_priv_entry entries[CCB_PERIPH_PRIV_SIZE];
326 u_int8_t bytes[CCB_PERIPH_PRIV_SIZE * sizeof(ccb_priv_entry)];
327 } ccb_ppriv_area;
328
329 typedef union {
330 ccb_priv_entry entries[CCB_SIM_PRIV_SIZE];
331 u_int8_t bytes[CCB_SIM_PRIV_SIZE * sizeof(ccb_priv_entry)];
332 } ccb_spriv_area;
333
334 typedef struct {
335 struct timeval *etime;
336 uintptr_t sim_data;
337 uintptr_t periph_data;
338 } ccb_qos_area;
339
340 struct ccb_hdr {
341 cam_pinfo pinfo; /* Info for priority scheduling */
342 camq_entry xpt_links; /* For chaining in the XPT layer */
343 camq_entry sim_links; /* For chaining in the SIM layer */
344 camq_entry periph_links; /* For chaining in the type driver */
345 u_int32_t retry_count;
346 void (*cbfcnp)(struct cam_periph *, union ccb *);
347 /* Callback on completion function */
348 xpt_opcode func_code; /* XPT function code */
349 u_int32_t status; /* Status returned by CAM subsystem */
350 struct cam_path *path; /* Compiled path for this ccb */
351 path_id_t path_id; /* Path ID for the request */
352 target_id_t target_id; /* Target device ID */
353 lun_id_t target_lun; /* Target LUN number */
354 u_int32_t flags; /* ccb_flags */
355 u_int32_t xflags; /* Extended flags */
356 ccb_ppriv_area periph_priv;
357 ccb_spriv_area sim_priv;
358 ccb_qos_area qos;
359 u_int32_t timeout; /* Hard timeout value in mseconds */
360 struct timeval softtimeout; /* Soft timeout value in sec + usec */
361 };
362
363 /* Get Device Information CCB */
364 struct ccb_getdev {
365 struct ccb_hdr ccb_h;
366 cam_proto protocol;
367 struct scsi_inquiry_data inq_data;
368 struct ata_params ident_data;
369 u_int8_t serial_num[252];
370 u_int8_t inq_flags;
371 u_int8_t serial_num_len;
372 void *padding[2];
373 };
374
375 /* Device Statistics CCB */
376 struct ccb_getdevstats {
377 struct ccb_hdr ccb_h;
378 int dev_openings; /* Space left for more work on device*/
379 int dev_active; /* Transactions running on the device */
380 int allocated; /* CCBs allocated for the device */
381 int queued; /* CCBs queued to be sent to the device */
382 int held; /*
383 * CCBs held by peripheral drivers
384 * for this device
385 */
386 int maxtags; /*
387 * Boundary conditions for number of
388 * tagged operations
389 */
390 int mintags;
391 struct timeval last_reset; /* Time of last bus reset/loop init */
392 };
393
394 typedef enum {
395 CAM_GDEVLIST_LAST_DEVICE,
396 CAM_GDEVLIST_LIST_CHANGED,
397 CAM_GDEVLIST_MORE_DEVS,
398 CAM_GDEVLIST_ERROR
399 } ccb_getdevlist_status_e;
400
401 struct ccb_getdevlist {
402 struct ccb_hdr ccb_h;
403 char periph_name[DEV_IDLEN];
404 u_int32_t unit_number;
405 unsigned int generation;
406 u_int32_t index;
407 ccb_getdevlist_status_e status;
408 };
409
410 typedef enum {
411 PERIPH_MATCH_ANY = 0x000,
412 PERIPH_MATCH_PATH = 0x001,
413 PERIPH_MATCH_TARGET = 0x002,
414 PERIPH_MATCH_LUN = 0x004,
415 PERIPH_MATCH_NAME = 0x008,
416 PERIPH_MATCH_UNIT = 0x010,
417 } periph_pattern_flags;
418
419 struct periph_match_pattern {
420 char periph_name[DEV_IDLEN];
421 u_int32_t unit_number;
422 path_id_t path_id;
423 target_id_t target_id;
424 lun_id_t target_lun;
425 periph_pattern_flags flags;
426 };
427
428 typedef enum {
429 DEV_MATCH_ANY = 0x000,
430 DEV_MATCH_PATH = 0x001,
431 DEV_MATCH_TARGET = 0x002,
432 DEV_MATCH_LUN = 0x004,
433 DEV_MATCH_INQUIRY = 0x008,
434 DEV_MATCH_DEVID = 0x010,
435 } dev_pattern_flags;
436
437 struct device_id_match_pattern {
438 uint8_t id_len;
439 uint8_t id[256];
440 };
441
442 struct device_match_pattern {
443 path_id_t path_id;
444 target_id_t target_id;
445 lun_id_t target_lun;
446 dev_pattern_flags flags;
447 union {
448 struct scsi_static_inquiry_pattern inq_pat;
449 struct device_id_match_pattern devid_pat;
450 } data;
451 };
452
453 typedef enum {
454 BUS_MATCH_ANY = 0x000,
455 BUS_MATCH_PATH = 0x001,
456 BUS_MATCH_NAME = 0x002,
457 BUS_MATCH_UNIT = 0x004,
458 BUS_MATCH_BUS_ID = 0x008,
459 } bus_pattern_flags;
460
461 struct bus_match_pattern {
462 path_id_t path_id;
463 char dev_name[DEV_IDLEN];
464 u_int32_t unit_number;
465 u_int32_t bus_id;
466 bus_pattern_flags flags;
467 };
468
469 union match_pattern {
470 struct periph_match_pattern periph_pattern;
471 struct device_match_pattern device_pattern;
472 struct bus_match_pattern bus_pattern;
473 };
474
475 typedef enum {
476 DEV_MATCH_PERIPH,
477 DEV_MATCH_DEVICE,
478 DEV_MATCH_BUS
479 } dev_match_type;
480
481 struct dev_match_pattern {
482 dev_match_type type;
483 union match_pattern pattern;
484 };
485
486 struct periph_match_result {
487 char periph_name[DEV_IDLEN];
488 u_int32_t unit_number;
489 path_id_t path_id;
490 target_id_t target_id;
491 lun_id_t target_lun;
492 };
493
494 typedef enum {
495 DEV_RESULT_NOFLAG = 0x00,
496 DEV_RESULT_UNCONFIGURED = 0x01
497 } dev_result_flags;
498
499 struct device_match_result {
500 path_id_t path_id;
501 target_id_t target_id;
502 lun_id_t target_lun;
503 cam_proto protocol;
504 struct scsi_inquiry_data inq_data;
505 struct ata_params ident_data;
506 dev_result_flags flags;
507 };
508
509 struct bus_match_result {
510 path_id_t path_id;
511 char dev_name[DEV_IDLEN];
512 u_int32_t unit_number;
513 u_int32_t bus_id;
514 };
515
516 union match_result {
517 struct periph_match_result periph_result;
518 struct device_match_result device_result;
519 struct bus_match_result bus_result;
520 };
521
522 struct dev_match_result {
523 dev_match_type type;
524 union match_result result;
525 };
526
527 typedef enum {
528 CAM_DEV_MATCH_LAST,
529 CAM_DEV_MATCH_MORE,
530 CAM_DEV_MATCH_LIST_CHANGED,
531 CAM_DEV_MATCH_SIZE_ERROR,
532 CAM_DEV_MATCH_ERROR
533 } ccb_dev_match_status;
534
535 typedef enum {
536 CAM_DEV_POS_NONE = 0x000,
537 CAM_DEV_POS_BUS = 0x001,
538 CAM_DEV_POS_TARGET = 0x002,
539 CAM_DEV_POS_DEVICE = 0x004,
540 CAM_DEV_POS_PERIPH = 0x008,
541 CAM_DEV_POS_PDPTR = 0x010,
542 CAM_DEV_POS_TYPEMASK = 0xf00,
543 CAM_DEV_POS_EDT = 0x100,
544 CAM_DEV_POS_PDRV = 0x200
545 } dev_pos_type;
546
547 struct ccb_dm_cookie {
548 void *bus;
549 void *target;
550 void *device;
551 void *periph;
552 void *pdrv;
553 };
554
555 struct ccb_dev_position {
556 u_int generations[4];
557 #define CAM_BUS_GENERATION 0x00
558 #define CAM_TARGET_GENERATION 0x01
559 #define CAM_DEV_GENERATION 0x02
560 #define CAM_PERIPH_GENERATION 0x03
561 dev_pos_type position_type;
562 struct ccb_dm_cookie cookie;
563 };
564
565 struct ccb_dev_match {
566 struct ccb_hdr ccb_h;
567 ccb_dev_match_status status;
568 u_int32_t num_patterns;
569 u_int32_t pattern_buf_len;
570 struct dev_match_pattern *patterns;
571 u_int32_t num_matches;
572 u_int32_t match_buf_len;
573 struct dev_match_result *matches;
574 struct ccb_dev_position pos;
575 };
576
577 /*
578 * Definitions for the path inquiry CCB fields.
579 */
580 #define CAM_VERSION 0x1a /* Hex value for current version */
581
582 typedef enum {
583 PI_MDP_ABLE = 0x80, /* Supports MDP message */
584 PI_WIDE_32 = 0x40, /* Supports 32 bit wide SCSI */
585 PI_WIDE_16 = 0x20, /* Supports 16 bit wide SCSI */
586 PI_SDTR_ABLE = 0x10, /* Supports SDTR message */
587 PI_LINKED_CDB = 0x08, /* Supports linked CDBs */
588 PI_SATAPM = 0x04, /* Supports SATA PM */
589 PI_TAG_ABLE = 0x02, /* Supports tag queue messages */
590 PI_SOFT_RST = 0x01 /* Supports soft reset alternative */
591 } pi_inqflag;
592
593 typedef enum {
594 PIT_PROCESSOR = 0x80, /* Target mode processor mode */
595 PIT_PHASE = 0x40, /* Target mode phase cog. mode */
596 PIT_DISCONNECT = 0x20, /* Disconnects supported in target mode */
597 PIT_TERM_IO = 0x10, /* Terminate I/O message supported in TM */
598 PIT_GRP_6 = 0x08, /* Group 6 commands supported */
599 PIT_GRP_7 = 0x04 /* Group 7 commands supported */
600 } pi_tmflag;
601
602 typedef enum {
603 PIM_ATA_EXT = 0x200,/* ATA requests can understand ata_ext requests */
604 PIM_EXTLUNS = 0x100,/* 64bit extended LUNs supported */
605 PIM_SCANHILO = 0x80, /* Bus scans from high ID to low ID */
606 PIM_NOREMOVE = 0x40, /* Removeable devices not included in scan */
607 PIM_NOINITIATOR = 0x20, /* Initiator role not supported. */
608 PIM_NOBUSRESET = 0x10, /* User has disabled initial BUS RESET */
609 PIM_NO_6_BYTE = 0x08, /* Do not send 6-byte commands */
610 PIM_SEQSCAN = 0x04, /* Do bus scans sequentially, not in parallel */
611 PIM_UNMAPPED = 0x02,
612 PIM_NOSCAN = 0x01 /* SIM does its own scanning */
613 } pi_miscflag;
614
615 /* Path Inquiry CCB */
616 struct ccb_pathinq_settings_spi {
617 u_int8_t ppr_options;
618 };
619
620 struct ccb_pathinq_settings_fc {
621 u_int64_t wwnn; /* world wide node name */
622 u_int64_t wwpn; /* world wide port name */
623 u_int32_t port; /* 24 bit port id, if known */
624 u_int32_t bitrate; /* Mbps */
625 };
626
627 struct ccb_pathinq_settings_sas {
628 u_int32_t bitrate; /* Mbps */
629 };
630
631 #define NVME_DEV_NAME_LEN 52
632 struct ccb_pathinq_settings_nvme {
633 uint32_t nsid; /* Namespace ID for this path */
634 uint32_t domain;
635 uint8_t bus;
636 uint8_t slot;
637 uint8_t function;
638 uint8_t extra;
639 char dev_name[NVME_DEV_NAME_LEN]; /* nvme controller dev name for this device */
640 };
641 _Static_assert(sizeof(struct ccb_pathinq_settings_nvme) == 64,
642 "ccb_pathinq_settings_nvme too big");
643
644 #define PATHINQ_SETTINGS_SIZE 128
645
646 struct ccb_pathinq {
647 struct ccb_hdr ccb_h;
648 u_int8_t version_num; /* Version number for the SIM/HBA */
649 u_int8_t hba_inquiry; /* Mimic of INQ byte 7 for the HBA */
650 u_int16_t target_sprt; /* Flags for target mode support */
651 u_int32_t hba_misc; /* Misc HBA features */
652 u_int16_t hba_eng_cnt; /* HBA engine count */
653 /* Vendor Unique capabilities */
654 u_int8_t vuhba_flags[VUHBALEN];
655 u_int32_t max_target; /* Maximum supported Target */
656 u_int32_t max_lun; /* Maximum supported Lun */
657 u_int32_t async_flags; /* Installed Async handlers */
658 path_id_t hpath_id; /* Highest Path ID in the subsystem */
659 target_id_t initiator_id; /* ID of the HBA on the SCSI bus */
660 char sim_vid[SIM_IDLEN]; /* Vendor ID of the SIM */
661 char hba_vid[HBA_IDLEN]; /* Vendor ID of the HBA */
662 char dev_name[DEV_IDLEN];/* Device name for SIM */
663 u_int32_t unit_number; /* Unit number for SIM */
664 u_int32_t bus_id; /* Bus ID for SIM */
665 u_int32_t base_transfer_speed;/* Base bus speed in KB/sec */
666 cam_proto protocol;
667 u_int protocol_version;
668 cam_xport transport;
669 u_int transport_version;
670 union {
671 struct ccb_pathinq_settings_spi spi;
672 struct ccb_pathinq_settings_fc fc;
673 struct ccb_pathinq_settings_sas sas;
674 struct ccb_pathinq_settings_nvme nvme;
675 char ccb_pathinq_settings_opaque[PATHINQ_SETTINGS_SIZE];
676 } xport_specific;
677 u_int maxio; /* Max supported I/O size, in bytes. */
678 u_int16_t hba_vendor; /* HBA vendor ID */
679 u_int16_t hba_device; /* HBA device ID */
680 u_int16_t hba_subvendor; /* HBA subvendor ID */
681 u_int16_t hba_subdevice; /* HBA subdevice ID */
682 };
683
684 /* Path Statistics CCB */
685 struct ccb_pathstats {
686 struct ccb_hdr ccb_h;
687 struct timeval last_reset; /* Time of last bus reset/loop init */
688 };
689
690 typedef enum {
691 SMP_FLAG_NONE = 0x00,
692 SMP_FLAG_REQ_SG = 0x01,
693 SMP_FLAG_RSP_SG = 0x02
694 } ccb_smp_pass_flags;
695
696 /*
697 * Serial Management Protocol CCB
698 * XXX Currently the semantics for this CCB are that it is executed either
699 * by the addressed device, or that device's parent (i.e. an expander for
700 * any device on an expander) if the addressed device doesn't support SMP.
701 * Later, once we have the ability to probe SMP-only devices and put them
702 * in CAM's topology, the CCB will only be executed by the addressed device
703 * if possible.
704 */
705 struct ccb_smpio {
706 struct ccb_hdr ccb_h;
707 uint8_t *smp_request;
708 int smp_request_len;
709 uint16_t smp_request_sglist_cnt;
710 uint8_t *smp_response;
711 int smp_response_len;
712 uint16_t smp_response_sglist_cnt;
713 ccb_smp_pass_flags flags;
714 };
715
716 typedef union {
717 u_int8_t *sense_ptr; /*
718 * Pointer to storage
719 * for sense information
720 */
721 /* Storage Area for sense information */
722 struct scsi_sense_data sense_buf;
723 } sense_t;
724
725 typedef union {
726 u_int8_t *cdb_ptr; /* Pointer to the CDB bytes to send */
727 /* Area for the CDB send */
728 u_int8_t cdb_bytes[IOCDBLEN];
729 } cdb_t;
730
731 /*
732 * SCSI I/O Request CCB used for the XPT_SCSI_IO and XPT_CONT_TARGET_IO
733 * function codes.
734 */
735 struct ccb_scsiio {
736 struct ccb_hdr ccb_h;
737 union ccb *next_ccb; /* Ptr for next CCB for action */
738 u_int8_t *req_map; /* Ptr to mapping info */
739 u_int8_t *data_ptr; /* Ptr to the data buf/SG list */
740 u_int32_t dxfer_len; /* Data transfer length */
741 /* Autosense storage */
742 struct scsi_sense_data sense_data;
743 u_int8_t sense_len; /* Number of bytes to autosense */
744 u_int8_t cdb_len; /* Number of bytes for the CDB */
745 u_int16_t sglist_cnt; /* Number of SG list entries */
746 u_int8_t scsi_status; /* Returned SCSI status */
747 u_int8_t sense_resid; /* Autosense resid length: 2's comp */
748 u_int32_t resid; /* Transfer residual length: 2's comp */
749 cdb_t cdb_io; /* Union for CDB bytes/pointer */
750 u_int8_t *msg_ptr; /* Pointer to the message buffer */
751 u_int16_t msg_len; /* Number of bytes for the Message */
752 u_int8_t tag_action; /* What to do for tag queueing */
753 /*
754 * The tag action should be either the define below (to send a
755 * non-tagged transaction) or one of the defined scsi tag messages
756 * from scsi_message.h.
757 */
758 #define CAM_TAG_ACTION_NONE 0x00
759 uint8_t priority; /* Command priority for SIMPLE tag */
760 u_int tag_id; /* tag id from initator (target mode) */
761 u_int init_id; /* initiator id of who selected */
762 #if defined(BUF_TRACKING) || defined(FULL_BUF_TRACKING)
763 struct bio *bio; /* Associated bio */
764 #endif
765 };
766
767 static __inline uint8_t *
scsiio_cdb_ptr(struct ccb_scsiio * ccb)768 scsiio_cdb_ptr(struct ccb_scsiio *ccb)
769 {
770 return ((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
771 ccb->cdb_io.cdb_ptr : ccb->cdb_io.cdb_bytes);
772 }
773
774 /*
775 * ATA I/O Request CCB used for the XPT_ATA_IO function code.
776 */
777 struct ccb_ataio {
778 struct ccb_hdr ccb_h;
779 union ccb *next_ccb; /* Ptr for next CCB for action */
780 struct ata_cmd cmd; /* ATA command register set */
781 struct ata_res res; /* ATA result register set */
782 u_int8_t *data_ptr; /* Ptr to the data buf/SG list */
783 u_int32_t dxfer_len; /* Data transfer length */
784 u_int32_t resid; /* Transfer residual length: 2's comp */
785 u_int8_t ata_flags; /* Flags for the rest of the buffer */
786 #define ATA_FLAG_AUX 0x1
787 #define ATA_FLAG_ICC 0x2
788 uint8_t icc; /* Isochronous Command Completion */
789 uint32_t aux;
790 uint32_t unused;
791 };
792
793 /*
794 * MMC I/O Request CCB used for the XPT_MMC_IO function code.
795 */
796 struct ccb_mmcio {
797 struct ccb_hdr ccb_h;
798 union ccb *next_ccb; /* Ptr for next CCB for action */
799 struct mmc_command cmd;
800 struct mmc_command stop;
801 };
802
803 struct ccb_accept_tio {
804 struct ccb_hdr ccb_h;
805 cdb_t cdb_io; /* Union for CDB bytes/pointer */
806 u_int8_t cdb_len; /* Number of bytes for the CDB */
807 u_int8_t tag_action; /* What to do for tag queueing */
808 u_int8_t sense_len; /* Number of bytes of Sense Data */
809 uint8_t priority; /* Command priority for SIMPLE tag */
810 u_int tag_id; /* tag id from initator (target mode) */
811 u_int init_id; /* initiator id of who selected */
812 struct scsi_sense_data sense_data;
813 };
814
815 static __inline uint8_t *
atio_cdb_ptr(struct ccb_accept_tio * ccb)816 atio_cdb_ptr(struct ccb_accept_tio *ccb)
817 {
818 return ((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
819 ccb->cdb_io.cdb_ptr : ccb->cdb_io.cdb_bytes);
820 }
821
822 /* Release SIM Queue */
823 struct ccb_relsim {
824 struct ccb_hdr ccb_h;
825 u_int32_t release_flags;
826 #define RELSIM_ADJUST_OPENINGS 0x01
827 #define RELSIM_RELEASE_AFTER_TIMEOUT 0x02
828 #define RELSIM_RELEASE_AFTER_CMDCMPLT 0x04
829 #define RELSIM_RELEASE_AFTER_QEMPTY 0x08
830 u_int32_t openings;
831 u_int32_t release_timeout; /* Abstract argument. */
832 u_int32_t qfrozen_cnt;
833 };
834
835 /*
836 * NVMe I/O Request CCB used for the XPT_NVME_IO and XPT_NVME_ADMIN function codes.
837 */
838 struct ccb_nvmeio {
839 struct ccb_hdr ccb_h;
840 union ccb *next_ccb; /* Ptr for next CCB for action */
841 struct nvme_command cmd; /* NVME command, per NVME standard */
842 struct nvme_completion cpl; /* NVME completion, per NVME standard */
843 uint8_t *data_ptr; /* Ptr to the data buf/SG list */
844 uint32_t dxfer_len; /* Data transfer length */
845 uint16_t sglist_cnt; /* Number of SG list entries */
846 uint16_t unused; /* padding for removed uint32_t */
847 };
848
849 /*
850 * Definitions for the asynchronous callback CCB fields.
851 */
852 typedef enum {
853 AC_UNIT_ATTENTION = 0x4000,/* Device reported UNIT ATTENTION */
854 AC_ADVINFO_CHANGED = 0x2000,/* Advance info might have changes */
855 AC_CONTRACT = 0x1000,/* A contractual callback */
856 AC_GETDEV_CHANGED = 0x800,/* Getdev info might have changed */
857 AC_INQ_CHANGED = 0x400,/* Inquiry info might have changed */
858 AC_TRANSFER_NEG = 0x200,/* New transfer settings in effect */
859 AC_LOST_DEVICE = 0x100,/* A device went away */
860 AC_FOUND_DEVICE = 0x080,/* A new device was found */
861 AC_PATH_DEREGISTERED = 0x040,/* A path has de-registered */
862 AC_PATH_REGISTERED = 0x020,/* A new path has been registered */
863 AC_SENT_BDR = 0x010,/* A BDR message was sent to target */
864 AC_SCSI_AEN = 0x008,/* A SCSI AEN has been received */
865 AC_UNSOL_RESEL = 0x002,/* Unsolicited reselection occurred */
866 AC_BUS_RESET = 0x001 /* A SCSI bus reset occurred */
867 } ac_code;
868
869 typedef void ac_callback_t (void *softc, u_int32_t code,
870 struct cam_path *path, void *args);
871
872 /*
873 * Generic Asynchronous callbacks.
874 *
875 * Generic arguments passed bac which are then interpreted between a per-system
876 * contract number.
877 */
878 #define AC_CONTRACT_DATA_MAX (128 - sizeof (u_int64_t))
879 struct ac_contract {
880 u_int64_t contract_number;
881 u_int8_t contract_data[AC_CONTRACT_DATA_MAX];
882 };
883
884 #define AC_CONTRACT_DEV_CHG 1
885 struct ac_device_changed {
886 u_int64_t wwpn;
887 u_int32_t port;
888 target_id_t target;
889 u_int8_t arrived;
890 };
891
892 /* Set Asynchronous Callback CCB */
893 struct ccb_setasync {
894 struct ccb_hdr ccb_h;
895 u_int32_t event_enable; /* Async Event enables */
896 ac_callback_t *callback;
897 void *callback_arg;
898 };
899
900 /* Set Device Type CCB */
901 struct ccb_setdev {
902 struct ccb_hdr ccb_h;
903 u_int8_t dev_type; /* Value for dev type field in EDT */
904 };
905
906 /* SCSI Control Functions */
907
908 /* Abort XPT request CCB */
909 struct ccb_abort {
910 struct ccb_hdr ccb_h;
911 union ccb *abort_ccb; /* Pointer to CCB to abort */
912 };
913
914 /* Reset SCSI Bus CCB */
915 struct ccb_resetbus {
916 struct ccb_hdr ccb_h;
917 };
918
919 /* Reset SCSI Device CCB */
920 struct ccb_resetdev {
921 struct ccb_hdr ccb_h;
922 };
923
924 /* Terminate I/O Process Request CCB */
925 struct ccb_termio {
926 struct ccb_hdr ccb_h;
927 union ccb *termio_ccb; /* Pointer to CCB to terminate */
928 };
929
930 typedef enum {
931 CTS_TYPE_CURRENT_SETTINGS,
932 CTS_TYPE_USER_SETTINGS
933 } cts_type;
934
935 struct ccb_trans_settings_scsi
936 {
937 u_int valid; /* Which fields to honor */
938 #define CTS_SCSI_VALID_TQ 0x01
939 u_int flags;
940 #define CTS_SCSI_FLAGS_TAG_ENB 0x01
941 };
942
943 struct ccb_trans_settings_ata
944 {
945 u_int valid; /* Which fields to honor */
946 #define CTS_ATA_VALID_TQ 0x01
947 u_int flags;
948 #define CTS_ATA_FLAGS_TAG_ENB 0x01
949 };
950
951 struct ccb_trans_settings_spi
952 {
953 u_int valid; /* Which fields to honor */
954 #define CTS_SPI_VALID_SYNC_RATE 0x01
955 #define CTS_SPI_VALID_SYNC_OFFSET 0x02
956 #define CTS_SPI_VALID_BUS_WIDTH 0x04
957 #define CTS_SPI_VALID_DISC 0x08
958 #define CTS_SPI_VALID_PPR_OPTIONS 0x10
959 u_int flags;
960 #define CTS_SPI_FLAGS_DISC_ENB 0x01
961 u_int sync_period;
962 u_int sync_offset;
963 u_int bus_width;
964 u_int ppr_options;
965 };
966
967 struct ccb_trans_settings_fc {
968 u_int valid; /* Which fields to honor */
969 #define CTS_FC_VALID_WWNN 0x8000
970 #define CTS_FC_VALID_WWPN 0x4000
971 #define CTS_FC_VALID_PORT 0x2000
972 #define CTS_FC_VALID_SPEED 0x1000
973 u_int64_t wwnn; /* world wide node name */
974 u_int64_t wwpn; /* world wide port name */
975 u_int32_t port; /* 24 bit port id, if known */
976 u_int32_t bitrate; /* Mbps */
977 };
978
979 struct ccb_trans_settings_sas {
980 u_int valid; /* Which fields to honor */
981 #define CTS_SAS_VALID_SPEED 0x1000
982 u_int32_t bitrate; /* Mbps */
983 };
984
985 struct ccb_trans_settings_pata {
986 u_int valid; /* Which fields to honor */
987 #define CTS_ATA_VALID_MODE 0x01
988 #define CTS_ATA_VALID_BYTECOUNT 0x02
989 #define CTS_ATA_VALID_ATAPI 0x20
990 #define CTS_ATA_VALID_CAPS 0x40
991 int mode; /* Mode */
992 u_int bytecount; /* Length of PIO transaction */
993 u_int atapi; /* Length of ATAPI CDB */
994 u_int caps; /* Device and host SATA caps. */
995 #define CTS_ATA_CAPS_H 0x0000ffff
996 #define CTS_ATA_CAPS_H_DMA48 0x00000001 /* 48-bit DMA */
997 #define CTS_ATA_CAPS_D 0xffff0000
998 };
999
1000 struct ccb_trans_settings_sata {
1001 u_int valid; /* Which fields to honor */
1002 #define CTS_SATA_VALID_MODE 0x01
1003 #define CTS_SATA_VALID_BYTECOUNT 0x02
1004 #define CTS_SATA_VALID_REVISION 0x04
1005 #define CTS_SATA_VALID_PM 0x08
1006 #define CTS_SATA_VALID_TAGS 0x10
1007 #define CTS_SATA_VALID_ATAPI 0x20
1008 #define CTS_SATA_VALID_CAPS 0x40
1009 int mode; /* Legacy PATA mode */
1010 u_int bytecount; /* Length of PIO transaction */
1011 int revision; /* SATA revision */
1012 u_int pm_present; /* PM is present (XPT->SIM) */
1013 u_int tags; /* Number of allowed tags */
1014 u_int atapi; /* Length of ATAPI CDB */
1015 u_int caps; /* Device and host SATA caps. */
1016 #define CTS_SATA_CAPS_H 0x0000ffff
1017 #define CTS_SATA_CAPS_H_PMREQ 0x00000001
1018 #define CTS_SATA_CAPS_H_APST 0x00000002
1019 #define CTS_SATA_CAPS_H_DMAAA 0x00000010 /* Auto-activation */
1020 #define CTS_SATA_CAPS_H_AN 0x00000020 /* Async. notification */
1021 #define CTS_SATA_CAPS_D 0xffff0000
1022 #define CTS_SATA_CAPS_D_PMREQ 0x00010000
1023 #define CTS_SATA_CAPS_D_APST 0x00020000
1024 };
1025
1026 struct ccb_trans_settings_nvme
1027 {
1028 u_int valid; /* Which fields to honor */
1029 #define CTS_NVME_VALID_SPEC 0x01
1030 #define CTS_NVME_VALID_CAPS 0x02
1031 #define CTS_NVME_VALID_LINK 0x04
1032 uint32_t spec; /* NVMe spec implemented -- same as vs register */
1033 uint32_t max_xfer; /* Max transfer size (0 -> unlimited */
1034 uint32_t caps;
1035 uint8_t lanes; /* Number of PCIe lanes */
1036 uint8_t speed; /* PCIe generation for each lane */
1037 uint8_t max_lanes; /* Number of PCIe lanes */
1038 uint8_t max_speed; /* PCIe generation for each lane */
1039 };
1040
1041 #include <cam/mmc/mmc_bus.h>
1042 struct ccb_trans_settings_mmc {
1043 struct mmc_ios ios;
1044 #define MMC_CLK (1 << 1)
1045 #define MMC_VDD (1 << 2)
1046 #define MMC_CS (1 << 3)
1047 #define MMC_BW (1 << 4)
1048 #define MMC_PM (1 << 5)
1049 #define MMC_BT (1 << 6)
1050 #define MMC_BM (1 << 7)
1051 #define MMC_VCCQ (1 << 8)
1052 uint32_t ios_valid;
1053 /* The folowing is used only for GET_TRAN_SETTINGS */
1054 uint32_t host_ocr;
1055 int host_f_min;
1056 int host_f_max;
1057 /* Copied from sys/dev/mmc/bridge.h */
1058 #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can do 4-bit data transfers */
1059 #define MMC_CAP_8_BIT_DATA (1 << 1) /* Can do 8-bit data transfers */
1060 #define MMC_CAP_HSPEED (1 << 2) /* Can do High Speed transfers */
1061 #define MMC_CAP_BOOT_NOACC (1 << 4) /* Cannot access boot partitions */
1062 #define MMC_CAP_WAIT_WHILE_BUSY (1 << 5) /* Host waits for busy responses */
1063 #define MMC_CAP_UHS_SDR12 (1 << 6) /* Can do UHS SDR12 */
1064 #define MMC_CAP_UHS_SDR25 (1 << 7) /* Can do UHS SDR25 */
1065 #define MMC_CAP_UHS_SDR50 (1 << 8) /* Can do UHS SDR50 */
1066 #define MMC_CAP_UHS_SDR104 (1 << 9) /* Can do UHS SDR104 */
1067 #define MMC_CAP_UHS_DDR50 (1 << 10) /* Can do UHS DDR50 */
1068 #define MMC_CAP_MMC_DDR52_120 (1 << 11) /* Can do eMMC DDR52 at 1.2 V */
1069 #define MMC_CAP_MMC_DDR52_180 (1 << 12) /* Can do eMMC DDR52 at 1.8 V */
1070 #define MMC_CAP_MMC_DDR52 (MMC_CAP_MMC_DDR52_120 | MMC_CAP_MMC_DDR52_180)
1071 #define MMC_CAP_MMC_HS200_120 (1 << 13) /* Can do eMMC HS200 at 1.2 V */
1072 #define MMC_CAP_MMC_HS200_180 (1 << 14) /* Can do eMMC HS200 at 1.8 V */
1073 #define MMC_CAP_MMC_HS200 (MMC_CAP_MMC_HS200_120| MMC_CAP_MMC_HS200_180)
1074 #define MMC_CAP_MMC_HS400_120 (1 << 15) /* Can do eMMC HS400 at 1.2 V */
1075 #define MMC_CAP_MMC_HS400_180 (1 << 16) /* Can do eMMC HS400 at 1.8 V */
1076 #define MMC_CAP_MMC_HS400 (MMC_CAP_MMC_HS400_120 | MMC_CAP_MMC_HS400_180)
1077 #define MMC_CAP_MMC_HSX00_120 (MMC_CAP_MMC_HS200_120 | MMC_CAP_MMC_HS400_120)
1078 #define MMC_CAP_MMC_ENH_STROBE (1 << 17) /* Can do eMMC Enhanced Strobe */
1079 #define MMC_CAP_SIGNALING_120 (1 << 18) /* Can do signaling at 1.2 V */
1080 #define MMC_CAP_SIGNALING_180 (1 << 19) /* Can do signaling at 1.8 V */
1081 #define MMC_CAP_SIGNALING_330 (1 << 20) /* Can do signaling at 3.3 V */
1082 #define MMC_CAP_DRIVER_TYPE_A (1 << 21) /* Can do Driver Type A */
1083 #define MMC_CAP_DRIVER_TYPE_C (1 << 22) /* Can do Driver Type C */
1084 #define MMC_CAP_DRIVER_TYPE_D (1 << 23) /* Can do Driver Type D */
1085
1086 uint32_t host_caps;
1087 uint32_t host_max_data;
1088 };
1089
1090 /* Get/Set transfer rate/width/disconnection/tag queueing settings */
1091 struct ccb_trans_settings {
1092 struct ccb_hdr ccb_h;
1093 cts_type type; /* Current or User settings */
1094 cam_proto protocol;
1095 u_int protocol_version;
1096 cam_xport transport;
1097 u_int transport_version;
1098 union {
1099 u_int valid; /* Which fields to honor */
1100 struct ccb_trans_settings_ata ata;
1101 struct ccb_trans_settings_scsi scsi;
1102 struct ccb_trans_settings_nvme nvme;
1103 struct ccb_trans_settings_mmc mmc;
1104 } proto_specific;
1105 union {
1106 u_int valid; /* Which fields to honor */
1107 struct ccb_trans_settings_spi spi;
1108 struct ccb_trans_settings_fc fc;
1109 struct ccb_trans_settings_sas sas;
1110 struct ccb_trans_settings_pata ata;
1111 struct ccb_trans_settings_sata sata;
1112 struct ccb_trans_settings_nvme nvme;
1113 } xport_specific;
1114 };
1115
1116 /*
1117 * Calculate the geometry parameters for a device
1118 * give the block size and volume size in blocks.
1119 */
1120 struct ccb_calc_geometry {
1121 struct ccb_hdr ccb_h;
1122 u_int32_t block_size;
1123 u_int64_t volume_size;
1124 u_int32_t cylinders;
1125 u_int8_t heads;
1126 u_int8_t secs_per_track;
1127 };
1128
1129 /*
1130 * Set or get SIM (and transport) specific knobs
1131 */
1132
1133 #define KNOB_VALID_ADDRESS 0x1
1134 #define KNOB_VALID_ROLE 0x2
1135
1136 #define KNOB_ROLE_NONE 0x0
1137 #define KNOB_ROLE_INITIATOR 0x1
1138 #define KNOB_ROLE_TARGET 0x2
1139 #define KNOB_ROLE_BOTH 0x3
1140
1141 struct ccb_sim_knob_settings_spi {
1142 u_int valid;
1143 u_int initiator_id;
1144 u_int role;
1145 };
1146
1147 struct ccb_sim_knob_settings_fc {
1148 u_int valid;
1149 u_int64_t wwnn; /* world wide node name */
1150 u_int64_t wwpn; /* world wide port name */
1151 u_int role;
1152 };
1153
1154 struct ccb_sim_knob_settings_sas {
1155 u_int valid;
1156 u_int64_t wwnn; /* world wide node name */
1157 u_int role;
1158 };
1159 #define KNOB_SETTINGS_SIZE 128
1160
1161 struct ccb_sim_knob {
1162 struct ccb_hdr ccb_h;
1163 union {
1164 u_int valid; /* Which fields to honor */
1165 struct ccb_sim_knob_settings_spi spi;
1166 struct ccb_sim_knob_settings_fc fc;
1167 struct ccb_sim_knob_settings_sas sas;
1168 char pad[KNOB_SETTINGS_SIZE];
1169 } xport_specific;
1170 };
1171
1172 /*
1173 * Rescan the given bus, or bus/target/lun
1174 */
1175 struct ccb_rescan {
1176 struct ccb_hdr ccb_h;
1177 cam_flags flags;
1178 };
1179
1180 /*
1181 * Turn on debugging for the given bus, bus/target, or bus/target/lun.
1182 */
1183 struct ccb_debug {
1184 struct ccb_hdr ccb_h;
1185 cam_debug_flags flags;
1186 };
1187
1188 /* Target mode structures. */
1189
1190 struct ccb_en_lun {
1191 struct ccb_hdr ccb_h;
1192 u_int16_t grp6_len; /* Group 6 VU CDB length */
1193 u_int16_t grp7_len; /* Group 7 VU CDB length */
1194 u_int8_t enable;
1195 };
1196
1197 /* old, barely used immediate notify, binary compatibility */
1198 struct ccb_immed_notify {
1199 struct ccb_hdr ccb_h;
1200 struct scsi_sense_data sense_data;
1201 u_int8_t sense_len; /* Number of bytes in sense buffer */
1202 u_int8_t initiator_id; /* Id of initiator that selected */
1203 u_int8_t message_args[7]; /* Message Arguments */
1204 };
1205
1206 struct ccb_notify_ack {
1207 struct ccb_hdr ccb_h;
1208 u_int16_t seq_id; /* Sequence identifier */
1209 u_int8_t event; /* Event flags */
1210 };
1211
1212 struct ccb_immediate_notify {
1213 struct ccb_hdr ccb_h;
1214 u_int tag_id; /* Tag for immediate notify */
1215 u_int seq_id; /* Tag for target of notify */
1216 u_int initiator_id; /* Initiator Identifier */
1217 u_int arg; /* Function specific */
1218 };
1219
1220 struct ccb_notify_acknowledge {
1221 struct ccb_hdr ccb_h;
1222 u_int tag_id; /* Tag for immediate notify */
1223 u_int seq_id; /* Tar for target of notify */
1224 u_int initiator_id; /* Initiator Identifier */
1225 u_int arg; /* Response information */
1226 /*
1227 * Lower byte of arg is one of RESPONSE CODE values defined below
1228 * (subset of response codes from SPL-4 and FCP-4 specifications),
1229 * upper 3 bytes is code-specific ADDITIONAL RESPONSE INFORMATION.
1230 */
1231 #define CAM_RSP_TMF_COMPLETE 0x00
1232 #define CAM_RSP_TMF_REJECTED 0x04
1233 #define CAM_RSP_TMF_FAILED 0x05
1234 #define CAM_RSP_TMF_SUCCEEDED 0x08
1235 #define CAM_RSP_TMF_INCORRECT_LUN 0x09
1236 };
1237
1238 /* HBA engine structures. */
1239
1240 typedef enum {
1241 EIT_BUFFER, /* Engine type: buffer memory */
1242 EIT_LOSSLESS, /* Engine type: lossless compression */
1243 EIT_LOSSY, /* Engine type: lossy compression */
1244 EIT_ENCRYPT /* Engine type: encryption */
1245 } ei_type;
1246
1247 typedef enum {
1248 EAD_VUNIQUE, /* Engine algorithm ID: vendor unique */
1249 EAD_LZ1V1, /* Engine algorithm ID: LZ1 var.1 */
1250 EAD_LZ2V1, /* Engine algorithm ID: LZ2 var.1 */
1251 EAD_LZ2V2 /* Engine algorithm ID: LZ2 var.2 */
1252 } ei_algo;
1253
1254 struct ccb_eng_inq {
1255 struct ccb_hdr ccb_h;
1256 u_int16_t eng_num; /* The engine number for this inquiry */
1257 ei_type eng_type; /* Returned engine type */
1258 ei_algo eng_algo; /* Returned engine algorithm type */
1259 u_int32_t eng_memeory; /* Returned engine memory size */
1260 };
1261
1262 struct ccb_eng_exec { /* This structure must match SCSIIO size */
1263 struct ccb_hdr ccb_h;
1264 u_int8_t *pdrv_ptr; /* Ptr used by the peripheral driver */
1265 u_int8_t *req_map; /* Ptr for mapping info on the req. */
1266 u_int8_t *data_ptr; /* Pointer to the data buf/SG list */
1267 u_int32_t dxfer_len; /* Data transfer length */
1268 u_int8_t *engdata_ptr; /* Pointer to the engine buffer data */
1269 u_int16_t sglist_cnt; /* Num of scatter gather list entries */
1270 u_int32_t dmax_len; /* Destination data maximum length */
1271 u_int32_t dest_len; /* Destination data length */
1272 int32_t src_resid; /* Source residual length: 2's comp */
1273 u_int32_t timeout; /* Timeout value */
1274 u_int16_t eng_num; /* Engine number for this request */
1275 u_int16_t vu_flags; /* Vendor Unique flags */
1276 };
1277
1278 /*
1279 * Definitions for the timeout field in the SCSI I/O CCB.
1280 */
1281 #define CAM_TIME_DEFAULT 0x00000000 /* Use SIM default value */
1282 #define CAM_TIME_INFINITY 0xFFFFFFFF /* Infinite timeout */
1283
1284 #define CAM_SUCCESS 0 /* For signaling general success */
1285 #define CAM_FAILURE 1 /* For signaling general failure */
1286
1287 #define CAM_FALSE 0
1288 #define CAM_TRUE 1
1289
1290 #define XPT_CCB_INVALID -1 /* for signaling a bad CCB to free */
1291
1292 /*
1293 * CCB for working with advanced device information. This operates in a fashion
1294 * similar to XPT_GDEV_TYPE. Specify the target in ccb_h, the buffer
1295 * type requested, and provide a buffer size/buffer to write to. If the
1296 * buffer is too small, provsiz will be larger than bufsiz.
1297 */
1298 struct ccb_dev_advinfo {
1299 struct ccb_hdr ccb_h;
1300 uint32_t flags;
1301 #define CDAI_FLAG_NONE 0x0 /* No flags set */
1302 #define CDAI_FLAG_STORE 0x1 /* If set, action becomes store */
1303 uint32_t buftype; /* IN: Type of data being requested */
1304 /* NB: buftype is interpreted on a per-transport basis */
1305 #define CDAI_TYPE_SCSI_DEVID 1
1306 #define CDAI_TYPE_SERIAL_NUM 2
1307 #define CDAI_TYPE_PHYS_PATH 3
1308 #define CDAI_TYPE_RCAPLONG 4
1309 #define CDAI_TYPE_EXT_INQ 5
1310 #define CDAI_TYPE_NVME_CNTRL 6 /* NVMe Identify Controller data */
1311 #define CDAI_TYPE_NVME_NS 7 /* NVMe Identify Namespace data */
1312 #define CDAI_TYPE_MMC_PARAMS 8 /* MMC/SD ident */
1313 off_t bufsiz; /* IN: Size of external buffer */
1314 #define CAM_SCSI_DEVID_MAXLEN 65536 /* length in buffer is an uint16_t */
1315 off_t provsiz; /* OUT: Size required/used */
1316 uint8_t *buf; /* IN/OUT: Buffer for requested data */
1317 };
1318
1319 /*
1320 * CCB for sending async events
1321 */
1322 struct ccb_async {
1323 struct ccb_hdr ccb_h;
1324 uint32_t async_code;
1325 off_t async_arg_size;
1326 void *async_arg_ptr;
1327 };
1328
1329 /*
1330 * Union of all CCB types for kernel space allocation. This union should
1331 * never be used for manipulating CCBs - its only use is for the allocation
1332 * and deallocation of raw CCB space and is the return type of xpt_ccb_alloc
1333 * and the argument to xpt_ccb_free.
1334 */
1335 union ccb {
1336 struct ccb_hdr ccb_h; /* For convenience */
1337 struct ccb_scsiio csio;
1338 struct ccb_getdev cgd;
1339 struct ccb_getdevlist cgdl;
1340 struct ccb_pathinq cpi;
1341 struct ccb_relsim crs;
1342 struct ccb_setasync csa;
1343 struct ccb_setdev csd;
1344 struct ccb_pathstats cpis;
1345 struct ccb_getdevstats cgds;
1346 struct ccb_dev_match cdm;
1347 struct ccb_trans_settings cts;
1348 struct ccb_calc_geometry ccg;
1349 struct ccb_sim_knob knob;
1350 struct ccb_abort cab;
1351 struct ccb_resetbus crb;
1352 struct ccb_resetdev crd;
1353 struct ccb_termio tio;
1354 struct ccb_accept_tio atio;
1355 struct ccb_scsiio ctio;
1356 struct ccb_en_lun cel;
1357 struct ccb_immed_notify cin;
1358 struct ccb_notify_ack cna;
1359 struct ccb_immediate_notify cin1;
1360 struct ccb_notify_acknowledge cna2;
1361 struct ccb_eng_inq cei;
1362 struct ccb_eng_exec cee;
1363 struct ccb_smpio smpio;
1364 struct ccb_rescan crcn;
1365 struct ccb_debug cdbg;
1366 struct ccb_ataio ataio;
1367 struct ccb_dev_advinfo cdai;
1368 struct ccb_async casync;
1369 struct ccb_nvmeio nvmeio;
1370 struct ccb_mmcio mmcio;
1371 };
1372
1373 #define CCB_CLEAR_ALL_EXCEPT_HDR(ccbp) \
1374 bzero((char *)(ccbp) + sizeof((ccbp)->ccb_h), \
1375 sizeof(*(ccbp)) - sizeof((ccbp)->ccb_h))
1376
1377 __BEGIN_DECLS
1378 static __inline void
cam_fill_csio(struct ccb_scsiio * csio,u_int32_t retries,void (* cbfcnp)(struct cam_periph *,union ccb *),u_int32_t flags,u_int8_t tag_action,u_int8_t * data_ptr,u_int32_t dxfer_len,u_int8_t sense_len,u_int8_t cdb_len,u_int32_t timeout)1379 cam_fill_csio(struct ccb_scsiio *csio, u_int32_t retries,
1380 void (*cbfcnp)(struct cam_periph *, union ccb *),
1381 u_int32_t flags, u_int8_t tag_action,
1382 u_int8_t *data_ptr, u_int32_t dxfer_len,
1383 u_int8_t sense_len, u_int8_t cdb_len,
1384 u_int32_t timeout)
1385 {
1386 csio->ccb_h.func_code = XPT_SCSI_IO;
1387 csio->ccb_h.flags = flags;
1388 csio->ccb_h.xflags = 0;
1389 csio->ccb_h.retry_count = retries;
1390 csio->ccb_h.cbfcnp = cbfcnp;
1391 csio->ccb_h.timeout = timeout;
1392 csio->data_ptr = data_ptr;
1393 csio->dxfer_len = dxfer_len;
1394 csio->sense_len = sense_len;
1395 csio->cdb_len = cdb_len;
1396 csio->tag_action = tag_action;
1397 csio->priority = 0;
1398 #if defined(BUF_TRACKING) || defined(FULL_BUF_TRACKING)
1399 csio->bio = NULL;
1400 #endif
1401 }
1402
1403 static __inline void
cam_fill_ctio(struct ccb_scsiio * csio,u_int32_t retries,void (* cbfcnp)(struct cam_periph *,union ccb *),u_int32_t flags,u_int tag_action,u_int tag_id,u_int init_id,u_int scsi_status,u_int8_t * data_ptr,u_int32_t dxfer_len,u_int32_t timeout)1404 cam_fill_ctio(struct ccb_scsiio *csio, u_int32_t retries,
1405 void (*cbfcnp)(struct cam_periph *, union ccb *),
1406 u_int32_t flags, u_int tag_action, u_int tag_id,
1407 u_int init_id, u_int scsi_status, u_int8_t *data_ptr,
1408 u_int32_t dxfer_len, u_int32_t timeout)
1409 {
1410 csio->ccb_h.func_code = XPT_CONT_TARGET_IO;
1411 csio->ccb_h.flags = flags;
1412 csio->ccb_h.xflags = 0;
1413 csio->ccb_h.retry_count = retries;
1414 csio->ccb_h.cbfcnp = cbfcnp;
1415 csio->ccb_h.timeout = timeout;
1416 csio->data_ptr = data_ptr;
1417 csio->dxfer_len = dxfer_len;
1418 csio->scsi_status = scsi_status;
1419 csio->tag_action = tag_action;
1420 csio->priority = 0;
1421 csio->tag_id = tag_id;
1422 csio->init_id = init_id;
1423 }
1424
1425 static __inline void
cam_fill_ataio(struct ccb_ataio * ataio,u_int32_t retries,void (* cbfcnp)(struct cam_periph *,union ccb *),u_int32_t flags,u_int tag_action __unused,u_int8_t * data_ptr,u_int32_t dxfer_len,u_int32_t timeout)1426 cam_fill_ataio(struct ccb_ataio *ataio, u_int32_t retries,
1427 void (*cbfcnp)(struct cam_periph *, union ccb *),
1428 u_int32_t flags, u_int tag_action __unused,
1429 u_int8_t *data_ptr, u_int32_t dxfer_len,
1430 u_int32_t timeout)
1431 {
1432 ataio->ccb_h.func_code = XPT_ATA_IO;
1433 ataio->ccb_h.flags = flags;
1434 ataio->ccb_h.retry_count = retries;
1435 ataio->ccb_h.cbfcnp = cbfcnp;
1436 ataio->ccb_h.timeout = timeout;
1437 ataio->data_ptr = data_ptr;
1438 ataio->dxfer_len = dxfer_len;
1439 ataio->ata_flags = 0;
1440 }
1441
1442 static __inline void
cam_fill_smpio(struct ccb_smpio * smpio,uint32_t retries,void (* cbfcnp)(struct cam_periph *,union ccb *),uint32_t flags,uint8_t * smp_request,int smp_request_len,uint8_t * smp_response,int smp_response_len,uint32_t timeout)1443 cam_fill_smpio(struct ccb_smpio *smpio, uint32_t retries,
1444 void (*cbfcnp)(struct cam_periph *, union ccb *), uint32_t flags,
1445 uint8_t *smp_request, int smp_request_len,
1446 uint8_t *smp_response, int smp_response_len,
1447 uint32_t timeout)
1448 {
1449 #ifdef _KERNEL
1450 KASSERT((flags & CAM_DIR_MASK) == CAM_DIR_BOTH,
1451 ("direction != CAM_DIR_BOTH"));
1452 KASSERT((smp_request != NULL) && (smp_response != NULL),
1453 ("need valid request and response buffers"));
1454 KASSERT((smp_request_len != 0) && (smp_response_len != 0),
1455 ("need non-zero request and response lengths"));
1456 #endif /*_KERNEL*/
1457 smpio->ccb_h.func_code = XPT_SMP_IO;
1458 smpio->ccb_h.flags = flags;
1459 smpio->ccb_h.retry_count = retries;
1460 smpio->ccb_h.cbfcnp = cbfcnp;
1461 smpio->ccb_h.timeout = timeout;
1462 smpio->smp_request = smp_request;
1463 smpio->smp_request_len = smp_request_len;
1464 smpio->smp_response = smp_response;
1465 smpio->smp_response_len = smp_response_len;
1466 }
1467
1468 static __inline void
cam_fill_mmcio(struct ccb_mmcio * mmcio,uint32_t retries,void (* cbfcnp)(struct cam_periph *,union ccb *),uint32_t flags,uint32_t mmc_opcode,uint32_t mmc_arg,uint32_t mmc_flags,struct mmc_data * mmc_d,uint32_t timeout)1469 cam_fill_mmcio(struct ccb_mmcio *mmcio, uint32_t retries,
1470 void (*cbfcnp)(struct cam_periph *, union ccb *), uint32_t flags,
1471 uint32_t mmc_opcode, uint32_t mmc_arg, uint32_t mmc_flags,
1472 struct mmc_data *mmc_d,
1473 uint32_t timeout)
1474 {
1475 mmcio->ccb_h.func_code = XPT_MMC_IO;
1476 mmcio->ccb_h.flags = flags;
1477 mmcio->ccb_h.retry_count = retries;
1478 mmcio->ccb_h.cbfcnp = cbfcnp;
1479 mmcio->ccb_h.timeout = timeout;
1480 mmcio->cmd.opcode = mmc_opcode;
1481 mmcio->cmd.arg = mmc_arg;
1482 mmcio->cmd.flags = mmc_flags;
1483 mmcio->stop.opcode = 0;
1484 mmcio->stop.arg = 0;
1485 mmcio->stop.flags = 0;
1486 if (mmc_d != NULL) {
1487 mmcio->cmd.data = mmc_d;
1488 } else
1489 mmcio->cmd.data = NULL;
1490 mmcio->cmd.resp[0] = 0;
1491 mmcio->cmd.resp[1] = 0;
1492 mmcio->cmd.resp[2] = 0;
1493 mmcio->cmd.resp[3] = 0;
1494 }
1495
1496 static __inline void
cam_set_ccbstatus(union ccb * ccb,cam_status status)1497 cam_set_ccbstatus(union ccb *ccb, cam_status status)
1498 {
1499 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1500 ccb->ccb_h.status |= status;
1501 }
1502
1503 static __inline cam_status
cam_ccb_status(union ccb * ccb)1504 cam_ccb_status(union ccb *ccb)
1505 {
1506 return ((cam_status)(ccb->ccb_h.status & CAM_STATUS_MASK));
1507 }
1508
1509 void cam_calc_geometry(struct ccb_calc_geometry *ccg, int extended);
1510
1511 static __inline void
cam_fill_nvmeio(struct ccb_nvmeio * nvmeio,u_int32_t retries,void (* cbfcnp)(struct cam_periph *,union ccb *),u_int32_t flags,u_int8_t * data_ptr,u_int32_t dxfer_len,u_int32_t timeout)1512 cam_fill_nvmeio(struct ccb_nvmeio *nvmeio, u_int32_t retries,
1513 void (*cbfcnp)(struct cam_periph *, union ccb *),
1514 u_int32_t flags, u_int8_t *data_ptr, u_int32_t dxfer_len,
1515 u_int32_t timeout)
1516 {
1517 nvmeio->ccb_h.func_code = XPT_NVME_IO;
1518 nvmeio->ccb_h.flags = flags;
1519 nvmeio->ccb_h.retry_count = retries;
1520 nvmeio->ccb_h.cbfcnp = cbfcnp;
1521 nvmeio->ccb_h.timeout = timeout;
1522 nvmeio->data_ptr = data_ptr;
1523 nvmeio->dxfer_len = dxfer_len;
1524 }
1525
1526 static __inline void
cam_fill_nvmeadmin(struct ccb_nvmeio * nvmeio,u_int32_t retries,void (* cbfcnp)(struct cam_periph *,union ccb *),u_int32_t flags,u_int8_t * data_ptr,u_int32_t dxfer_len,u_int32_t timeout)1527 cam_fill_nvmeadmin(struct ccb_nvmeio *nvmeio, u_int32_t retries,
1528 void (*cbfcnp)(struct cam_periph *, union ccb *),
1529 u_int32_t flags, u_int8_t *data_ptr, u_int32_t dxfer_len,
1530 u_int32_t timeout)
1531 {
1532 nvmeio->ccb_h.func_code = XPT_NVME_ADMIN;
1533 nvmeio->ccb_h.flags = flags;
1534 nvmeio->ccb_h.retry_count = retries;
1535 nvmeio->ccb_h.cbfcnp = cbfcnp;
1536 nvmeio->ccb_h.timeout = timeout;
1537 nvmeio->data_ptr = data_ptr;
1538 nvmeio->dxfer_len = dxfer_len;
1539 }
1540 __END_DECLS
1541
1542 #endif /* _CAM_CAM_CCB_H */
1543