1 /*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ 33 #define _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ 34 35 /* 36 * PCI/PCIe-Gen1 Host Bridge definitions. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 42 #include "bhnd_pcivar.h" 43 44 DECLARE_CLASS(bhnd_pci_hostb_driver); 45 46 /** 47 * PCI/PCIe-Gen1 endpoint-mode device quirks 48 */ 49 enum { 50 /** No quirks */ 51 BHND_PCI_QUIRK_NONE = 0, 52 53 /** 54 * SBTOPCI_PREF and SBTOPCI_BURST must be set on the 55 * SSB_PCICORE_SBTOPCI2 register. 56 */ 57 BHND_PCI_QUIRK_SBTOPCI2_PREF_BURST = (1<<1), 58 59 /** 60 * SBTOPCI_RC_READMULTI must be set on the SSB_PCICORE_SBTOPCI2 61 * register. 62 */ 63 BHND_PCI_QUIRK_SBTOPCI2_READMULTI = (1<<2), 64 65 /** 66 * PCI CLKRUN# should be disabled on attach (via CLKRUN_DSBL). 67 * 68 * The purpose of this work-around is unclear; there is some 69 * documentation regarding earlier Broadcom drivers supporting 70 * a "force CLKRUN#" *enable* registry key for use on mobile 71 * hardware. 72 */ 73 BHND_PCI_QUIRK_CLKRUN_DSBL = (1<<3), 74 75 /** 76 * On PCI-attached BCM4321CB* boards, the PCI latency timer must be set 77 * to 960ns on initial attach. 78 */ 79 BHND_PCI_QUIRK_960NS_LATTIM_OVR = (1<<4), 80 81 /** 82 * TLP workaround for unmatched address handling is required. 83 * 84 * This TLP workaround will enable setting of the PCIe UR status bit 85 * on memory access to an unmatched address. 86 */ 87 BHND_PCIE_QUIRK_UR_STATUS_FIX = (1<<5), 88 89 /** 90 * PCI-PM power management must be explicitly enabled via 91 * the data link control register. 92 */ 93 BHND_PCIE_QUIRK_PCIPM_REQEN = (1<<6), 94 95 /** 96 * Fix L0s to L0 exit transition on SerDes <= rev9 devices. 97 * 98 * On these devices, PCIe/SerDes symbol lock can be lost if the 99 * reference clock has not fully stabilized during the L0s to L0 100 * exit transition, triggering an internal reset of the chip. 101 * 102 * The SerDes RX CDR phase lock timers and proportional/integral 103 * filters must be tweaked to ensure the CDR has fully stabilized 104 * before asserting receive sequencer completion. 105 */ 106 BHND_PCIE_QUIRK_SDR9_L0s_HANG = (1<<7), 107 108 /** 109 * The idle time for entering L1 low-power state must be 110 * explicitly set (to 114ns) to fix slow L1->L0 transition issues. 111 */ 112 BHND_PCIE_QUIRK_L1_IDLE_THRESH = (1<<8), 113 114 /** 115 * The ASPM L1 entry timer should be extended for better performance, 116 * and restored for better power savings. 117 */ 118 BHND_PCIE_QUIRK_L1_TIMER_PERF = (1<<9), 119 120 /** 121 * ASPM and ECPM settings must be overridden manually. 122 * Applies to 4311B0/4321B1 chipset revisions. 123 * 124 * The override behavior is controlled by the BHND_BFL2_PCIEWAR_OVR 125 * flag; if set, ASPM and CLKREQ should be explicitly disabled. If not 126 * set, they should be explicitly enabled. 127 * 128 * Attach/Resume: 129 * - Update SRSH_ASPM_ENB flag in the SPROM ASPM register. 130 * - Update SRSH_CLKREQ_ENB flag in the SPROM CLKREQ_REV5 131 * register. 132 * - Update ASPM L0S/L1 flags in PCIER_LINK_CTL register. 133 * - Clear CLKREQ (ECPM) flag in PCIER_LINK_CTL register. 134 * 135 * Suspend: 136 * - Clear ASPM L1 flag in the PCIER_LINK_CTL register. 137 * - Set CLKREQ (ECPM) flag in the PCIER_LINK_CTL register. 138 * 139 * Detach: 140 * - Set CLKREQ (ECPM) flag in the PCIER_LINK_CTL register. 141 */ 142 BHND_PCIE_QUIRK_ASPM_OVR = (1<<10), 143 144 /** 145 * A subset of Apple devices did not set the BHND_BFL2_PCIEWAR_OVR 146 * flag in SPROM; on these devices, the BHND_BFL2_PCIEWAR_OVR flag 147 * should always be treated as if set. 148 */ 149 BHND_PCIE_QUIRK_BFL2_PCIEWAR_EN = (1<<11), 150 151 /** 152 * Fix SerDes polarity on SerDes <= rev9 devices. 153 * 154 * The SerDes polarity must be saved at device attachment, and 155 * restored on suspend/resume. 156 */ 157 BHND_PCIE_QUIRK_SDR9_POLARITY = (1<<12), 158 159 /** 160 * SerDes PLL down flag must be manually disabled (by ChipCommon) on 161 * resume. 162 */ 163 BHND_PCIE_QUIRK_SERDES_NOPLLDOWN = (1<<13), 164 165 /** 166 * On attach and resume, consult the SPROM to determine whether 167 * the L2/L3-Ready w/o PCI RESET work-around must be applied. 168 * 169 * If L23READY_EXIT_NOPRST is not already set in the SPROM, set it 170 */ 171 BHND_PCIE_QUIRK_SPROM_L23_PCI_RESET = (1<<14), 172 173 /** 174 * The PCIe SerDes PLL must be configured to not retry the startup 175 * sequence upon frequency detection failure on SerDes <= rev9 devices 176 * 177 * The issue this workaround resolves is unknown. 178 */ 179 BHND_PCIE_QUIRK_SDR9_NO_FREQRETRY = (1<<15), 180 181 /** 182 * Common flag for quirks that require PCIe SerDes TX 183 * drive strength adjustment. 184 * 185 * Only applies to PCIe >= rev10 devices. 186 */ 187 BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST = (1<<16), 188 189 /** 190 * On Apple BCM94322X9 devices, the PCIe SerDes TX drive strength 191 * should be set to 700mV. 192 * 193 * The exact issue is unknown, but presumably this workaround 194 * resolves signal integrity issues with these devices. 195 * 196 * Only applies to PCIe >= rev10 devices. 197 */ 198 BHND_PCIE_QUIRK_SERDES_TXDRV_700MV = (1<<17) | 199 BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST, 200 201 /** 202 * On some Apple BCM4331-based devices, the PCIe SerDes TX drive 203 * strength should be set to its maximum. 204 * 205 * The exact issue is unknown, but presumably this workaround 206 * resolves signal integrity issues with these devices. 207 */ 208 BHND_PCIE_QUIRK_SERDES_TXDRV_MAX = (1<<18) | 209 BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST, 210 211 /** 212 * PCIe cores prior to rev18 do not support an MRRS larger than 213 * 128 bytes. 214 */ 215 BHND_PCIE_QUIRK_MAX_MRRS_128 = (1<<19), 216 217 /** 218 * The PCIe core should be configured with an MRRS of 512 bytes. 219 */ 220 BHND_PCIE_QUIRK_DEFAULT_MRRS_512 = (1<<20), 221 }; 222 223 /** 224 * bhnd_pci_hostb driver instance state. 225 */ 226 struct bhnd_pcihb_softc { 227 struct bhnd_pci_softc common; /**< common bhnd_pci state */ 228 device_t dev; 229 device_t pci_dev; /**< host PCI device */ 230 uint32_t quirks; /**< hostb device quirks */ 231 232 /** BHND_PCIE_QUIRK_ASPM_OVR state. */ 233 struct { 234 /** 235 * ASPM/CLKREQ override setting. 236 * 237 * If true, ASPM/CLKREQ should be overridden as enabled. 238 * If false, ASPM/CLKREQ should be overridden as disabled. 239 */ 240 bool aspm_en; 241 } aspm_quirk_override; 242 243 /** BHND_PCIE_QUIRK_SDR9_POLARITY state. */ 244 struct { 245 /** 246 * PCIe SerDes RX polarity. 247 * 248 * Initialized to the PCIe link's RX polarity 249 * at attach time. This is used to restore the 250 * correct polarity on resume */ 251 bool inv; 252 } sdr9_quirk_polarity; 253 }; 254 255 256 #endif /* _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ */ 257